WO2005043601A3 - Apparatus and method for forming compound integrated circuits - Google Patents

Apparatus and method for forming compound integrated circuits Download PDF

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Publication number
WO2005043601A3
WO2005043601A3 PCT/US2004/036739 US2004036739W WO2005043601A3 WO 2005043601 A3 WO2005043601 A3 WO 2005043601A3 US 2004036739 W US2004036739 W US 2004036739W WO 2005043601 A3 WO2005043601 A3 WO 2005043601A3
Authority
WO
WIPO (PCT)
Prior art keywords
master modules
master
integrated circuits
forming compound
circuits
Prior art date
Application number
PCT/US2004/036739
Other languages
French (fr)
Other versions
WO2005043601A2 (en
Inventor
Stephen Charles Bateman
Douglas John Bailey
David John Coakley
Original Assignee
Chipx Inc
Stephen Charles Bateman
Douglas John Bailey
David John Coakley
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipx Inc, Stephen Charles Bateman, Douglas John Bailey, David John Coakley filed Critical Chipx Inc
Publication of WO2005043601A2 publication Critical patent/WO2005043601A2/en
Publication of WO2005043601A3 publication Critical patent/WO2005043601A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology

Abstract

The present invention provides for modularized circuits (500) and methods of manufacturing both modularized circuits ('master modules') (520, 522, 524, 526) and compound Ics (504). These master modules are designed to minimize waste and to evenly distribute power throughout its structure. Also, a number of master modules (520, 522, 524, 526) and a compound IC (504) composed of a group of these master modules are structured to minimize the effects of mechanically-induced stresses. In one embodiment, a substrate includes master modules (520, 522, 524, 526) distributed over a surface of the substrate, wherein each master module includes, for example, one or more logic circuits, a memory, an input interface and an output interface.
PCT/US2004/036739 2003-11-03 2004-11-03 Apparatus and method for forming compound integrated circuits WO2005043601A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US70137503A 2003-11-03 2003-11-03
US10/701,375 2003-11-03

Publications (2)

Publication Number Publication Date
WO2005043601A2 WO2005043601A2 (en) 2005-05-12
WO2005043601A3 true WO2005043601A3 (en) 2005-12-01

Family

ID=34551413

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/036739 WO2005043601A2 (en) 2003-11-03 2004-11-03 Apparatus and method for forming compound integrated circuits

Country Status (1)

Country Link
WO (1) WO2005043601A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI823617B (en) * 2022-10-14 2023-11-21 鯨鏈科技股份有限公司 Reconfigurable capacity memory and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6175952B1 (en) * 1997-05-27 2001-01-16 Altera Corporation Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions
US6226779B1 (en) * 1997-09-29 2001-05-01 Xilinx, Inc. Programmable IC with gate array core and boundary scan capability
US6480989B2 (en) * 1998-06-29 2002-11-12 Lsi Logic Corporation Integrated circuit design incorporating a power mesh
US6564364B1 (en) * 2000-11-15 2003-05-13 Reshape, Inc. Method and system for maintaining element abstracts of an integrated circuit netlist using a master library file and modifiable master library file

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6604228B1 (en) * 1996-05-28 2003-08-05 Altera Corporation Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions
US6175952B1 (en) * 1997-05-27 2001-01-16 Altera Corporation Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions
US6226779B1 (en) * 1997-09-29 2001-05-01 Xilinx, Inc. Programmable IC with gate array core and boundary scan capability
US6480989B2 (en) * 1998-06-29 2002-11-12 Lsi Logic Corporation Integrated circuit design incorporating a power mesh
US6564364B1 (en) * 2000-11-15 2003-05-13 Reshape, Inc. Method and system for maintaining element abstracts of an integrated circuit netlist using a master library file and modifiable master library file

Also Published As

Publication number Publication date
WO2005043601A2 (en) 2005-05-12

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