WO2005045692A2 - Data processing device and method - Google Patents
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- WO2005045692A2 WO2005045692A2 PCT/EP2004/009640 EP2004009640W WO2005045692A2 WO 2005045692 A2 WO2005045692 A2 WO 2005045692A2 EP 2004009640 W EP2004009640 W EP 2004009640W WO 2005045692 A2 WO2005045692 A2 WO 2005045692A2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
- G06F15/8023—Two dimensional arrays, e.g. mesh, torus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
- G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
- G06F15/17381—Two dimensional, e.g. mesh, torus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
- G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
- G06F15/803—Three-dimensional arrays or hypercubes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
- G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
- G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates to recon igurable computing.
- the present invention relates to improvements in the architecture of r ⁇ configurable devices.
- Reconfigurable data procesing arrays are known in the art. Reference is being made to the previous applications and/or publications of the present applicant/assignee all of which are encorporated herein by way of reference. Accordingly, the devices described hereinafter may be multidimensional (n>l) arrays comprinsing coarse grained computing and/or data operation elements allowing for runtime reconfiguration of the entire array or parts thereof, preferably in response to a signal indicating reconfigurability to a loading unit (CT, CM or the like) .
- a first way to improve the known devices is to improve the functionability of each single processor element. It has been previously suggested to include a ring-memory (R ⁇ NGSPEICHER) in the array, to store instructions in the ring-memory and to provide a pointer that points to one of the ring-memory address- ses so as to select an instruction to be carried out next . Furthermore, it has been suggested to provide at least onerada shadow configuration" and to switch over between several configurations /shadow configurations. Anotrher or additional suggestions has been designated as suntwave reconfiguration". hile these known methods improve the performance of a recon ⁇ figurable device, there seems to be both a need and a possibility for further improvements.
- a PAE might e.g. comprise 4 input ports and 4 output ports.
- Embedded with each PAE is the_FREG -path newly named DF with its dataflow capabilities, like MERGE, SWAP, DEMUX as well as ELUT.
- Ri2 and Ri3 are typically fed to the DF path which output is Ro2 and Ro3.
- Ri2 and Ri3 can serve as inputs for the ALU as well. This extension is needed to provide a suitable amount of ALU inputs if Function Folding (as described later) is used. In this mode Ro2 and Ro3 serve as additional outputs.
- each data register (Ri or Ro) is- an event port (Ei or Eo) .
- Tt is possible, albeit not necessary to implement an additional data and event bypass BRiO-l f BEiO-.
- the decision depends on how often Function Folding will be used and how many inputs and outputs are required in average.
- SIMD operation is implemented, in the ALUs to support 8 and 16 bit wide data words for i.e. graphics and imaging.
- each PAE operates as a data flow node as defined by Perti-Nets. (Some arrays might have parts that have other functions and should thus be not considered as a standard PAE) .
- a Petri-Net supports a calculation of multiple inputs and produces one single output. Special for a Perti-Net is, that the operation is delayed until all input data is available.
- the quantity of data - and events is defined by the data and control flow, the availability is displayed at runtime by the handshake protocol RDY/ACK.
- the thick arbor indicates the operation
- the dot on the right side indicates that the- operation is delayed until all inputs are available.
- Enhancing the basic methodology function folding supports multiple operations - maybe even sequential - instead of one, defined as a Cycle. It is important that the basics of Petri- Nets remain unchanged.
- Typical PAE-like Petri-Nets consume one input packet per one operation. For sequential operation multiple reads of the same input packet are supported. However, the interface model again keeps unchanged.
- the internal registers can be implemented in different ways, e.g. in one of the following two:
- Each register (r' ) has a valid bit which is set as soon as data has-been written into the register and reset after the data has been read. Data cannot be written if valid is set, data can not be read if valid is not set. This approach implements a 100% compatible dataflow behaviour.
- the registers have no associated valid bits.
- the PAE operates as a sequencer, whereas at the edges of the PAE (the bus connects) the paradigm is changed to the XPP-like dataflow behaviour.
- PAE For allowing complex function like i.e. address generation as well as algorithms like "IMEC'-like data stream operations the PAE has not only 4 instruction registers implemented but 8, whereas the maximum bus-clock vs. PAE-clock ration is limited to a factor of 4 for usual function folding.
- a program counter is used to select a certain instruction within the instruction memory.
- a finite state machine controls the program counter.
- This finite state machine now checks whether or not all conditions for the instruction in RC (PC) , that is the instruction, onto which the PC (Program Counter) points, are fulfilled. To do so, the respective RDY- and/or ACK- handshakes of the in- and/or outputs needed for the execution of the instructions are checked. Furthermore, the valid-flags of the internal registers to be read (RD0..RDn) are checked so as to control whether or not they are set, and the valid-flags of those internal registers (RD0..RDn) into which is to be written, are checked whether they are not set. -If one of the conditions is not fulfilled, the instructions will not be carried out. PC is controlled to count further, the instruction is. skipped and the next instruction is selected and checked as described.
- each RC is assigned an entry in an evaluation mask field, the length of which corresponds to the maximum number of states to be tested; therefore, for every possible RDY- or ACK-trigger- signal (as well the RDY/ACKs of the triggers) as well as for every valid bit in RD0...RDn two bits are available indicating whether or not the respective signal is to be set or not set; or, whether the state of the signal is unimportant for the execution of the instruction.
- the mask shows only some entries.
- both the state of the trigger (set, not set) as well as the value of the trigger (trigger value) can be tested via RDY-value.
- an instruction of the set of all executables is selected.
- the arbiter controls the instruction multiplexer via ISel according to the transferral of the selected instructions to the PAE.
- the Line Control has one single line of Boolean test logic for every single instruction.
- ExOR-gate e
- OR-gate 4-
- a selection is carried out, whether the checked signal is relevant (don't care) .
- the results of all checked signals are ANDed.
- a logic 1 at the output of the AND-gates (&) shows an executable instruction.
- An arbiter having one of a number of possible implementations such as a priority arbiter, Round-Robin-Arbiter and so forth, selects one instruction for execution out of all executable instructions.
- Advantages of the method are: Significantly fast, in view of the fact that one instruction can be carried out in every single clock Reduced power consumption, since no energy is wasted on disgaxded—cycles which is in particular advantageous to the static power dissipation. Similar hardware expense as in the sequential solution when using small and medium sized configuration memories (RC) therefor similar costs.
- RC configuration memories
- All busses assigned to a certain PAE are connected to the input registers (IR) or the output registers of the PAE are connected to all busses respectively (compare for example DE 100 50 442.6 or the XPP/VPU-handbooks of the applicant).
- PAEs in particular FF PAEs
- FF PAEs allow for a depopulation of bus interconnects, in particular, if more IR/OR will be available compared to the State of the Art of the XPP as previously known.
- the depopulation that is the reductions of the possibilities to connect the IR or ER onto the busses can be symmetrically or asymmetrically.
- the depopulation will typically amount to 20 to 70 %. It is significant that the depopulation will not or not significantly effect the interconnectability and/or the routability of an algorithm in a negative way.
- the method of depopulation is particularly relevant in view of the fact that several results can be achieved.
- the hardware- expense and thus the costs of the bus systems can be reduced significantly; the speed of the busses is increased since the gate delay is reduced by the minimisation of connecting points; simultaneously, the power consumption of the busses is reduced.
- the known PAE has a main data flow in the direction from top to bottom to the main ALU in the PAE-core.
- data channels are placed additionally transmitting data along the main data flow direction, once the same direction as the main data flow (FREG) and once in the reverse direction (BREG) .
- FREG main data flow
- BREG reverse direction
- data busses are provided that run in the reverse direction of the main data flow of the PAE and onto which the PAE as well as FREG and BREG are connected.
- the architecture of the State of the Art requires eight data busses for each PAE side as well as four transfer channels for FREG/BREG for typical applications.
- the bus system of the State of the Art has switching elements, register elements (R) , each at the side of the PAEs.
- the switching elements allow for the disruption of a bus segment or- disconnection to a neighbouring bus
- the register elements allow the construction of an efficient pipelining by transferring data through the register, so as to allow for higher transferral band-width.
- the typical latency in vertical direction for next-neighbour-transmitting is 0 per segment, however is 0,5-1 in horizontal direction per segment and higher frequencies .
- the double-ALU structure has been further developed to an ALU-PAE having inputs and outputs in both directions.
- automatic routers as well as hand-routed applications, further additional significant improvements of the network topology can be shown.
- register and switching elements in the busses in the middle of the PAE instead of at the sides thereof (see Fig, below) .
- the perferred embodiment comprises two ALUs, one of these being "complete" and having all necessary functions, for example-multiplication and BarrelShift while the second has a reduced instruction set eliminating functions that require larger arrays such as multiplication and BarrelShift.
- the second ALU is in a way replacing BYPASS (as drawn) .
- BYPASS as drawn
- Both ALUs comprise additional circuits to transfer data between the busses so as to implement the function of the bypass.
- Configurable multiplexers within the ALU are connected so that ALU inputs are bypassing the ALU and are directly connected to their outputs.
- a MOVE instruction, stored in RcO.. Ren is transferring within the respective processing clock of the function fol the data according to the input specified within the instruction to the specified output.
- MUL is implemented as one single opcode which is pipelined over two stages.
- MUL takes its operands from the input registers Ri and stores the results into internal data registers Rd.
- VALID is set if • data is stored into Rd.
- ADD or any other Opcode, such as BSFT) uses the result in Rd if VALID is set; if not the execution is skipped according to the specified VALID behaviour.
- the timing changes for all OpCodes ' if the MUL instruction is used inside a PAE configuration. In this case all usually single cycle OpCodes will change to pipelined 2 cycle OpCodes. The change is achieved by inserting a bypass able multiplexer into the data stream as well as into control.
- OpCodes besides MUL which require 2 clock cycles for execution e.g. BSTF
- the architecture must be modified to allow at least 3 data writes to registers after the second internal clock cycle.
- the data path output multiplexer gets 2 times larger as well as the bus system to the output registers (OR) and the feedback path to the internal data registers (Rd) . If accordingly defined for the OpCodes, more than 4 internal registers can be used without increasing the complexity by using enables (en) to select the specific register to write in the data. Multiple registers are connected to the same bus, e.g. RdO, Rd4, Rd8, Rdl2. However not all combinations of register transfers are possible with this structure. If e.g. MUL uses RdO and Rdl the following registers are blocked for the OpCode executed in parallel: Rd4, 5, 8, 9, 12, 13.
- the SEQ-PAEs are not build from scratch. Instead such a tile will be build up by a closely coupling of a ALU-PAE and neighboring RAM-PAE, which can be seen in Figure 1.
- the extended version of the ALU-PAE is ' given in Figure 2. To the right border the registers which are controlling the different modules can be seen. Those registers will be used in normal- as well as in SEQ-mode. Therefore the appropriate control signals from the local configuration manager and the RAM- PAE are first merged by OR-Gates and then are forwarded to the register whereas it has to be ensured that in normal mode the signals from the RAM-PAE are .0 and vice versa.
- Figure 2 Enhanced Version of the ALU-PAE
- data can be processed during one or two cycles by the ALU-PAE depending on the selected arithmetic function. Due to the auto synchronization feature of the XPP and due to the fact that in normal mode a successive operation will not start before the previous one is finished, it does not really care if an operation lasts one or two clock cycles. Whereas the tile is working in SEQ mode there is a difference since we assume to have a pipeline character. This means that a one cycle operation could run in parallel with a two cycle module where the operation would be executed in stage two at this time. Due to the limited multiplexing capacities of a word - 16 Bit - only one result could be written to the connected registers whereas the other one would be lost. In general there are three possibilities to solve this problem.
- the second idea could be to recognize such a situation in the decode stage of the pipeline. If a two cycle instruction is directly followed by an instruction accessing a one stage arithmetic unit it has to be delayed by one clock cycle as well.
- the program counter for the next clock cycle will be calculated. This means that it will be either incremented by 1 via a local adder or one of the program counters from the decode or execution stage 2 will be selected.
- the program counter of the execution stage thereby provides the address if a call instruction occurred whereas the program counter of- -the execution stage provides the PC if there has been a conditional jump.
- the branch address can'ei- ther be calculated out of the current PC and a value which either be an immediate value or a value from a internal registers of the ALU-RAM - indirect addressing mode - or an absolute value. This e.g. is necessary if there is return from a subroutine ' to the previous context whereas the according absolute PC will be provided by the stack bank.
- the instruction coming from the Gode bank will be decoded.
- Necessary control signals and, if needed, the immediate, value for the internal execution stage 1 as well as for the execution stage 1 of the ALU-PAE will be generated.
- the signals include the control information for the multiplexers and gating stages of section two of the ALU-PAE, the operation selection of the ALU's tiles, e.g. signed or unsigned multiplication, and the information whether the stack pointer (SP) should be in/decremented or kept unchanged in the next stage- depending on the fact if the instruction is either a call or jump, in case a call instruction occurred a new PC will be calculated in parallel and delivered to the fetch stage.
- SP stack pointer
- the read address and read enable signal to the data bank will be generated in case of a load instruction.
- the execution stage 1 which by the way is the first stage available on the ALU as well as on the RAM-PAE, the control signals for execution stage 2 of the ALU-PAE are generated. Those...signal will take care that the correct output of one of the arithmetical tiles will be selected and written to the enabled registers. If the instruction should be a conditional jump or return the stack pointer will be modified in this stage. In parallel the actual PC will be saved to the stack bank at the address give by the Rsp EXl register in case of a branch. Otherwise, in case of a return, the read address as well as the read enable .signal will be applied to the stack bank.
- execution stage 2 the value of the PC will be calculated and provided to the multiplexer in the fetch stage in case of a jump.
- write address arid write enable signal to the data bank are generated if data from the ALU have to be saved.
- FIG. 3 Overview of the RAM-PAE Pipeline actions
- ⁇ IR Instruction Register DR: Data Register DB: Data Bank
- SBR Store/Branch Register Instruction: Load value from data bank to R[n]
- the XPP-II structure of the PAEs consumes much area for FREG and BREG and their associated bus interfaces. I-h addition feed backs through the FREGs require the insertion of registers into the feedback path, which result not only in an increased latency but also in a negative impact onto the throughput and performance of the XPP.
- a new PAE structure and arrangement is proposed with the expectation to minimize latency and optimize the bus interconnect structure to achieve an optimized area.
- the XPP-III PAE structure does not include BREGs any more.
- the ALUs are alternating flipped horizontally which leads to improved placement and routing capabilities especially for feedback paths i.e. of loops.
- Each PAE contains now two ALUs and two BP paths, one from top to bottom. and one flipped from bottom to top.
- registers are implemented in the vertical busses which can be switched on by configuration for longer paths. This registers can furthermore be preloaded by configuration which requires a significant amount of silicon area. It is proposed to not implement registers in the busses any more, but to use an enhanced DF or Bypass (PB) part within the PAEs which is able to reroute a path to the same bus using the DF or BP internal registers instead:
- PB Bypass
- This method saves a significant amount of static resources in silicon but requires dedicated PAE resources at runtime.
- the RAM-PAE is enhanced by an feedback from the data output to the address input through a register (FF) to supply subsequent address within each stage. Furthermore additional address inputs from the PAE array can cause conditional jumps, data output will generate event signals for the PAE array. Associated counters which can be reloaded and stepped by the memory output generate address input for conditional jumps (i.e. end of line, end of frame of a video picture) .
- a typical—RAM—PAE implementation has about 16-32 data bits but only 8-12 address bits. To optimize the range of input vectors it is therefore suggested to insert some multiplexers at the address inputs to select between multiple vectors, whereas the multiplexers are controlled by some of the output data bits.
- the memory organisation suggested here may be as follows: 8 address bits 24 data bits (22 used) 4 next address 8 multiplexer selectors 6 counter control (shared with 4 additional next address) 4 output
- the width of the counters is according to the bus width of the data busses.
- the proposed memory organisation is as follows: 8 address bits 16 data bits (16 used) 4 next address 4 multiplexer selectors 3 counter control (shared with 3 additional next address) 4 output
- address generators to support e.g. 1 to 3 dimensional addressing directly without any ALU-PAE resources.
- the address generation is then done by 3 counters, each of them has e.g. configurable base- address, length and step width.
- the first counter (CNT1) has a step input to be controlled by the array of ALU-PAEs. Its carry is connected to the step input of CNT2,. which carry again is connected to the step input of CNT3.
- Each counter generates carry if the value is equal to the configured length. Immediately with carry the counter is reset to its configured base address. One input is dedicated for addresses from the array of ALU- PAEs which can be added to the values of the counters. If one or more counters are not used they are configured to be zero. In addition CNT1 supports generation of bit reversal addressing by supplying multiple carry modes.
- the IOAG allows the split and merge of such smaller data words. Since the new PAE structure allows 4 input and 4 output ports, the IOAG can support word splitting and merging as follows:
- Input ports are. merged within the IOAG for word writes to the 10.
- For output ports the read word is split according tb the configured word width.
- PAEs and busses are build to perform depending on the workload. Therefore the clock frequency is configurable according to the data bandwidth, in addition clock gating for registers is supported, busses are decoupled using row of AND gates. Dynamically clock pulses are gated, whenever no data can be processed.
- the voltage is scaled in an advanced architecture. Within the 4S project such methods are evaluated and commercially usable technologies are researched.
- a) memory coupling for large data streams The most convenient method with the highest performance is a direct cache coupling, whereas an AMBA based memory coupling will be sufficient for the beginning (to be discussed with ATAIR)
- b) register coupling for small data and irregular MAC operations Preferable is a direct coupling into the processors registers with an implicit synchronisation in the OF-stage of the processor pipeline. However coupling via load/store- or in/out-commands as external registers is acceptable with the penalty of a higher latency which causes some performance limitation.
- the ALU-PAE comprises 3 paths: ALU arithmetic, logic and data flow handling BP bypass
- each of the paths contains 2 data busses and 1 event bus.
- the busses of the DF path can be rerouted to the ALU path by configuration.
- The. ALU path comprises 12 data registers: RiO-3 Input data register 0-3 from bus RvO-3 Virtual output data register 0-3 to bus Rd0-3 Internal general purpose register 0-3 ViO-3 V event input 0-3 from bus UiO-3 U event input 0-3 from bus EvO-3 Virtual V event output register 0-3 to bus EuO-3 Virtual U event output register 0-3 to bus FuO-3 FvO-3 Internal Flag u and v registers according to the XPP-II PAE's event busses , J Ace Accumulator
- Rlc Loop Counter configured by CM
- CM not accessible through ALU-PAE itself. Will be decremented according to JL opcode. Is reloaded after value 0 is reached.
- Rjb Jump-Back register to define the number of used entries in Rc[0..7]. It is not accessible through ALU-PAE itself. If Rpp is equal to Rjb, Rpp is immediately reset to 0. The jump back can be bound to a condition i.e. an incoming event. If the condition is missing, the jump back will be delayed.
- Each input register, Ri can be configured to work in- one of two different modes: ⁇
- a data packet is taken read from the bus if the register is empty, an ACK handshake is generated. If the register is not empty ACK the data is not latched and ACK is not generated.. If the register contains data, it can be read once. Immediately with the read access the register is marked as empty. An empty register cannot be read.
- the input interface is according to the bus protocol definition: A data packet is taken read from the bus if the register is empty, an ACK handshake is generated. If the register is not empty ACK the data is not latched and ACK is not generated.
- the register contains data it can be read multiple times during a sequence.
- each data register can be individually selected.
- Three address opcode form is used, r t * - r sl , r s0 .
- An virtual output register is selected by adding o' behind the register. The result will be stored in rt and copied to the virtual output register r v as well according to the rule op out (r v , r t ) — r sl , r s0 .
- Events are used equal to data registers. All input and internal events can be addressed directly, output events are used whenever an ⁇ o' is added behind the event.
- an accumulator register is available which can be addressed by just one set bit for the result register (ao) and- operand register (ai) .
- Operand register 2 defines the accordingly other operand.
- Jt is to be noted that it has to be clarified whether a real Accumula tor mode makes sense or j ust a MAC-command should be implemented to handle the multiply accumulate in a single com ⁇ mand consuming two clock cycles with an implicit hidden accumulator access .
- the FF-PAE To access the PStack, the FF-PAE must be in the Fast-Parameter Mode. Each read access to Ri3 is redirected to read, from the PStack, whereas after each read access the pointer incremented with one. ' There is no check for an overflow of the PStack pointer implemented, an overflow is regarded as a program bug. Programming Error
- n 1 Transitions n:l transitions are not supported within the busses any more. Alternatively simple writes to multiple output registers Ro and event outputs Eo are supported.
- the Virtual Output registers (Rv) and Virtual Event (Ev) are translated to real Output registers (Ro) and real Events (Eo) , whereas a virtual register can be mapped to multiple output registers .
- the Multi-Config Mode allows for selecting 1 out of maximum stored configurations. Incoming events .on Fui0,l and Fvi0,l select one of the 4 configurations. Only one Event shall be active at a clock, cycle.
- each event points to a specific memory address.
- Long configurations may use more than 3 opcode by using the next code segments as well. In this case, the according events can not be used .
- Source registers can be Ri and Rd
- target registers are Rv and
- Each operation can target a Virtual Output Register Rv by adding an out tag as a target identifier to the opcode: op (r t , ro t ) ⁇ - r a , r b
- the SKIPE command supports conditional execution. Either an event or ALU flag is tested for a specific value. Depending on the check either the next two addresses are executed (Rpp + 1). or skipped (Rpp + 3) . If an incoming event is checked, the program execution stops until the event is arrived at the event port (RDY handshake set) . ,.,
- SKIPE supports conditional execution of any OpCode which is not larger than two memory entries.
- the PAE can operate at a configurable clock frequency of lx Bus Clock 2x Bus Clock 4x Bus Clock [8x Bus Clock]
- the DataFlow path comprises the data registers Bri0..3 and Bro0..3 as well as the event register Bui/Bvi0..3 and Buo/BvoO ..3.
- the main purpose of the DF path is to establish bus connections in the vertical direction.
- the path includes a 4 stage FIFO for each of the data and event paths.
- the DF path supports numerous instructions, whereas the instruction is selected by ' configuration and only one of them can be performed during a configuration, function folding is not available.
- Parameters and constants can be updated fast and synchronous using input register Ri3 and event input Ei7.
- data packets at the input register Ri3 are copied subsequently into Rd3, Rd2 and Rdl at each access of the according register by the PAE, if the event Ei7 is set. Afterwards all input data at Ri3 is propagated to the output register Ro3, also the Eo7 event output is set, to indicate following PAEs the occurrence of a fast parameter update, which allows to chain PAEs together (i.e. in a multi-TAP FIR filter) and updating all parameters in the chain.
- Ei7 must be 0 for at least one clock cycle to indicate the end of a running parameter update and the start of a new update.
- the IOAGs are located in the RAM-PAEs and share, the same registers to the busses.
- An IOAG comprises 3 counters with forwarded carries. The values of the counters and an immediate address input from the array are added to generate the address .
- One counter offers reverse carry capabilities.
- Multidimensional addressing using IOAG internal counters xD means ID, 2D, 3D xD circular Multidimensional addressing using IOAG internal counters, after overflow counters reload with base address xD plus immedixD plus a value from the PAE array ate Stack decrement after "push” operations increment after "read” operations
- the address is generated in the array and directly fed through the adder to the address output. All counters are. disabled and set to 0.
- Counters are enabled depending on the required dimension (x- di ensions require x counters) . For each counter a base address- and the step width as well as the maximum address are configured. Each carry is forwarded to the next higher and enabled counter; after carry the counter is reloaded with the start address.
- a carry at the highest enabled counter generates an event, counting stops.
- One counter (CNTl) is used to decrement after data writes and increment after data reads.
- the base value of the counter can either be configured (base address) or loaded by the PAE array.
- carry is forwarded from LSB to MSB. Forwarding the carry to the opposite direction (reverse carry) allows generating address patterns which are very well suited for applications like FFT and the like. The carry is discarded at MSB.
- the counter is implemented to allow reverse carry at least for STEP values of -2, -1, +1, +2.
- Each ALU-PAE at the left or right edge of the array can be closely coupled to the neighbouring RAM-PAEs as an IP option, thus allowing for configure a sequencer.
- the data and opcode width of the sequencer is l ⁇ bits.
- the ALU-PAEs can operate exactly as array internal ALU-PAEs but have several extensions. Operation is Sequencer mode the register file is 8 data registers wide, Fu and Fv flags are used as carry, sign, null, overflow, and parity ALU flag word.
- the address width is accordingly l ⁇ bit.
- the RAM- PAE size is limited it is segmented into 16 segments. Those segments are used for code, data and stack and must be individually preloaded by the compiler.
- the compiler has to take care that necessary data segments are preloaded and available. For cost reasons there is no automatic. TLB installed.
- Code segments behave accordingly to data segments.
- the compiler has to preload them before execution jumps into them. Also jumps are physically direct addressed, due to the absence of TLBs again.
- mapping is fixed by the compiler.
- CodeBank CB
- SB StackBank
- Memory banks are updates in terms of loaded or flushed in the background by a DMA engine controlled by the following opcodes LOADDSEG Loads and validates a data/auxiliary/stack bank ; STOREDSEG Stores and invalidates a data/auxiliary/stack bank LOADCSEG Loads and validates a code bank
- the address generators in the IOAG interfaces can be reused as DMA engine.
- Memory banks can be specifically validated or invalidated as follows: VALIDATESSEG Validates a bank INVALIDATESEG Invalidates a bank
- the bank pointers are added to the address of any memory access. Since the address pointer can be larger than the 6 bits addressing a 64 line range, segment -boarders are not "sharp", which means, can be crossed without any limitation. However the programmer or compiler has to take care that no damage occurs while crossing them. If an invalid segment is reached a flag or trap is generated indicating the fault, eventually just wait states are inserted if a segment preload is running already in the background.
- IOAGs may comprise a 4-8 stage data output buffer to balance external latency and allow reading the same data address directly after the data has been written, regardless of external bus or memory latencies (up to the number of buffer stages) .
- Event output Eo II -> 0 Rpp++ rs: source register rt: target register et4: target event Input Registers: Ri / Rd
- Input Flags Output Flags : Mode SEQ sign, zero FF sign, zero -> F / Eo-
- Event output Eo II , 12 -> 0
- CodeBank is not influenced.
- CodeBank is not influenced.
- Rpp++ rs source register rt: target register as: add/substract mode es4: event source
- Rpp++ rt target register rs: source register et4 :. target event Input Registers: Ri / Rd, Ri / Rd
- Rpp-t-t- rs source register rt: target register et4: target event Input Registers:
- Output 02 Rpp++ rt: target register rs: source register es4: source event
- Event E - es3 nnn Ei [nnn ] Wait for incoming event of defined value. Acknowledge all incoming events .
- FIG. 1 depicts a cut-out of a reconfigurable array with a set of functional units (FU) .
- Each functional unit encloses one routing unit (RU) and additional functional modules (FMs) .
- the enclosed functional modules are used to manipulate data and characterize the type of the FU.
- the RU contains an interconnect matrix which' is able to route each input port to any desirable output ports. All FUs are connected through point-to-point links whereas each is composed of two half-duplex links and able to transport the data in both directions at the same time.
- the routing technique described in this document is instruction based which means that each routing process must be started by an instruction. If the user wants to establish a routing between two cells, he has to bring a specific instruction into the source cell. The hardware within the array calculates based on the instruction fields values the desired routing direction and establishes the logic stream. The routing process happens stepwise from one functional unit to another whereby each cell decides which direction should be taken next.
- On the way to an established route we defined three valuable states of the routing resources.
- the first state is the physical route or link. This means that the resources of this route are not used and available to routing processes.
- the second state is named temporal route or link. This state describes the temporarily not available link, which means that this link is in use for routing purposes but the mentioned routing is not confirmed yet . The problem here is that this route can be confirmed in the future or released if the successor cells are able to realise the desired routing.
- the last state is the logical route or link. This state represents an established route on the array which is able to transport calculation data.
- This routing technique uses coordinates on the array to calculation routings.
- Each FU possesses unique coordinate's und on the basis of this information it is able to determine the routing direction to each desired cell within the array.
- This concept is the basis for the adaptive runtime routing described in this document.
- the needed control logic for adaptive routing is implemented within the routing unit, especially within the routing controller which controls the interconnect matrix at runtime. Therefore the routing controller is able to analyze the incoming data of all input ports of the concerned FU and come to a decision what to do next.
- each input port owns so called in-registers (InReg) .
- InRegCtrl InReg-controllers implemented
- FSMs finite state machines
- InCtrl in-controllers
- InCtrl in-controller
- Important requirement for requesting of new routings is that the mentioned input resource (InReg, InRegCtrl) are not used and so in the state of physical link.
- InCtrl gets requests of all InRegCtrls all over the time and forwards one request after another to the routing controller (RoutCtrl) . ; The selection which InRegCtrl should be served first is dependant on the routing priority of the input link and/or which input link was served last. Based on the coordinate information of the target cell and the coordinates of the actual FU the RoutCtrl calculates the forward direction for the requested input link. Thereby the RoutCtrl takes into account additional parameters like optimum bit (will be described later) , the network utilisation towards the desired direction, etc.
- RoutCtrl forwards the request with additional information about the output port to the interconnect matrix, which connects the input port with calculated output port. If this is done the RoutCtrl signals the successful. routing operation to InCtrl. Because the actual reached routing state is not final it is necessary to store the actual state. This happens within the queue-request-registerfile (QueueRRF) . Therefore the InCtrl is directly connected to the QueueRRF and is able to store the desired information. At this point the related input and output links reach the temporal link state and are temporarily not available for other routing processes.
- the InCtrl Due the fact that the QueueRRF is able to store more than one routing entry, the InCtrl is able to hold multiple routing processes at the same time. But for the purpose of high hardware area consumption the direction calculation is realized once within the RoutCtrl.
- the established temporal routing stays stored within the QueueRRF till the point the successor cell acknowledges the routing.
- the InCtrl clear the according entry in the QueueRRF and signals the ' successful routing to the InCtrl .
- the InRegCtrl changes into the state logical route and signal the predecessor cell the successfully finished routing process. The other case can happen if the successor cell is not able to establish the desired route.
- the InCtrl forwards a new request to the RoutCtrl based on the QueueRRF-entry. This request leads to new routing suggestion which will be stored within the QueueRRF.
- InCtrl If all available and expedient directions are checked and routing trials failed the InCtrl signals to InRegCtrl the failed routing. The InCtrl signals the same routing miss to the predecessor cell and finishes the routing process in the current cell.
- the routing unit establishes a desired routing. Those exceptions affect the source and the target cell. The exception in both cases is that as well the source cell as the target cell do not need to route the started/ending routing through the interconnect matrix.
- the InRegCtrl doesn't have to acknowledge the successful routing the predecessor it just has to consume the actual routing instruction in the InReg instead. This happens after the InCtrl signals the successful routing. Additionally the InReg switches the output multiplexer associated to the output port of the FM and finishes the routing establishment. The information needed the switch the right output multiplexer gets the InCtrl from the RoutCtrl.
- the second exception concerns the target routing cell.
- the InRegCtrl has the last job to finish the routing process by deleting the routing instruction and going to logical state.
- end packets For releasing of the logically established routings we introduced special instructions, so called end packets.
- the only purpose of those instructions is the route-dissolving by inject the necessary end packet into the logic established routing.
- the second way for route releasing is the local route releasing. Here it is possible to release single established routes between output and input ports of FMs. The end packets are not propagated through the FMs. In this case the end packet will be consumed by the last InRegCtrl .
- the internal RU communication is similar to the routing process. If the InRegCtrl determines incoming end packet and the InRegCtrl is in the logic route state, the InRegCtrl forwards the route release request to the InCtrl. The InCtrl clears the entries either within the interconnect matrix or within the input multiplexers registers or within the output multiplexer registers. Meanwhile the InRegCtrl consumes (in case of the local end packet and last cell in the chain) the instruction and goes to the idle state. If the end packet was a global instruction the InRegCtrl forwards alway the end packet to the successor. , '
- the instructions For the purpose of priority control, we introduced a priority system to influence the order in which the RU serves the incoming routing requests. Therefore the instructions contain priority fields which describe the priority level. Higher values in this field result in higher priority und will be preferred by the RU during the runtime routing.
- the priority field has direct influence on the selection of the incoming routing requests from the InRegCtrls to InCtrl.
- Some inner configuration communication streams require strictly defined latency to reach the desired performance. Therefore it is very important to keep the maximum register chain length. To decrease the latency of the routed streams its is necessary to ensure that the array chose always the best routing between source and target, but this requirement may lead to not routable streams if this feature will be always required. To ease this problem we introduced a special bit within the routing instruction, so called optimum bit (OptBit) . This bit has to be activated if the optimum routing is definitely required. In this case the array tries to reach this requirement und delivers an ⁇ interrupt if fails.
- the alternative to reach the required latency is the speed path counter.
- This counter gives the possibility to bypass a specific number of registers before buffering again. Therefore we defined a reference value and the counter value. Both numbers are stored within the instruction field. Each passed cell respective the RU compares the counter value and the reference- value. If both values are equal then the actual cell buffers the stream and resets the counter. If the counter is smaller than the reference value the current buffer will be bypassed and the counter incremented by one. In this way it is possible to bypass a number of buffers which equals exactly to reference value.
- one single point-to- point link connects two neighbor cells respective the RUs within those cells.
- One coarse-grained link consists of a set of wires, e.g. 32 wires for one 32 link, and additionally protocol signals. The whole vector is handled by a single set of control signals which makes this communication resource not usable for multi-grained communication.
- Multi-grained Routing In order to route multi-grained channels it's necessary to use the coarse grained links to support the routing process.
- the idea is to route two links in parallel, one coarse-grained link to support multi-grained routing and one multi-grained link, which will contain the final multi-grained stream. Therefore we defined a two packet routing instruction with needed data fields .
- the first instruction packet contains - compared to coarsegrained routing instruction - additional bit mask to specify used multi- grained sub-links and multi-grained link ID to identify the associated multi-grained link.
- the other features like described above - optimum bit, speed path, priority routing - are support in this routing mode as well.
- the routing process within the RU is performed similar " to the coarsegrained routing.
- the first packet which arrives in a cell is analyzed by the InRegCtrl and a request is generated and forwarded to the InCtrl.
- InCtrl forwards the request to the RoutCtrl and wait for the acknowledgement. If RoutCtrl finds one possible routing direction, the InCtrl gets the successful acknowledgement and the temporal routing will be established by the RoutCtrl. Next, the actual job will be stored within the QueueRRP and the InCtrl waits for the acknowledgement from the successor cell. If RoutCtrl is not able to find a possible routing, the InCtrl gets negative acknowledgement and which will be forwarded to the associated InRegCtrl, which generates the route unable signal to the predecessor cell and quits the routing process within this cell.
- the InRegCtrl clears the related entry in the QueueRRP and finishes the routing. If the successor cell is not able to establish a rout to the destination cell, it generates negative acknowledgement signal. Hereupon, the InCtlr starts new request to the RoutCtrl and handle the responses as described above.
- the difference between the coarse-grained routing and multi-grained routing lies in the handling of the multi-grained interconnect matrix. Each strip of a multi-grained link is handled separately.
- the RoutCtrl forwards the switch request to the strip matcher.
- Strip matcher has the job to analyze the input strips and to match them to the output link according to already used strips. What strip matcher is doing is to map the problem of strip matching into the time domain and switches the needed switchboxes for each strip separately one after another.
Abstract
Description
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US8812820B2 (en) | 2014-08-19 |
JP2007504688A (en) | 2007-03-01 |
JP4700611B2 (en) | 2011-06-15 |
US20100241823A1 (en) | 2010-09-23 |
WO2005045692A3 (en) | 2006-03-02 |
EP1676208A2 (en) | 2006-07-05 |
US20090172351A1 (en) | 2009-07-02 |
US20140359255A1 (en) | 2014-12-04 |
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