WO2005045904A3 - Notch-free etching of high aspect soi structures using a time division multiplex process and rf bias modulation - Google Patents

Notch-free etching of high aspect soi structures using a time division multiplex process and rf bias modulation Download PDF

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Publication number
WO2005045904A3
WO2005045904A3 PCT/US2004/034803 US2004034803W WO2005045904A3 WO 2005045904 A3 WO2005045904 A3 WO 2005045904A3 US 2004034803 W US2004034803 W US 2004034803W WO 2005045904 A3 WO2005045904 A3 WO 2005045904A3
Authority
WO
WIPO (PCT)
Prior art keywords
notch
time division
high aspect
division multiplex
soi structures
Prior art date
Application number
PCT/US2004/034803
Other languages
French (fr)
Other versions
WO2005045904A2 (en
Inventor
Sunil Srinivasan
David Johnson
Russell Westerman
Original Assignee
Unaxis Usa Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unaxis Usa Inc filed Critical Unaxis Usa Inc
Priority to DE602004018531T priority Critical patent/DE602004018531D1/en
Priority to EP04817803A priority patent/EP1676302B1/en
Priority to JP2006536773A priority patent/JP2007509506A/en
Publication of WO2005045904A2 publication Critical patent/WO2005045904A2/en
Publication of WO2005045904A3 publication Critical patent/WO2005045904A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Abstract

The present invention provides a method and an apparatus for reducing, or eliminating, the notching observed in the creation of SOI structures on a substrate when plasma etching through an alternating deposition/etch process by modulating the RF bias that is applied to the cathode. Modulation of the bias voltage to the cathode is accomplished either discretely, between at least two frequencies, or continuously during the alternating deposition/etch process.
PCT/US2004/034803 2003-10-21 2004-10-19 Notch-free etching of high aspect soi structures using a time division multiplex process and rf bias modulation WO2005045904A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE602004018531T DE602004018531D1 (en) 2003-10-21 2004-10-19 TOOL-FREE SEEDING OF SOI STRUCTURES WITH HIGH SEULTIPLEXED PROCESSES AND HF PREMODULATION
EP04817803A EP1676302B1 (en) 2003-10-21 2004-10-19 Notch-free etching of high aspect soi structures using a time division multiplex process and rf bias modulation
JP2006536773A JP2007509506A (en) 2003-10-21 2004-10-19 High-aspect SOI structure notch-etching using time division multiplexing and RF bias modulation

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US51293303P 2003-10-21 2003-10-21
US60/512,933 2003-10-21
US10/968,823 US20050112891A1 (en) 2003-10-21 2004-10-18 Notch-free etching of high aspect SOI structures using a time division multiplex process and RF bias modulation
US10/968,823 2004-10-18

Publications (2)

Publication Number Publication Date
WO2005045904A2 WO2005045904A2 (en) 2005-05-19
WO2005045904A3 true WO2005045904A3 (en) 2005-09-09

Family

ID=34576731

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/034803 WO2005045904A2 (en) 2003-10-21 2004-10-19 Notch-free etching of high aspect soi structures using a time division multiplex process and rf bias modulation

Country Status (6)

Country Link
US (2) US20050112891A1 (en)
EP (1) EP1676302B1 (en)
JP (1) JP2007509506A (en)
AT (1) ATE418157T1 (en)
DE (1) DE602004018531D1 (en)
WO (1) WO2005045904A2 (en)

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US7771606B2 (en) * 2007-02-22 2010-08-10 Applied Materials, Inc. Pulsed-plasma system with pulsed reaction gas replenish for etching semiconductors structures
US7737042B2 (en) * 2007-02-22 2010-06-15 Applied Materials, Inc. Pulsed-plasma system for etching semiconductor structures
US7718538B2 (en) * 2007-02-21 2010-05-18 Applied Materials, Inc. Pulsed-plasma system with pulsed sample bias for etching semiconductor substrates
KR20100128333A (en) * 2008-03-21 2010-12-07 어플라이드 머티어리얼스, 인코포레이티드 Method and apparatus of a substrate etching system and process
JP2010118549A (en) * 2008-11-13 2010-05-27 Tokyo Electron Ltd Plasma etching method and plasma etching device
JP2011100760A (en) * 2009-11-04 2011-05-19 Ulvac Japan Ltd Etching method
US8658541B2 (en) * 2010-01-15 2014-02-25 Applied Materials, Inc. Method of controlling trench microloading using plasma pulsing
US9373521B2 (en) 2010-02-24 2016-06-21 Tokyo Electron Limited Etching processing method
US9105705B2 (en) * 2011-03-14 2015-08-11 Plasma-Therm Llc Method and apparatus for plasma dicing a semi-conductor wafer
US8802545B2 (en) * 2011-03-14 2014-08-12 Plasma-Therm Llc Method and apparatus for plasma dicing a semi-conductor wafer
JP5718124B2 (en) * 2011-03-30 2015-05-13 株式会社日立ハイテクノロジーズ Plasma processing apparatus and plasma processing method
US8758638B2 (en) * 2011-05-10 2014-06-24 Applied Materials, Inc. Copper oxide removal techniques
US8609548B2 (en) * 2011-06-06 2013-12-17 Lam Research Corporation Method for providing high etch rate
US20130119018A1 (en) * 2011-11-15 2013-05-16 Keren Jacobs Kanarik Hybrid pulsing plasma processing systems
US8883028B2 (en) * 2011-12-28 2014-11-11 Lam Research Corporation Mixed mode pulsing etching in plasma processing systems
GB2499816A (en) * 2012-02-29 2013-09-04 Oxford Instr Nanotechnology Tools Ltd Controlling deposition and etching in a chamber with fine time control of parameters and gas flow
JP5841917B2 (en) 2012-08-24 2016-01-13 株式会社日立ハイテクノロジーズ Plasma processing apparatus and plasma processing method
JP5967710B2 (en) * 2012-09-28 2016-08-10 サムコ株式会社 End point detection method of plasma etching
CN103928283B (en) * 2013-01-10 2016-06-15 中微半导体设备(上海)有限公司 The method of the radio-frequency pulse power match of a kind of application of vacuum chamber and device thereof
US9653316B2 (en) * 2013-02-18 2017-05-16 Tokyo Electron Limited Plasma processing method and plasma processing apparatus
JP6173086B2 (en) * 2013-07-19 2017-08-02 キヤノン株式会社 Etching method of silicon substrate
US20150371889A1 (en) * 2014-06-20 2015-12-24 Applied Materials, Inc. Methods for shallow trench isolation formation in a silicon germanium layer
US9691625B2 (en) * 2015-11-04 2017-06-27 Lam Research Corporation Methods and systems for plasma etching using bi-modal process gas composition responsive to plasma power level
KR102124407B1 (en) * 2016-01-18 2020-06-18 주식회사 히타치하이테크 Plasma processing method and plasma processing device
US11170981B2 (en) * 2019-09-17 2021-11-09 Tokyo Electron Limited Broadband plasma processing systems and methods
US11295937B2 (en) * 2019-09-17 2022-04-05 Tokyo Electron Limited Broadband plasma processing systems and methods
RU2715412C1 (en) * 2019-11-26 2020-02-28 Акционерное общество «Российская корпорация ракетно-космического приборостроения и информационных систем» (АО «Российские космические системы») Multilayer switching board of microwave-hybrid integrated microcircuit of space designation and method for its production (versions)
CN114467169A (en) * 2020-09-02 2022-05-10 株式会社日立高新技术 Plasma processing apparatus and plasma processing method
US11917806B2 (en) 2021-08-12 2024-02-27 Changxin Memory Technologies, Inc. Method of manufacturing semiconductor structure and semiconductor structure

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Also Published As

Publication number Publication date
EP1676302B1 (en) 2008-12-17
DE602004018531D1 (en) 2009-01-29
EP1676302A2 (en) 2006-07-05
US20050112891A1 (en) 2005-05-26
US20070175856A1 (en) 2007-08-02
JP2007509506A (en) 2007-04-12
WO2005045904A2 (en) 2005-05-19
ATE418157T1 (en) 2009-01-15

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