WO2005055325A1 - トランジスタおよびそのゲート絶縁膜の成膜に用いるcvd装置 - Google Patents
トランジスタおよびそのゲート絶縁膜の成膜に用いるcvd装置 Download PDFInfo
- Publication number
- WO2005055325A1 WO2005055325A1 PCT/JP2004/018051 JP2004018051W WO2005055325A1 WO 2005055325 A1 WO2005055325 A1 WO 2005055325A1 JP 2004018051 W JP2004018051 W JP 2004018051W WO 2005055325 A1 WO2005055325 A1 WO 2005055325A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- transistor
- gate insulating
- film
- insulating film
- electrode
- Prior art date
Links
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 36
- 239000011737 fluorine Substances 0.000 claims abstract description 36
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims description 32
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 24
- 238000005229 chemical vapour deposition Methods 0.000 claims description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 230000005669 field effect Effects 0.000 claims description 7
- 239000004973 liquid crystal related substance Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 230000006866 deterioration Effects 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 104
- 239000010410 layer Substances 0.000 description 12
- 239000000758 substrate Substances 0.000 description 8
- 239000010409 thin film Substances 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000004140 cleaning Methods 0.000 description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000007743 anodising Methods 0.000 description 3
- 238000011156 evaluation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- -1 fluorine ions Chemical class 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
Definitions
- the present invention relates to an improvement in a transistor, and more particularly to a measure for improving reliability in a case where the transistor is continuously driven at a relatively high temperature for a long time.
- Amorphous silicon nitride films formed by CVD Chemical Vapor Deposition
- CVD Chemical Vapor Deposition
- the NF Use a cleaning gas such as CF or SF to clean the inside of the deposition chamber of a CVD system.
- Patent Document 1 describes that the concentration of fluorine contained in the semiconductor film is suppressed to 1.0 ⁇ 10 19 atoms ms cm 3 or less. Further, as a means for suppressing the fluorine concentration, it is described that a residual plasma is removed by generating hydrogen plasma after cleaning the inside of a film formation chamber. By suppressing the concentration of fluorine contained in the semiconductor film, an increase in the shift amount of the threshold voltage when the substrate is operated for 10 minutes at a substrate temperature of 25.0 ⁇ 3.0 ° C. It is said that it is possible to improve the reliability of the transistor by suppressing it.
- Patent Document 1 JP-A-2002-329869 (page 2, FIG. 1)
- Patent Document 2 Japanese Patent Application Laid-Open No. 2003-124469 (Page 2, FIG. 1)
- the present invention has been made in view of the above points, and a main object of the present invention is to provide a transistor which suppresses deterioration in characteristics due to fluorine contained in a thin film constituting the transistor.
- the purpose is to provide excellent reliability even when driven at high temperatures for a long time.
- the present invention focuses on a gate insulating film of a transistor, and adjusts the concentration of fluorine contained in the gate insulating film to 1 ⁇ 10 2 ° a tom S / C m 3 or less, More preferably, IX
- the gate insulating film is formed using a CVD apparatus
- an electrode in a film forming chamber of the CVD apparatus is used.
- the pole surface is a non-porous layer.
- carrier traps due to fluorine at the gate insulating film interface in contact with the semiconductor film are reduced, and the on-current characteristics of the transistor are improved.
- the fluorine ions in the gate insulating film are reduced, and the threshold characteristics of the transistor are reduced. Not only is improved, but also excellent reliability is obtained even when driven for a long time under relatively high temperature.
- fluorine is formed on a porous layer (for example, formed by anodizing protection film treatment) on an electrode surface in the film formation chamber. Since the root cause of the residue can be eliminated, the occurrence of transistor defects due to insufficient fluorine removal due to variations in processing conditions is compared to the case where the residual fluorine is removed using hydrogen plasma. That is, the decrease in yield can be suppressed.
- the transistor is a field-effect transistor.
- the gate insulating film is an amorphous silicon nitride film. Further, it is preferable that the gate insulating film is formed by a CVD method. Further, the above transistor is suitable for use as a switching element for a pixel electrode portion in a liquid crystal display device.
- the content fluorine concentration in the gate insulating film of the transistor, 1 X 10 20 ato ms / cm 3 or less, more preferably by the following 1 X 10 19 atoms / cm 3 good Not only can the initial characteristics be obtained, but also the reliability can be improved even when the device is driven continuously at a relatively high temperature for a long time, such as a liquid crystal display device.
- FIG. 1 is a cross-sectional view schematically showing an overall configuration of a field-effect thin film transistor according to an embodiment of the present invention.
- FIG. 2 is a schematic diagram showing an overall configuration of a CVD apparatus used for forming a gate insulating film.
- FIG. 3 is a cross-sectional view schematically showing a configuration of an anode surface in a film forming chamber of a CVD apparatus.
- FIG. 4 is a diagram schematically showing a configuration of an anode surface in a film forming chamber of a conventional CVD apparatus.
- FIG. 5 is a characteristic diagram showing a relationship between a concentration of fluorine contained in a gate insulating film and a threshold voltage of a transistor.
- FIG. 6 is a characteristic diagram showing a relationship between a concentration of fluorine contained in a gate insulating film and an on-current characteristic of a transistor.
- FIG. 1 schematically shows a cross section of a field-effect thin film transistor according to the present embodiment.
- This transistor is used, for example, as a switching element for a pixel electrode portion in a liquid crystal display device.
- the above-described transistor includes a strong insulating substrate (1) such as glass, for example, and a gate electrode (2) made of Ta, Al, Mo, or the like is formed on the substrate (1).
- a gate electrode (2) made of Ta, Al, Mo, or the like is formed on the substrate (1).
- a gate insulating film (3) made of, for example, an amorphous silicon nitride film is formed to a thickness of, for example, 4000 A over substantially the entire surface of the substrate (1).
- an amorphous silicon semiconductor film (4) as a semiconductor film is formed to a thickness of, for example, 2000A, centering on a portion corresponding to the gate electrode (2).
- an n + amorphous silicon semiconductor film (5) as a semiconductor film different from the amorphous silicon semiconductor film (4) is formed by doping with phosphorus.
- a gate electrode (2) is formed on the substrate (1) by patterning.
- the film forming chamber was cleaned with NF gas,
- a gate insulating film (3) is formed. Thereafter, a first semiconductor film for obtaining an amorphous silicon semiconductor film (4) and a second semiconductor film for obtaining an n + amorphous silicon semiconductor film (5) are formed. Thereafter, the laminated film including the first and second semiconductor films is patterned into an island shape, and first, an amorphous silicon semiconductor film (4) is formed.
- a source electrode (6) and a drain electrode (7) are formed on a predetermined portion of the gate insulating film (3) and on the laminated film. Then, the second semiconductor film is separated and etched using the patterns of the source electrode (6) and the drain electrode (7) to form an n + amorphous silicon semiconductor film (5). Thus, a field-effect thin film transistor is completed.
- an aluminum anode (52) having a number of gas supply holes (51) is arranged in the film forming chamber (50). Unlike the conventional case, the surface of the anode (52) is not subjected to the anodic oxidation protective film treatment, and is schematically shown in FIG. Layer (70) is exposed in a solid state.
- the surface of the aluminum layer (70) is formed on the surface of the aluminum layer (70) by anodizing the anodized protective film (61). Is formed, and since the anodized protective film (61) is porous, fluorine is absorbed in the pores, and immediately after the fluorine is absorbed, a large amount is formed in the film forming chamber (51) after cleaning. Causes fluorine to remain.
- the surface of the anode (52) is By making it powerful, that is, by not forming the conventional anodized protective film (61) on the surface of the aluminum layer (70), the above-mentioned root cause is eliminated.
- a new non-porous layer is formed on the surface of the aluminum layer (70).
- a high-frequency power source [RF power source] is used.
- output 1000 W of] the flow rate of the gas is 3LZmin [However, 1. 013 X 10 5 Pa, 0 ° C ] was subjected to a Wataru connexion hydrogen plasma treatment for 60 seconds with the proviso that, a gate insulating film (3) was 3 ⁇ 10 2 ° atomsZcm 3 .
- a value of 7 ⁇ 10 18 -1 ⁇ 10 19 atoms / cm 3 was constantly obtained under the same conditions.
- the semiconductor film is an amorphous silicon semiconductor film (4) and n
- the present invention can also be applied to a transistor in which the semiconductor film is a single layer.
- the gate insulating film (3) is an amorphous silicon nitride film.
- the present invention relates to the case where the gate insulating film (3) is made of, for example, amorphous silicon
- the present invention can also be applied to transistors other than the amorphous silicon nitride film, such as an amorphous silicon film and an amorphous silicon oxide film.
- the concentration of fluorine contained in the gate insulating film (3) is reduced.
- the surface of the positive electrode (52) of (50) is made of a non-porous layer.
- means for reducing the concentration of force-containing fluorine other means are not particularly limited, and other means may be appropriately employed. Can be.
- the plasma CVD method is used to form the gate insulating film (3) of the transistor. It can be applied when using sputtering such as putter and reactive sputtering, and even in the case of CVD, the gate insulating film can be formed by a method other than plasma CVD, such as thermal CVD or optical CVD. It can be applied to a transistor on which a film is formed. Further, in the above embodiment, the case of a transistor used for a switching element for a pixel electrode portion in a liquid crystal display device has been described. However, the present invention is not limited to a transistor used for other purposes. Can also be applied.
- the characteristic diagram of FIG. 5 shows the initial characteristics between the concentration of fluorine contained in the gate insulating film and the threshold voltage of the transistor.
- the characteristic diagram of FIG. 6 shows the concentration of fluorine contained in the gate insulating film and the transistor. The initial characteristics between the on-current characteristics and the on-current characteristics of the transistors are shown.
- the initial transistor characteristics are good when the concentration of fluorine contained is 1 X 10 2 atoms / cm 3 or less, more preferably 1 X 1 O 19 atoms / cm 3 or less.
- the present invention is applicable to general transistors, and is particularly suitable for transistors that are driven for a long time at a relatively high temperature, such as those used as switching elements for pixel electrodes in liquid crystal display devices. It is.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/595,640 US7557416B2 (en) | 2003-12-03 | 2004-12-03 | Transistor and CVD apparatus used to deposit gate insulating film thereof |
US12/474,353 US7893509B2 (en) | 2003-12-03 | 2009-05-29 | Transistor and CVD apparatus used to deposit gate insulating film thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003404895A JP2005167019A (ja) | 2003-12-03 | 2003-12-03 | トランジスタおよびそのゲート絶縁膜の成膜に用いるcvd装置 |
JP2003-404895 | 2003-12-03 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/595,640 A-371-Of-International US7557416B2 (en) | 2003-12-03 | 2004-12-03 | Transistor and CVD apparatus used to deposit gate insulating film thereof |
US12/474,353 Division US7893509B2 (en) | 2003-12-03 | 2009-05-29 | Transistor and CVD apparatus used to deposit gate insulating film thereof |
Publications (1)
Publication Number | Publication Date |
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WO2005055325A1 true WO2005055325A1 (ja) | 2005-06-16 |
Family
ID=34650150
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2004/018051 WO2005055325A1 (ja) | 2003-12-03 | 2004-12-03 | トランジスタおよびそのゲート絶縁膜の成膜に用いるcvd装置 |
Country Status (4)
Country | Link |
---|---|
US (2) | US7557416B2 (ja) |
JP (1) | JP2005167019A (ja) |
TW (1) | TWI266422B (ja) |
WO (1) | WO2005055325A1 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI326790B (en) * | 2005-02-16 | 2010-07-01 | Au Optronics Corp | Method of fabricating a thin film transistor of a thin film transistor liquid crystal display and method of fabricating a transistor liquid crystal display |
TWI500159B (zh) * | 2008-07-31 | 2015-09-11 | Semiconductor Energy Lab | 半導體裝置和其製造方法 |
WO2011048959A1 (en) * | 2009-10-21 | 2011-04-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US9490368B2 (en) * | 2010-05-20 | 2016-11-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method of the same |
US8552425B2 (en) | 2010-06-18 | 2013-10-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
KR20130043063A (ko) * | 2011-10-19 | 2013-04-29 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 반도체 장치의 제작 방법 |
US9443987B2 (en) * | 2013-08-23 | 2016-09-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6156415A (ja) * | 1984-07-24 | 1986-03-22 | Fujitsu Ltd | プラズマ処理装置 |
JPH0499282A (ja) * | 1990-08-10 | 1992-03-31 | Nippon Light Metal Co Ltd | 高周波プラズマ発生用電極 |
JPH06302591A (ja) * | 1993-02-19 | 1994-10-28 | Semiconductor Energy Lab Co Ltd | 絶縁被膜および半導体装置の作製方法 |
JPH09289210A (ja) * | 1996-04-19 | 1997-11-04 | Nec Corp | 窒化シリコン膜の形成方法及び薄膜トランジスタ素子 |
JPH1050998A (ja) * | 1996-07-30 | 1998-02-20 | Nec Kagoshima Ltd | 薄膜トランジスタの製造方法 |
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US4838652A (en) * | 1985-05-15 | 1989-06-13 | Canon Kabushiki Kaisha | Image forming apparatus |
JP3189990B2 (ja) * | 1991-09-27 | 2001-07-16 | キヤノン株式会社 | 電子回路装置 |
KR0143873B1 (ko) * | 1993-02-19 | 1998-08-17 | 순페이 야마자끼 | 절연막 및 반도체장치 및 반도체 장치 제조방법 |
JPH07283147A (ja) * | 1994-04-15 | 1995-10-27 | Toshiba Corp | 薄膜形成方法 |
US5712208A (en) * | 1994-06-09 | 1998-01-27 | Motorola, Inc. | Methods of formation of semiconductor composite gate dielectric having multiple incorporated atomic dopants |
JPH08144060A (ja) * | 1994-11-25 | 1996-06-04 | Ulvac Japan Ltd | プラズマcvd装置 |
JP2762968B2 (ja) * | 1995-09-28 | 1998-06-11 | 日本電気株式会社 | 電界効果型薄膜トランジスタの製造方法 |
JPH09106899A (ja) * | 1995-10-11 | 1997-04-22 | Anelva Corp | プラズマcvd装置及び方法並びにドライエッチング装置及び方法 |
JPH11330474A (ja) * | 1998-05-13 | 1999-11-30 | Toshiba Corp | 液晶表示装置およびその製造方法 |
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JP3365742B2 (ja) * | 1998-10-29 | 2003-01-14 | シャープ株式会社 | プラズマcvd装置 |
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WO2002058125A1 (fr) * | 2001-01-22 | 2002-07-25 | Tokyo Electron Limited | Dispositif et procede de traitement au plasma |
US7095460B2 (en) * | 2001-02-26 | 2006-08-22 | Samsung Electronics Co., Ltd. | Thin film transistor array substrate using low dielectric insulating layer and method of fabricating the same |
JP2002329869A (ja) | 2001-04-27 | 2002-11-15 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2003124469A (ja) | 2001-10-09 | 2003-04-25 | Hitachi Ltd | 薄膜トランジスタおよびその製造方法 |
US20050223986A1 (en) * | 2004-04-12 | 2005-10-13 | Choi Soo Y | Gas diffusion shower head design for large area plasma enhanced chemical vapor deposition |
-
2003
- 2003-12-03 JP JP2003404895A patent/JP2005167019A/ja active Pending
-
2004
- 2004-12-03 TW TW093137480A patent/TWI266422B/zh not_active IP Right Cessation
- 2004-12-03 US US10/595,640 patent/US7557416B2/en active Active
- 2004-12-03 WO PCT/JP2004/018051 patent/WO2005055325A1/ja active Application Filing
-
2009
- 2009-05-29 US US12/474,353 patent/US7893509B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS6156415A (ja) * | 1984-07-24 | 1986-03-22 | Fujitsu Ltd | プラズマ処理装置 |
JPH0499282A (ja) * | 1990-08-10 | 1992-03-31 | Nippon Light Metal Co Ltd | 高周波プラズマ発生用電極 |
JPH06302591A (ja) * | 1993-02-19 | 1994-10-28 | Semiconductor Energy Lab Co Ltd | 絶縁被膜および半導体装置の作製方法 |
JPH09289210A (ja) * | 1996-04-19 | 1997-11-04 | Nec Corp | 窒化シリコン膜の形成方法及び薄膜トランジスタ素子 |
JPH1050998A (ja) * | 1996-07-30 | 1998-02-20 | Nec Kagoshima Ltd | 薄膜トランジスタの製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20070063227A1 (en) | 2007-03-22 |
TW200522370A (en) | 2005-07-01 |
TWI266422B (en) | 2006-11-11 |
US7557416B2 (en) | 2009-07-07 |
US7893509B2 (en) | 2011-02-22 |
JP2005167019A (ja) | 2005-06-23 |
US20090236642A1 (en) | 2009-09-24 |
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