WO2005067058A1 - Mis field-effect transistor - Google Patents

Mis field-effect transistor Download PDF

Info

Publication number
WO2005067058A1
WO2005067058A1 PCT/JP2004/019589 JP2004019589W WO2005067058A1 WO 2005067058 A1 WO2005067058 A1 WO 2005067058A1 JP 2004019589 W JP2004019589 W JP 2004019589W WO 2005067058 A1 WO2005067058 A1 WO 2005067058A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
effect transistor
semiconductor layer
mis field
source
Prior art date
Application number
PCT/JP2004/019589
Other languages
French (fr)
Japanese (ja)
Inventor
Kazuya Uejima
Original Assignee
Nec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corporation filed Critical Nec Corporation
Priority to US10/585,576 priority Critical patent/US7579636B2/en
Priority to JP2005516855A priority patent/JP4892976B2/en
Publication of WO2005067058A1 publication Critical patent/WO2005067058A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Definitions

  • the present invention relates to an MIS type field effect transistor, and more particularly to an MIS type field effect transistor whose channel is formed of a semiconductor having a strain.
  • MISFET MIS field-effect transistor
  • Group 4 semiconductors include Ge, C, Si and mixed crystals thereof. Compared with other semiconductors, these Group 4 semiconductors are superior in terms of mechanical strength, cost, and fine workability, and are suitable for large-scale integrated circuits, which are the main applications of MISFETs.
  • a Si substrate is often used for manufacturing MISFETs. This is because it is industrially easy to form Si ⁇ as a gate insulating film, and SiO / S
  • Si has a disadvantage that the mobility of electrons and holes is lower than that of other semiconductors.
  • FIG. 17 shows a method for producing strained Si. First, Si Ge (0 ⁇ x
  • SiGe ⁇ 1
  • SiGe ⁇ 1
  • thin Si is epitaxially grown on the SiGe undersubstrate so as to lattice match.
  • Si receives biaxial tensile strain, and the band structure changes. This reduces the effective mass of electrons and holes and phonon scattering, and increases the mobility of electrons and holes compared to unstrained Si.
  • FIGS. 18 (a) and 18 (b) show the relationship between the Ge concentration (X 100 [%]) of the SiGe base substrate and the rate of increase in the mobility of electrons and holes.
  • the solid and dashed curves show the calculated values and plots. Points indicate experimental values. Since the atomic spacing of the SiGe crystals of the underlying substrate is almost proportional to the Ge concentration, the higher the Ge concentration, the greater the amount of Si distortion. The figure shows that by applying strain to Si, it is possible to increase the mobility of both electrons and holes by 1.5 times or more compared to the case of no strain.
  • a method for manufacturing a strained Si channel MISFET according to a conventional technique will be described.
  • a strained Si layer 2 is epitaxially grown on the underlying SiGe layer 1 (FIG. 19 (a)).
  • a gate insulating film 3 and a gate electrode film 4 are grown on the strained Si layer 2 (FIG. 19B), and then patterned to form a gate insulating film 3a and a gate electrode 4a. ( Figure 19 (c)).
  • the gate electrode 4a as a mask, impurities are introduced into the source and drain formation regions on the surface of the strained Si layer 2 by ion implantation.
  • the dose is 1 ⁇ 10 15 cm— 2 or more. This is to reduce the source-drain parasitic resistance and the contact resistance sufficiently.
  • an amorphous layer 5 is formed on the strained Si layer 2 (FIG. 20 (a)).
  • the amorphous layer 5 is crystallized while growing as a solid layer, and the source / drain regions 6 are formed (FIG. 20 (b)).
  • FIG. 21 shows the electrical characteristics of the strained Si channel MISFET having the gate length of 1 ⁇ thus manufactured. It has good electrical properties and no abnormal leakage current is observed.
  • Patent Document 1 JP-A-10-270685
  • Patent Document 2 Japanese Patent Application Laid-Open No. 2002-237590
  • Non-Patent Document 2 Applied Physics No.65 No.11 p.1131 1996, Ion Implantation
  • MISFETs have realized high performance by miniaturization according to the scaling law, and therefore, practical use of a strained Si channel MISFET with a short gate length is desired.
  • the present inventors have discovered that an abnormal off-leak current occurs in a strained Si channel MISFET when the gate length is reduced.
  • FIGS. 22 (a) and 22 (b) show the electrical characteristics (source-drain current) of two types of strained Si channel MISFETs with short gate lengths.
  • FIGS. 22 (a) and 22 (b) many MISFETs were measured, respectively, and all were plotted on the same graph.
  • FIG. 22 (a) shows a case in which boron is ion-implanted with an energy of 2 keV and a dose of 3 ⁇ 10 15 cm— 2
  • FIG. 22 (b) shows an arsenic with an energy of 8 keV and a dose of 3 X 10 15 ions are implanted in CM_ 2 shows a case of forming the source 'drain region. Only in the latter case, there were some MISFETs with abnormal off-leakage current flowing between the source and the drain.
  • Non-Patent Document 1 states that the cause of the abnormal leakage is a long misfit transition extending in the ⁇ 110> direction, and the strained Si film thickness should be set to a critical film thickness or less.
  • the present inventors it has been found that abnormal leakage is not caused by such a long-range, misfit transition.
  • An object of the present invention is to eliminate the above-mentioned U-shaped dislocation, suppress an abnormal off-leak current that appears when the gate length is short, and reduce the power consumption even when the gate length is short. Is to provide.
  • the MIS field-effect transistor according to the present invention is characterized in that a base layer, an active semiconductor layer formed on the base layer and having a strain, a gate insulating film formed on the active semiconductor layer, An MIS field-effect transistor having a gate electrode formed on a film, and source and drain regions formed in the active semiconductor layer on both sides of the gate electrode.
  • T when the depth at which the concentration of the impurity introduced for forming the source and drain regions is maximized is T,
  • the interface between the underlayer and the active semiconductor layer is at a depth of 2T or less from the surface.
  • another MIS field-effect transistor includes a base layer, an active semiconductor layer formed on the base layer and having a distortion, and a gate insulating film formed on the active semiconductor layer.
  • a gate electrode formed on the gate insulating film, source and drain regions formed in the active semiconductor layer on both sides of the gate electrode, and a gate sidewall formed on a side surface of the gate electrode.
  • a portion of the active semiconductor layer below the gate electrode and the gate side wall is thicker than other portions to form a source 'drain region.
  • T is the depth at which the concentration of impurities introduced for
  • an interface between the underlayer and the active semiconductor layer is at a depth of 2T or less from a surface.
  • Still another MIS field-effect transistor according to the present invention includes a base layer, an active semiconductor layer formed on the base layer and having a distortion, and a gate insulating film formed on the active semiconductor layer.
  • a gate electrode formed on the gate insulating film, and a raised layer formed on the active semiconductor layer on both sides of the gate electrode and having a source and drain region formed thereon. is there.
  • the thickness of the lifted layer is 3 T or more. 5T or less
  • the underlayer is made of Si Ge C (where 0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l,
  • the active semiconductor layer is a Si layer.
  • the thickness of the strain-active semiconductor layer is set to not more than twice the depth T at which the concentration of the impurity introduced for forming the source and drain regions is maximum, or
  • the thickness of the raised region formed on the strain-active semiconductor layer is set to be at least three times T.
  • FIGS. 1 (a) to 1 (c) are cross-sectional views illustrating a method of manufacturing an MISFET according to a first embodiment of the present invention in the order of steps.
  • FIGS. 2 (a) to 2 (c) are cross-sectional views showing a method of manufacturing the MISFET according to the first embodiment of the present invention in the order of steps, and are views showing steps subsequent to FIG.
  • FIGS. 3 (a) to 3 (c) are cross-sectional views illustrating a method of manufacturing a MISFET according to a second embodiment of the present invention in the order of steps.
  • FIGS. 4 (a) to 4 (c) are cross-sectional views showing a method of manufacturing a MISFET according to a second embodiment of the present invention in the order of steps, and show the next step of FIG.
  • FIGS. 5 (a) and (b) are cross-sectional views showing a method of manufacturing a MISFET according to a second embodiment of the present invention in the order of steps, and show the next step of FIG.
  • FIG. 6 is a graph showing gate length dependence of an abnormal off-leak current appearance ratio of a MISFET actually manufactured according to the second embodiment of the present invention.
  • FIGS. 7 (a) to 7 (c) are cross-sectional views illustrating a method of manufacturing a MISFET according to a third embodiment of the present invention in the order of steps.
  • 8 (a) to 8 (c) are cross-sectional views showing a method of manufacturing a MISFET according to a third embodiment of the present invention in the order of steps, and show the next step after FIG.
  • FIGS. 9 (a) to 9 (c) are cross-sectional views showing a method of manufacturing the MISFET according to the third embodiment of the present invention in the order of steps, and show the steps subsequent to FIG.
  • FIGS. 10 (a) to 10 (c) are cross-sectional views illustrating a method of manufacturing an MISFET according to a fourth embodiment of the present invention in the order of steps.
  • FIG. 11 (a) to (d) are cross-sectional views showing a method of manufacturing a MISFET according to a fourth embodiment of the present invention in the order of steps, and show the next step after FIG.
  • FIG. 12 (a) and (b) are cross-sectional views showing a method of manufacturing an MISFET according to a fourth embodiment of the present invention in the order of steps, and show the next step after FIG.
  • FIG. 14 is a sectional view showing an MISFET according to a sixth embodiment of the present invention.
  • FIG. 15 is a sectional view showing an MISFET according to a seventh embodiment of the present invention.
  • FIG. 16 is a sectional view showing an MISFET according to an eighth embodiment of the present invention.
  • FIG. 18 is a graph showing a mobility increase rate of a strained Si channel MISFET.
  • FIG. 19 (a) to (c) are cross-sectional views showing a method of manufacturing a strained Si channel MISFET having a conventional structure in the order of steps.
  • FIG. 20 (a) and (b) are cross-sectional views showing a method of manufacturing a strained Si channel MISFET having a conventional structure in the order of steps, and are views showing the next step after FIG.
  • FIG. 23 is a graph showing the gate length dependence of an abnormal off-leak current appearance ratio of a strained Si channel MISFET.
  • FIG.25 (a), (a) 'is the source of a strained Si channel MISFET formed by arsenic ion implantation.' Plane TEM images of the drain region, (b), (h) (c), (c) (d) and (dr are cross-sectional TEM observation images of the source and drain regions of the strained Si channel MISFET formed by arsenic ion implantation.
  • FIG. 26 is a graph showing the distribution of the length of U-shaped dislocations observed in the source and drain regions of a strained Si channel MISFET formed by arsenic ion implantation.
  • FIG. 27 (a) is a schematic plan view illustrating a mechanism in which a MISFET generates an abnormal off-leak current due to a U-shaped dislocation, and (b) is a schematic cross-sectional view thereof.
  • FIG. 29 (a) to (d) are diagrams for explaining a mechanism of generating a dislocation loop when impurities are ion-implanted into a crystal substrate and heat treatment is performed.
  • FIG. 30 (a) and (b) are graphs showing Monte Carlo simulation results of the depth of the amorphous layer and the distribution of surplus atoms of impurities when boron and arsenic are ion-implanted into a Si (100) substrate. .
  • FIG. 31 shows Monte Carlo simulation results of amorphous layer depth and phosphorus concentration distribution when phosphorus is ion-implanted into a Si (100) substrate, and a cross-sectional TEM observation image after heat treatment.
  • FIG. 32 (a) to (c) are diagrams illustrating a mechanism for growing a dislocation loop force formed in a strained layer into a U-shaped dislocation and relaxing the strain.
  • FIG. 33 is a graph showing the dose dependence of the depth of an amorphous layer by Monte Carlo simulation when arsenic is ion-implanted into a Si (100) substrate.
  • FIG. 34 (a) and (b) are graphs showing Monte Carlo simulation results of impurity distributions immediately after implantation and after heat treatment when boron and arsenic are ion-implanted into a Si (100) substrate.
  • FIG. 35 (a) to (c) are cross-sectional views showing a method of manufacturing a MISFET having a short gate length by a method of manufacturing a strained Si channel MISFET having a conventional structure in the order of steps.
  • FIG. 36 (a) to (c) are cross-sectional views showing a method of manufacturing a MISFET having a short gate length by a method of manufacturing a strained Si channel MISFET having a conventional structure in the order of steps, and are steps subsequent to FIG. FIG.
  • FIG. 23 shows the gate length dependence of the appearance ratio (appearance probability) of MISFETs in which an abnormal off-state current flows when the source and drain are formed by arsenic ion implantation. It can be seen that an abnormal leakage current appears when the gut length is shorter than 0.4 zm. This suggests that a certain finite length leak path exists in the strained Si layer or the underlying SiGe layer.
  • FIG. 24 (a) shows the results of TEM observation of the source and drain regions formed by boron ion implantation
  • FIG. 24 (b) shows the results of TEM observation of the source and drain regions formed by arsenic ion implantation
  • FIGS. 24 (a) ′ and (b) ′ are traces of the linear patterns of FIGS. 24 (a) and (b), respectively.
  • FIG. 25 shows the results.
  • FIG. 25 (a) is an enlarged view inside the square frame of FIG. 24 (b), and FIGS. 25 (b), (c) and (d) show (3), ( It is a cross section image of a portion corresponding to c) and (d).
  • Figures 25 (a) ', (b)', (c) ', and (d)' are traces of the linear patterns in Figures 25 (a), (b), (c), and (d), respectively. Is
  • pattern A on a long straight line was long misfit dislocations generated at the interface between strained Si and SiGe. This misfit dislocation is not the cause of abnormal off-leakage. This is because no abnormal leakage current is observed in the case of boron ion implantation, and no abnormal leakage current is observed in the case of arsenic implantation when the gate length is long.
  • the short linear pattern B has a U-shaped pattern in which misfit dislocations are present in the strained Si or at the interface between the strained Si and SiGe, and both ends form threading dislocations to the strained Si surface. It turned out to be a finite length dislocation. Hereinafter, this dislocation is referred to as a U-shaped dislocation. The present inventor has speculated that this U-shaped dislocation may not be a cause of abnormal leakage.
  • FIG. 26 shows the relationship between the length and density of U-shaped dislocations obtained from a TEM image of an arsenic-implanted region.
  • the length of the longest U-shaped dislocation was about 0.3 / im-0. 4 / im. This length is almost the same as the gate length at which the MISFET with an abnormal leakage current starts to appear.
  • FIG. 27 is a schematic diagram of a MISFET having a U-shaped dislocation.
  • a U-shaped dislocation 7 represented by a length a2 straddles between the source and the drain region 6, and an abnormal off-leak current occurs.
  • the probability is 1 when L> a and exp ⁇ _b 'W (a_L) ⁇ when L ⁇ a.
  • ⁇ (L x ai) means that the product of the numbers ljexp ⁇ _b W (ai_L) ⁇ ix GxGG ixGxG is calculated over L ⁇ ai.
  • the probability that one or more U-shaped dislocations straddle between the source and the drain of the MISFET and generate an abnormal off-peak current is ln (L ⁇ ai) exp ⁇ -b W (ai_L) ⁇ . .
  • FIG. 28 shows the relationship between the gate length on the horizontal axis and the abnormal off-leak rate between the source and drain on the vertical axis.
  • FIG. 28 also shows the data of the MISFET of FIG. 23, which agree well with each other, and it can be concluded that the U-shaped dislocation is the cause of the abnormal leakage current.
  • the present invention has been completed based on such findings.
  • FIGS. 29 (a) to 29 (d) show the behavior of atoms by ion implantation of impurities into the substrate and subsequent heat treatment.
  • the surface becomes amorphous, as shown in FIG. 29 (b), and vacancies and interstitial atoms are generated in the crystal region immediately below the amorphous layer interface.
  • the number of interstitial atoms is larger than the number of vacancies because they include atoms repelled from the amorphous layer.
  • the interstitial atoms larger than the vacancies are referred to as surplus atoms.
  • FIGS. 30 (a) and 30 (b) show the results of Monte Carlo simulation of the distribution of surplus atoms immediately after boron or arsenic is ion-implanted into a Si (100) crystal substrate by broken lines. Arsenic ion implantation has more surplus atoms than boron ion implantation.
  • FIG. 31 shows a cross-sectional TEM image of a dislocation loop formed by ion implantation.
  • Phosphorus was implanted into the Si (100) crystal at 30 keV and 2 ⁇ 10 15 cm— 2 , 790. C, heat treatment for 10 seconds.
  • the depth of the amorphous region immediately after ion implantation was calculated to be 73 nm.
  • Cross-sectional TEM images actually confirmed that dislocations had formed just below this depth.
  • Such experimental results have been reported in other documents (Non-Patent Document 2).
  • Non-Patent Document 2 The small dislocation loop generated by such ion implantation causes a peripheral distortion in an unstrained film.
  • the interstitial atoms are gradually reduced while re-emitting, so as to reduce the strain.
  • the re-emitted interstitial diffuses towards the substrate surface, where it forms part of a new crystal surface.
  • dislocation loops are formed in a layer having strain, it is considered that the heat treatment results in larger dislocation loops. This is because the strain of the strained film can be reduced by increasing the dislocation.
  • FIG. 32 (b) shows a small dislocation loop formed in the strained film by ion implantation and subsequent heat treatment.
  • the strain is relaxed around the dislocation loop. Therefore, after heat treatment, the atoms rearrange to increase the dislocation loop. Eventually, the dislocation loop reaches the surface and becomes a U-shaped dislocation. This is shown in Fig. 32 (c).
  • FIG. 33 shows the relationship between the dose of arsenic and the depth of the amorphous layer / crystal layer interface in the Si (100) crystal substrate, which is normalized by the depth (Rp) at which the impurity concentration immediately after implantation is maximized.
  • FIG. 4 is a graph showing the results calculated by Monte Carlo simulation. It can be seen that when the dose is 1 ⁇ 10 15 cnT 2 or more necessary for forming the source 'drain, the depth of the amorphous layer / crystal layer interface is formed to a depth of 2 Rp or more and 2.5 Rp or less. Dislocations due to ion implantation are formed deeper than the interface between the amorphous layer and the crystal layer. Therefore, if the thickness of the strained layer is less than 2Rp, no U-shaped dislocations will be generated in the strained Si layer because dislocations are not formed by ion implantation.
  • FIGS. 34 (a) and 34 (b) show the impurity concentration distribution after the heat treatment.
  • the strained layer Assuming that the depth at which the substance concentration is maximum is T, if the thickness of the strained layer is 2T or less, the strained layer
  • a strained Si layer 2 is epitaxially grown on the underlying SiGe layer 1 (FIG. 35 (a)).
  • a gate insulating film 3 and a gate electrode film 4 are grown thereon (FIG. 35 (b)), and then patterned to form a gate insulating film 3a and a gate electrode 4a having a length of 0.4 ⁇ m or less. (Fig. 35 (c)).
  • an impurity is ion-implanted at a dose of 1 ⁇ 10 15 cm ⁇ 2 or more.
  • an impurity is introduced into the source and drain regions, and the amorphous layer 5 is formed (FIG. 36A). This depth is defined as the depth at which the impurity concentration is maximum.
  • amorphous layer 5 is crystallized, and a dislocation loop 8 is formed immediately below (FIG. 36 (b)).
  • the dislocation loop 8 grows large to relax the strain of the strained Si layer 2 and becomes a U-shaped dislocation 7 (FIG. 36 (c)).
  • the maximum length of these U-shaped dislocations 7 is about 0.4 z m. For this reason, MISFETs with a gate length of 0.4 x m or less are prone to stochastic abnormal off-leak current.
  • dislocation loops 8 due to ion implantation which are nuclei of U-shaped dislocations, are prevented from being formed in the strained Si layer 2.
  • strained Si has been described as an example of a group 4 semiconductor having strain
  • a strained semiconductor film In some cases, Si Ge C (where 0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, x + y ⁇ 1) may be used.
  • the reason for making this Si layer 10 nm or less is to prevent all channels from being localized only in the cap Si layer.
  • the depth from the surface to the interface between the strained Si Ge C layer and the underlayer is set to 2T or less.
  • the thickness of the raised film should be 3 mm or more.
  • the raised film thickness needs to be 5 mm or less. As can be seen from Figure 34, this membrane
  • doping of at least 1 ⁇ 10 18 cm— 3 or more is possible, and it is possible to maintain the ohmic properties of the source-drain resistance.
  • the source and drain layers can be doped with low damage and high dose, dislocations will not occur in the strained Si layer.
  • Such methods include a plasma doping method and a gas phase doping method. In these methods, impurities are vapor-adsorbed on the surface of the strained film and then diffused into the inside, so that a high dose doping can be performed without destroying the crystal layer.
  • FIG. 1 (a) is a strained Si layer 2 epitaxially grown on the underlying SiGe layer 1 (FIG. 1 (a)).
  • the thickness of this strained Si layer 2 depends on the final MISFET When the depth at which the impurity concentration of the source 'drain is maximized is T, the depth is set to 2 mm or less.
  • a gate insulating film 3 and a gate electrode film 4 are grown thereon (FIG. 1 (b)), and then patterned to form a gate insulating film 3a and a gate electrode 4a having a length of 0.4 / m or less ( Figure 1 (c)).
  • the strained Si layer 2 and the underlying SiGe layer 1 is 1 X 10 15 CM_ 2 or more ion implantation of impurities.
  • a high concentration impurity is introduced into the source / drain formation scheduled region, and the amorphous layer 5 is formed in this region.
  • the depth of the amorphous layer 5 is 2R or more, where R is the depth at which the impurity concentration becomes maximum (FIG. 2 (a)).
  • the amorphous layer 5 is crystallized, and a dislocation loop 8 is formed immediately below the amorphous layer.
  • the dislocation loops 8 are not formed in the strained Si layer 2 but are all formed in the unstrained underlying SiGe layer 1 (FIG. 2 (b)). Further heat treatment is performed to sufficiently activate the impurities.
  • the dislocation loop 8 is formed in the unstrained underlying SiGe layer 1, it disappears or becomes smaller by the heat treatment, and no U-shaped dislocation is formed (FIG. 2 (c)). Therefore, no abnormal off-leak current occurs in the completed MISFET.
  • FIGS. 3 (a) to 3 (c), FIGS. 4 (a) to (c), and FIGS. 5 (a) and 5 (b) are cross-sectional views showing a method of manufacturing an MSIFET according to a second embodiment of the present invention in the order of steps. It is.
  • a strained Si layer 2 is epitaxially grown on the underlying SiGe layer 1.
  • the thickness of the strained Si layer 2 is set to 2T or less, where T is the depth at which the impurity concentration of the source / drain of the final MISFET is maximum (see FIG.
  • FIG. 3 (a) a gate insulating film 3 and a gate electrode film 4 are grown thereon (FIG. 3 (b)), and then patterned to form a gate insulating film 3a and a gate electrode 4a having a length of 0.4 ⁇ or less. (Fig. 3 (c)).
  • an impurity for forming a source / drain extension region is ion-implanted into the strained Si layer 2 to form an impurity implantation region 9 (FIG. 4 (a)).
  • the implantation energy and dose at this time are set smaller than those for ion implantation for forming the source and drain. This is to form a shallower and steeper junction.
  • a gate sidewall 10 is formed by oxide film growth and etch back (FIG. 4B).
  • impurities are ion-implanted by 1 ⁇ 10 15 cm ⁇ 2 or more.
  • the impurity is introduced at a high concentration into the region where the source 'drain is to be formed, and the amorphous layer 5 is formed.
  • the depth of the amorphous layer 5 is R where the depth at which the impurity concentration is maximum is R.
  • the amorphous layer 5 is crystallized, and dislocation loops 8 are formed immediately below (FIG. 5 (a)).
  • the dislocation loops 8 are not formed in the strained Si layer 2 but are all formed in the unstrained underlying SiGe layer 1.
  • no dislocation loop is formed immediately below the impurity injection region 9. This is because the ion implantation for forming the source and drain extension regions does not generate enough extra atoms to form a dislocation loop with low energy and low dose. Further heat treatment is performed to sufficiently activate the impurities.
  • dislocation loop 8 is formed in the unstrained underlying SiGe layer 1, it disappears or becomes smaller, and no U-shaped dislocation is formed (FIG. 5 (b)). Therefore, abnormal off-leak current does not occur in the completed MISFET.
  • FIG. 6 shows the gate length dependence of the abnormal off-leak current appearance ratio of the MISFET manufactured according to the second embodiment.
  • a strained Si layer 2 is epitaxially grown on the underlying SiGe layer 1 (FIG. 7 (a)).
  • the thickness of this strained Si layer 2 is 2T or more, where T is the depth at which the impurity concentration of the source and drain of the final MISFET is the maximum.
  • a gate insulating film 3 and a gate electrode film 4 are grown thereon (FIG. 7 (b)), followed by patterning to form a gate insulating film 3a and a gate electrode 4a having a length of 0.4 ⁇ m or less. (Fig. 7 (c)).
  • an impurity for forming a source / drain extension region is ion-implanted into the strained Si layer 2 to form an impurity implantation region 9 (FIG. 8A).
  • the energy and dose at this time are set smaller than those for ion implantation for forming the source and drain. This is to form a shallower and steeper junction.
  • a gate sidewall 10 is formed by oxide film growth and etch back (FIG. 8B).
  • the strained Si layer 2 in the source and drain regions is etched back so that the film thickness becomes 2T or less (FIG. 8C). Then goo
  • impurities are ion-implanted by 1 ⁇ 10 15 cm— 2 or more. Then, high-concentration impurities are introduced into the source and drain regions, and the amorphous layer 5 is formed (FIG. 9A). This depth is defined as the depth at which the impurity concentration is maximum.
  • the amorphous layer 5 is crystallized, and dislocation loops 8 are formed immediately below the amorphous layer 5 (FIG. 9B).
  • the dislocation loops 8 are not formed in the strained Si layer 2 but are all formed in the unstrained underlying SiGe layer 1.
  • no dislocation loop is formed immediately below the impurity injection region 9. This is because the ion implantation for forming the source / drain extension region 11 does not generate extra atoms sufficient to form a dislocation loop having low energy and low dose.
  • heat treatment is further performed to sufficiently activate the impurities.
  • the dislocation loop 8 is formed in the unstrained underlying SiGe layer 1, it disappears or becomes smaller, and no U-shaped dislocation is formed (FIG. 9 (c)). Therefore, no abnormal off-leak current occurs in the completed MISFET.
  • FIGS. 10 (a) to (c), FIGS. 11 (a) to (d), and FIGS. 12 (a) and (b) are cross-sectional views illustrating a method of manufacturing an MSIFET according to the fourth embodiment of the present invention in the order of steps.
  • FIG. 10 (a) the strained Si layer 2 is epitaxially grown on the underlying SiGe layer 1 (FIG. 10 (a)).
  • the thickness of this strained Si layer 2 is T, where T is the depth at which the impurity concentration of the source and drain of the final MISFET is maximum.
  • a gate insulating film 3 and a gate electrode film 4 are grown thereon (see FIG.
  • the pattern is formed to form a gate insulating film 3a and a gate electrode 4a having a length of 0.4 zm or less (FIG. 10 (c)).
  • impurities for forming a source / drain extension region are ion-implanted to form an impurity implantation region 9 (FIG. 11A).
  • the energy and dose at this time are set smaller than those for ion implantation for forming the source and drain. This is to form a shallower and steeper junction.
  • a gate sidewall 10 is formed by oxide film growth and etch back (FIG. 11B).
  • the source'drain raised region 12 is formed in the source'drain region by using a selective growth method (FIG. 11C). This film thickness is 3T or less
  • impurities are ion-implanted by 1 ⁇ 10 15 cm — 2 or more. Then, impurities are introduced into the source / drain lift region 12 at a high concentration, and the amorphous layer 5 is formed (FIG. 11D). This depth is less than or equal to 2.5R, where R is the depth at which the impurity concentration becomes maximum. Next, activate the impurities
  • a source'drain region 6 and a source'drain extension region 11 are formed, and at the same time, the amorphous layer 5 is crystallized, and a dislocation loop 8 is formed immediately below this (FIG. 12 (a)).
  • the thickness of the source / drain lift region 12 is greater than 3T
  • the dislocation loops 8 are not formed in the strained Si layer 2, but are all localized in the source / drain lift region 12. Also, since the thickness of the raised film is less than 5T,
  • Impurities are diffused in the entire raised region 12 and connected to the source / drain extension region 11 to form the source / drain region 6 (FIG. 12A).
  • no dislocation loop is formed immediately below the impurity introduction region 9. This is because the ion implantation for forming the source and drain extension regions does not generate enough extra atoms to form a dislocation loop having low energy and low dose.
  • further heat treatment is performed to sufficiently activate the impurities (Fig. 12 (b)).
  • the dislocation loop 8 is localized in the source / drain lift region 12, no U-shaped dislocation is formed in the strained Si layer 2 even if the dislocation increases. Therefore, no abnormal off-leak current occurs in the completed MISFET.
  • FIG. 13 is a cross-sectional view of a MISFET according to a fifth embodiment of the present invention.
  • the thickness of the strained Si Ge C layer 14 epitaxially grown on the underlying Si layer 13 is
  • the depth at which the impurity concentration of the source and drain of ET is maximized is T, the depth should be 2 mm or less.
  • Channel material from strained Si to strained Si Ge C (where 0 ⁇ x ⁇ l, 0 ⁇ y ⁇ l, 0 ⁇ x
  • FIG. 14 is a sectional view of the MISFET showing the sixth embodiment of the present invention. Film thickness of strained Si Ge C layer 14 and cap Si layer 15 epitaxially grown on underlying Si layer 13
  • the cap Si layer 15 improves the reliability of the gate insulating film 3a.
  • the thickness of the cap Si layer 15 is set to 10 nm or less. In this case, a channel is formed not only in the cap Si layer 15 but also in the strained Si Ge C layer 14, and the MISFET is formed.
  • FIG. 15 is a sectional view of the MISFET showing the seventh embodiment of the present invention.
  • the thickness of the strained Si layer 2 epitaxially grown on the underlying SiGe layer 1 is 2 T or less, where T is the depth at which the impurity concentration of the source / drain of the final MISFET is maximized.
  • FIG. 16 is a sectional view of an MISFET showing an eighth embodiment of the present invention.
  • a buried oxide film 16 is provided on an underlying Si layer 13, on which a strained Si layer 2 is formed.
  • the thickness of the strained Si layer 2 is determined by the depth at which the impurity concentration of the source / drain of the final MISFET becomes maximum.
  • the eighth embodiment is different from the seventh embodiment in that the underlying SiGe layer 1 does not exist.
  • the parasitic capacitance of the source / drain 6 can be further reduced as compared with the seventh embodiment, and the performance of the MISFET can be further improved.
  • the present invention is not limited to these embodiments, and appropriate changes can be made without departing from the spirit of the present invention.
  • the embodiments may be appropriately combined with each other to form embodiments of the present invention. it can.
  • the fourth and fifth embodiments may be combined to form the source / drain elevated region 12 on the strained SiGeC layer 14.
  • the fifth and eighth embodiments may be combined.
  • the strained SiGeC layer 14 may be formed on the buried oxide film 16.
  • the present invention is effective in preventing an abnormal leakage current in a MISFET whose performance is improved by miniaturization.

Abstract

A strain Si layer (2) is epitaxially grown on an underlying SiGe layer (1), and a gate insulating film (3a) and a gate electrode (4a) are formed. Then, using the gate electrode (4a) as a mask, impurity ions are implanted into the underlying SiGe layer (1) and the strain Si layer (2) (Fig. 2(a)). A heat treatment for activation is carried out to form source/drain regions (6) (Figs. 2(b), 2(c)). The thickness of the strain Si layer (2) is limited to 2Tp or less where Tp(=Rp) is the depth at which the eventual impurity concentration of the source/drain regions (6) of the MISFET is maximum.

Description

明 細 書  Specification
MIS型電界効果トランジスタ  MIS type field effect transistor
技術分野  Technical field
[0001] 本発明は、 MIS型電界効果トランジスタに関し、特にチャネルが歪みを有する半導 体で形成されている MIS型電界効果トランジスタに関するものである。  The present invention relates to an MIS type field effect transistor, and more particularly to an MIS type field effect transistor whose channel is formed of a semiconductor having a strain.
背景技術  Background art
[0002] MIS型電界効果トランジスタ (以下、 MISFETと略記する)は、 4族半導体基板上に 形成されることが多い。 4族半導体とは、 Ge、 C、 Si及びこれらの混晶を指している。 これら 4族半導体は、その他の半導体と比較し、機械的強度、コスト、微細加工性の 観点で優れており、 MISFETの主な用途である大規模集積回路の作製に向いてい るのである。  [0002] An MIS field-effect transistor (hereinafter abbreviated as MISFET) is often formed on a Group 4 semiconductor substrate. Group 4 semiconductors include Ge, C, Si and mixed crystals thereof. Compared with other semiconductors, these Group 4 semiconductors are superior in terms of mechanical strength, cost, and fine workability, and are suitable for large-scale integrated circuits, which are the main applications of MISFETs.
[0003] 4族半導体の中でも、特に Si基板が、 MISFETの作製に多く使用されている。これ は、ゲート絶縁膜として Si〇を形成することが工業的に容易であること、及び SiO /S  [0003] Among the group 4 semiconductors, particularly, a Si substrate is often used for manufacturing MISFETs. This is because it is industrially easy to form Si〇 as a gate insulating film, and SiO / S
2 2 i界面特性が良好であることが理由としてあげられる。  The reason is that the 22 i interface properties are good.
[0004] 但し、 Siには、電子と正孔の移動度が他の半導体に比べて低いという欠点がある。  [0004] However, Si has a disadvantage that the mobility of electrons and holes is lower than that of other semiconductors.
これは、シリコン特有のバンド構造に由来している。低い移動度は MISFETのチヤネ ノレ抵抗を増大させ、 MISFETのスイッチングスピードの低下を招く。そこで、 MISFE Tのチャネル材料として、 Siを使用しつつ、バンド構造を変化させて、電子と正孔の 移動度を向上させる技術が提案されている (例えば、特許文献 1、 2参照)。それは、 S iに歪みを印加する方法である。  This is due to the band structure peculiar to silicon. The low mobility increases the channel resistance of the MISFET and reduces the switching speed of the MISFET. Therefore, a technique has been proposed in which the band structure is changed while using Si as the channel material of the MISFET to improve the mobility of electrons and holes (for example, see Patent Documents 1 and 2). It is a method of applying strain to Si.
[0005] 図 17は歪み Siの作製法を示す。先ず、 Siよりも原子間隔が大きい Si Ge (0<x  FIG. 17 shows a method for producing strained Si. First, Si Ge (0 <x
1-x x 1-x x
≤1、以下、 SiGeと略記する）からなる下地基板を用意する。次に、この SiGe下地基 板の上に薄い Siを格子整合するようェピタキシャル成長させる。そうすると、 Siは 2軸 の引っ張り歪みを受け、バンド構造が変化する。これにより、電子と正孔の有効質量と フオノン散乱が減少し、無歪み Si中に比べ、電子と正孔の移動度が増加する。 ≤1, hereafter abbreviated as SiGe). Next, thin Si is epitaxially grown on the SiGe undersubstrate so as to lattice match. Then, Si receives biaxial tensile strain, and the band structure changes. This reduces the effective mass of electrons and holes and phonon scattering, and increases the mobility of electrons and holes compared to unstrained Si.
[0006] 図 18 (a)、 （b)に、 SiGe下地基板の Ge濃度（X 100 [%] )と、電子と正孔の移動度 増加率の関係を示す。同図において実線及び破線の曲線は計算値を、またプロット 点は実験値を示す。下地基板の Si Ge結晶の原子間隔は Ge濃度にほぼ比例す るため、 Ge濃度が高いほど Siの歪み量が大きくなる。同図より、 Siに歪みを印加する ことにより、無歪みの場合に比べ、電子及び正孔とも 1. 5倍以上移動度を増加させる ことが可能であることが分かる。 [0006] FIGS. 18 (a) and 18 (b) show the relationship between the Ge concentration (X 100 [%]) of the SiGe base substrate and the rate of increase in the mobility of electrons and holes. In the same figure, the solid and dashed curves show the calculated values and plots. Points indicate experimental values. Since the atomic spacing of the SiGe crystals of the underlying substrate is almost proportional to the Ge concentration, the higher the Ge concentration, the greater the amount of Si distortion. The figure shows that by applying strain to Si, it is possible to increase the mobility of both electrons and holes by 1.5 times or more compared to the case of no strain.
[0007] 次に、図 19 (a)乃至（c)及び図 20 (a)、（b)を参照して、従来技術による歪み Siチ ャネル MISFETの作製法を説明する。先ず、下地 SiGe層 1上に歪み Si層 2をェピタ キシャル成長させる（図 19 (a) )。次に、この歪み Si層 2の上に、ゲート絶縁膜 3とグー ト電極膜 4を成長させ（図 19 (b) )、その後パターユングして、ゲート絶縁膜 3aとゲート 電極 4aを形成する（図 19 (c) )。続いて、ゲート電極 4aをマスクにして、イオン注入法 により、歪み Si層 2の表面におけるソース及びドレイン形成予定領域に不純物を導入 する。このとき、ドーズ量は 1 X 1015cm— 2以上である。これは、ソース'ドレインの寄生 抵抗と、コンタクト抵抗を十分下げるためである。このような高ドーズのイオン注入によ り、歪み Si層 2にアモルファス層 5が形成される（図 20 (a) )。最後に、不純物を活性 化するために熱処理を行うと、アモルファス層 5は固層成長しながら結晶化すると共 に、ソース'ドレイン領域 6が形成される（図 20 (b) )。 Next, with reference to FIGS. 19 (a) to (c) and FIGS. 20 (a) and (b), a method for manufacturing a strained Si channel MISFET according to a conventional technique will be described. First, a strained Si layer 2 is epitaxially grown on the underlying SiGe layer 1 (FIG. 19 (a)). Next, a gate insulating film 3 and a gate electrode film 4 are grown on the strained Si layer 2 (FIG. 19B), and then patterned to form a gate insulating film 3a and a gate electrode 4a. (Figure 19 (c)). Subsequently, using the gate electrode 4a as a mask, impurities are introduced into the source and drain formation regions on the surface of the strained Si layer 2 by ion implantation. At this time, the dose is 1 × 10 15 cm— 2 or more. This is to reduce the source-drain parasitic resistance and the contact resistance sufficiently. By such high dose ion implantation, an amorphous layer 5 is formed on the strained Si layer 2 (FIG. 20 (a)). Finally, when a heat treatment is performed to activate the impurities, the amorphous layer 5 is crystallized while growing as a solid layer, and the source / drain regions 6 are formed (FIG. 20 (b)).
[0008] 図 21に、このようにして作製したゲート長 1 μ ΐηの歪み Siチャネル MISFETの電気 特性を示す。良好な電気特性を有しており、異常リーク電流などは観察されない。  [0008] FIG. 21 shows the electrical characteristics of the strained Si channel MISFET having the gate length of 1 μΐη thus manufactured. It has good electrical properties and no abnormal leakage current is observed.
[0009] 特許文献 1 :特開平 10 - 270685号公報  Patent Document 1: JP-A-10-270685
特許文献 2：特開 2002 - 237590号公報  Patent Document 2: Japanese Patent Application Laid-Open No. 2002-237590
特 3午文献 1： H.C. -H.Wang et al., Substrate-Strained Silicon Technology:  Special Reference 1: H.C.-H. Wang et al., Substrate-Strained Silicon Technology:
Process Integration", IEDM 2003， Technical Digest, pp.61-64  Process Integration ", IEDM 2003, Technical Digest, pp.61-64
非特許文献 2 :応用物理 第 65号 第 11号 p.1131 1996、 Ion Implantation  Non-Patent Document 2: Applied Physics No.65 No.11 p.1131 1996, Ion Implantation
Technology Proceedings vol.2, p.744 1999  Technology Proceedings vol.2, p.744 1999
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0010] し力しながら、 MISFETはスケーリング則に従う微細化によって高性能化を実現し てきており、このため、ゲート長の短い歪み Siチャネル MISFETの実用化が望まれて いる。 [0011] ところが、ゲート長が短くなると、歪み Siチャネル MISFETに異常なオフリーク電流 が生じることを本発明者は発見した。 [0010] However, MISFETs have realized high performance by miniaturization according to the scaling law, and therefore, practical use of a strained Si channel MISFET with a short gate length is desired. [0011] However, the present inventors have discovered that an abnormal off-leak current occurs in a strained Si channel MISFET when the gate length is reduced.
[0012] 図 22 (a)、 （b)に、ゲート長が短い 2種類の歪み Siチャネル MISFETの電気特性（ ソース.ドレイン間電流）を示す。図 22 (a)、（b)に示したものは、夫々多数の MISFE Tを測定して、全てを同じグラフ上にプロットしたものである。図 22 (a)は、ボロンをェ ネルギー： 2keV、ドーズ量： 3 X 1015cm— 2でイオン注入した場合を示し、図 22 (b)は 、ヒ素をエネルギー： 8keV、ドーズ量： 3 X 1015cm_2でイオン注入してソース'ドレイン 領域を形成した場合を示す。後者の場合のみ、ソース'ドレイン間に異常オフリーク電 流が流れる MISFET力 Sいくつかみられた。 FIGS. 22 (a) and 22 (b) show the electrical characteristics (source-drain current) of two types of strained Si channel MISFETs with short gate lengths. In FIGS. 22 (a) and 22 (b), many MISFETs were measured, respectively, and all were plotted on the same graph. FIG. 22 (a) shows a case in which boron is ion-implanted with an energy of 2 keV and a dose of 3 × 10 15 cm— 2 , and FIG. 22 (b) shows an arsenic with an energy of 8 keV and a dose of 3 X 10 15 ions are implanted in CM_ 2 shows a case of forming the source 'drain region. Only in the latter case, there were some MISFETs with abnormal off-leakage current flowing between the source and the drain.
[0013] このような異常オフリーク電流を持つ MISFETで回路を構成した場合、回路の消費 電力の増大を招くため好ましくない。  [0013] It is not preferable to configure a circuit with MISFETs having such an abnormal off-leakage current because power consumption of the circuit is increased.
[0014] なお、非特許文献 1に示された研究結果においても、異常リークが発見されている 。そして、この非特許文献 1においては、この異常リークの原因を、く 110〉方向に 伸びる長いミスフィット転移にあるとして、臨界膜厚以下に歪み Si膜厚を設定すべき であるとしている。しかし、後述するように、本願発明者による解析の結果、異常リーク は、このような長レ、ミスフィット転移に起因するのではないことが判明した。  [0014] In the research results shown in Non-Patent Document 1, an abnormal leak was also found. Non-Patent Document 1 states that the cause of the abnormal leakage is a long misfit transition extending in the <110> direction, and the strained Si film thickness should be set to a critical film thickness or less. However, as will be described later, as a result of analysis by the present inventors, it has been found that abnormal leakage is not caused by such a long-range, misfit transition.
[0015] 本願発明の目的は、上述の U字型転位を無くし、ゲート長が短いときに現れる異常 オフリーク電流を抑制し、ゲート長が短い場合にも消費電力が小さい歪み活性半導 体層 MISFETを提供することにある。  An object of the present invention is to eliminate the above-mentioned U-shaped dislocation, suppress an abnormal off-leak current that appears when the gate length is short, and reduce the power consumption even when the gate length is short. Is to provide.
課題を解決するための手段  Means for solving the problem
[0016] 本発明に係る MIS型電界効果トランジスタは、下地層と、この下地層上に形成され 歪みを有する活性半導体層と、前記活性半導体層上に形成されたゲート絶縁膜と、 前記ゲート絶縁膜上に形成されたゲート電極と、前記ゲート電極の両側の前記活性 半導体層内に形成されたソース'ドレイン領域とを有する MIS型電界効果トランジス タである。そして、この本発明に係る MIS型電界効果トランジスタは、ソース'ドレイン 領域を形成するために導入された不純物の濃度が最大になる深さを Tとしたとき、前 The MIS field-effect transistor according to the present invention is characterized in that a base layer, an active semiconductor layer formed on the base layer and having a strain, a gate insulating film formed on the active semiconductor layer, An MIS field-effect transistor having a gate electrode formed on a film, and source and drain regions formed in the active semiconductor layer on both sides of the gate electrode. In the MIS field effect transistor according to the present invention, when the depth at which the concentration of the impurity introduced for forming the source and drain regions is maximized is T,
P  P
記下地層と前記活性半導体層との界面が表面から 2T以下の深さにあることを特徴  The interface between the underlayer and the active semiconductor layer is at a depth of 2T or less from the surface.
P  P
とする。 [0017] また、本発明に係る他の MIS型電界効果トランジスタは、下地層と、この下地層上 に形成され歪みを有する活性半導体層と、前記活性半導体層上に形成されたゲート 絶縁膜と、このゲート絶縁膜上に形成されたゲート電極と、前記ゲート電極の両側の 前記活性半導体層内に形成されたソース'ドレイン領域と、前記ゲート電極の側面に 形成されたゲート側壁と、を有する MIS型電界効果トランジスタである。そして、この 本発明に係る MIS型電界効果トランジスタは、前記活性半導体層の前記ゲート電極 及び前記ゲート側壁の下の部分は他の部分の膜厚より厚くなつており、ソース'ドレイ ン領域を形成するために導入された不純物の濃度が最大になる深さを Tとしたとき、 And Further, another MIS field-effect transistor according to the present invention includes a base layer, an active semiconductor layer formed on the base layer and having a distortion, and a gate insulating film formed on the active semiconductor layer. A gate electrode formed on the gate insulating film, source and drain regions formed in the active semiconductor layer on both sides of the gate electrode, and a gate sidewall formed on a side surface of the gate electrode. It is an MIS type field effect transistor. In the MIS field-effect transistor according to the present invention, a portion of the active semiconductor layer below the gate electrode and the gate side wall is thicker than other portions to form a source 'drain region. Where T is the depth at which the concentration of impurities introduced for
P  P
前記活性半導体層の前記ゲート電極及び前記ゲート側壁の下以外の領域では前記 下地層と前記活性半導体層との界面が表面から 2T以下の深さにあることを特徴と  In a region of the active semiconductor layer other than below the gate electrode and the gate side wall, an interface between the underlayer and the active semiconductor layer is at a depth of 2T or less from a surface.
P  P
する。  I do.
[0018] 更に、本発明に係る更に他の MIS型電界効果トランジスタは、下地層と、この下地 層上に形成され歪みを有する活性半導体層と、前記活性半導体層上に形成された ゲート絶縁膜と、このゲート絶縁膜上に形成されたゲート電極と、前記ゲート電極の 両側の前記活性半導体層上に形成されソース'ドレイン領域が形成されたせり上げ 層と、を有する MIS型電界効果トランジスタである。この本発明に係る MIS型電界効 果トランジスタは、ソース ·ドレイン領域を形成するために導入された不純物の濃度が 最大になる深さを Tとしたとき、前記せり上げ層の膜厚が 3T以上 5T以下であること  [0018] Still another MIS field-effect transistor according to the present invention includes a base layer, an active semiconductor layer formed on the base layer and having a distortion, and a gate insulating film formed on the active semiconductor layer. A gate electrode formed on the gate insulating film, and a raised layer formed on the active semiconductor layer on both sides of the gate electrode and having a source and drain region formed thereon. is there. In the MIS field-effect transistor according to the present invention, when the depth at which the concentration of the impurity introduced for forming the source / drain regions is maximized is T, the thickness of the lifted layer is 3 T or more. 5T or less
P P P  P P P
を特徴とする。  It is characterized by.
[0019] そして、好ましくは、前記下地層は、 Si Ge C (但し、 0≤x≤l , 0≤y≤l ,  [0019] Preferably, the underlayer is made of Si Ge C (where 0≤x≤l, 0≤y≤l,
1— x— y x y  1— x— y x y
0<x + y≤l )の組成を有する半導体層により構成され、また、好ましくは、前記活性 半導体層は、 Si層により構成される。 発明の効果  0 <x + y ≦ l), and preferably, the active semiconductor layer is a Si layer. The invention's effect
[0020] 本発明の MISFETは、歪み活性半導体層の膜厚を、ソース'ドレイン領域を形成 するために導入された不純物の濃度が最大になる深さ Tの 2倍以下にするか、又は  In the MISFET of the present invention, the thickness of the strain-active semiconductor layer is set to not more than twice the depth T at which the concentration of the impurity introduced for forming the source and drain regions is maximum, or
P  P
、歪み活性半導体層上に形成されるせり上げ領域の膜厚を、 Tの 3倍以上とするも  The thickness of the raised region formed on the strain-active semiconductor layer is set to be at least three times T.
P  P
のであるので、歪み活性半導体層内にドーピングによって形成される転位が形成さ れないようにすることができる。従って、これらを核に歪み活性半導体層に U字型転 位が成長することもなぐその結果、ゲート長が短い MISFETにおいても、異常オフリ ーク電流を生じることはなぐ低消費電力 ·短チャネル長の歪みチャネル MISFETを 実現することができる。 Therefore, dislocations formed by doping in the strain-active semiconductor layer can be prevented from being formed. Therefore, these are used as nuclei, and U-shaped inversion As a result, it is possible to realize a low-power-consumption, short-channel-length strained MISFET that does not cause abnormal off-current even in a MISFET with a short gate length.
図面の簡単な説明 Brief Description of Drawings
[図 1] (a)乃至 (c)は、本発明の第 1実施形態に係る MISFETの製造方法を工程順 に示す断面図である。 FIGS. 1 (a) to 1 (c) are cross-sectional views illustrating a method of manufacturing an MISFET according to a first embodiment of the present invention in the order of steps.
[図 2] (a)乃至 (c)は、本発明の第 1実施形態に係る MISFETの製造方法を工程順 に示す断面図であって、図 1の次の工程を示す図である。  FIGS. 2 (a) to 2 (c) are cross-sectional views showing a method of manufacturing the MISFET according to the first embodiment of the present invention in the order of steps, and are views showing steps subsequent to FIG.
[図 3] (a)乃至 (c)は、本発明の第 2実施形態に係る MISFETの製造方法を工程順 に示す断面図である。  FIGS. 3 (a) to 3 (c) are cross-sectional views illustrating a method of manufacturing a MISFET according to a second embodiment of the present invention in the order of steps.
[図 4] (a)乃至 (c)は、本発明の第 2実施形態に係る MISFETの製造方法を工程順 に示す断面図であって、図 3の次の工程を示す図である。  FIGS. 4 (a) to 4 (c) are cross-sectional views showing a method of manufacturing a MISFET according to a second embodiment of the present invention in the order of steps, and show the next step of FIG.
[図 5] (a)及ぴ (b)は、本発明の第 2実施形態に係る MISFETの製造方法を工程順 に示す断面図であって、図 4の次の工程を示す図である。  FIGS. 5 (a) and (b) are cross-sectional views showing a method of manufacturing a MISFET according to a second embodiment of the present invention in the order of steps, and show the next step of FIG.
[図 6]本発明の第 2実施形態により実際に製造した MISFETの異常オフリーク電流 出現割合のゲート長依存性を示すグラフ図である。  FIG. 6 is a graph showing gate length dependence of an abnormal off-leak current appearance ratio of a MISFET actually manufactured according to the second embodiment of the present invention.
[図 7] (a)乃至（c)は、本発明の第 3実施形態に係る MISFETの製造方法を工程順 に示す断面図である。  FIGS. 7 (a) to 7 (c) are cross-sectional views illustrating a method of manufacturing a MISFET according to a third embodiment of the present invention in the order of steps.
[図 8] (a)乃至 (c)は、本発明の第 3実施形態に係る MISFETの製造方法を工程順 に示す断面図であって、図 7の次の工程を示す図である。  8 (a) to 8 (c) are cross-sectional views showing a method of manufacturing a MISFET according to a third embodiment of the present invention in the order of steps, and show the next step after FIG.
[図 9] (a)乃至 (c)は、本発明の第 3実施形態に係る MISFETの製造方法を工程順 に示す断面図であって、図 8の次の工程を示す図である。  FIGS. 9 (a) to 9 (c) are cross-sectional views showing a method of manufacturing the MISFET according to the third embodiment of the present invention in the order of steps, and show the steps subsequent to FIG.
[図 10] (a)乃至 (c)は、本発明の第 4実施形態に係る MISFETの製造方法を工程順 に示す断面図である。  FIGS. 10 (a) to 10 (c) are cross-sectional views illustrating a method of manufacturing an MISFET according to a fourth embodiment of the present invention in the order of steps.
[図 11] (a)乃至 (d)は、本発明の第 4実施形態に係る MISFETの製造方法を工程順 に示す断面図であって、図 10の次の工程を示す図である。  11 (a) to (d) are cross-sectional views showing a method of manufacturing a MISFET according to a fourth embodiment of the present invention in the order of steps, and show the next step after FIG.
[図 12] (a)及ぴ (b)は、本発明の第 4実施形態に係る MISFETの製造方法を工程順 に示す断面図であって、図 11の次の工程を示す図である。  12 (a) and (b) are cross-sectional views showing a method of manufacturing an MISFET according to a fourth embodiment of the present invention in the order of steps, and show the next step after FIG.
差替え用^ 園 13]本発明の第 5実施形態に係る MISFETを示す断面図である。 For replacement ^ Garden 13] is a sectional view showing an MISFET according to a fifth embodiment of the present invention.
園 14]本発明の第 6実施形態に係る MISFETを示す断面図である。 FIG. 14 is a sectional view showing an MISFET according to a sixth embodiment of the present invention.
園 15]本発明の第 7実施形態に係る MISFETを示す断面図である。 FIG. 15 is a sectional view showing an MISFET according to a seventh embodiment of the present invention.
園 16]本発明の第 8実施形態に係る MISFETを示す断面図である。 FIG. 16 is a sectional view showing an MISFET according to an eighth embodiment of the present invention.
園 17]下地 SiGe層上に形成した歪み Siの構造を示す図である。 Garden 17] A diagram showing the structure of strained Si formed on an underlying SiGe layer.
[図 18]歪み Siチャネル MISFETの移動度増加率を示すグラフ図である。  FIG. 18 is a graph showing a mobility increase rate of a strained Si channel MISFET.
[図 19] (a)乃至（c)は、従来構造の歪み Siチャネル MISFETの製造方法を工程順に 示す断面図である。  [FIG. 19] (a) to (c) are cross-sectional views showing a method of manufacturing a strained Si channel MISFET having a conventional structure in the order of steps.
[図 20] (a)及び (b)は、従来構造の歪み Siチャネル MISFETの製造方法を工程順に 示す断面図であって、図 1 9の次の工程を示す図である。  20 (a) and (b) are cross-sectional views showing a method of manufacturing a strained Si channel MISFET having a conventional structure in the order of steps, and are views showing the next step after FIG.
園 21]従来構造の歪み Siチャネル MISFETの電気特性を示すグラフ図である。 園 22]従来構造の歪み Siチャネル MISFETのゲート長を短くした場合の電気特性を 示すグラフ図である。 Garden 21] A graph showing the electrical characteristics of the strained Si channel MISFET of the conventional structure. Garden 22] A graph showing the electrical characteristics when the gate length of the strained Si channel MISFET of the conventional structure is reduced.
[図 23]歪み Siチャネル MISFETの異常オフリーク電流出現割合のゲート長依存性を 示すグラフ図である。  FIG. 23 is a graph showing the gate length dependence of an abnormal off-leak current appearance ratio of a strained Si channel MISFET.
[図 24] (a) , (a) 'はボロンのイオン注入により形成した歪み Siチャネル MISFETのソ ース'ドレイン領域の TEM観察像、及び、（b) , 0)) Ίまヒ素のイオン注入により形成し た歪み Siチャネル MISFETのソース ·ドレイン領域の TEM観察像である。  [Figure 24] (a) and (a) 'are TEM images of the source' drain region of strained Si channel MISFETs formed by boron ion implantation, and (b), 0)) arsenic ions It is a TEM observation image of the source / drain region of a strained Si channel MISFET formed by implantation.
[図 25] (a) , (a) 'はヒ素のイオン注入により形成した歪み Siチャネル MISFETのソー ス 'ドレイン領域の平面 TEM観察像、（b)、 (h) (c)、 (c) (d)、 (drはヒ素のィ オン注入により形成した歪み Siチャネル MISFETのソース'ドレイン領域の断面 TE M観察像である。 [Fig.25] (a), (a) 'is the source of a strained Si channel MISFET formed by arsenic ion implantation.' Plane TEM images of the drain region, (b), (h) (c), (c) (d) and (dr are cross-sectional TEM observation images of the source and drain regions of the strained Si channel MISFET formed by arsenic ion implantation.
[図 26]ヒ素のイオン注入により形成した歪み Siチャネル MISFETのソース'ドレイン領 域で観察された U字型転位の長さの分布を示すグラフ図である。  FIG. 26 is a graph showing the distribution of the length of U-shaped dislocations observed in the source and drain regions of a strained Si channel MISFET formed by arsenic ion implantation.
[図 27] (a)は U字型転位により、 MISFETが異常オフリーク電流を生じるメカニズムを 説明する平面模式図、（b)はその断面模式図である。 [FIG. 27] (a) is a schematic plan view illustrating a mechanism in which a MISFET generates an abnormal off-leak current due to a U-shaped dislocation, and (b) is a schematic cross-sectional view thereof.
園 28]U字型転位の分布により予想計算した異常オフリーク電流出現割合のゲート 長依存性と実測値を比較するグラフ図である。 [図 29] (a)乃至（d)は、結晶基板に不純物をイオン注入し、熱処理を施した場合に、 転位ループを生じるメカニズムを説明する図である。 Garden 28] A graph comparing the gate length dependence of the occurrence rate of abnormal off-leakage current calculated by the distribution of U-shaped dislocations with the measured value. [FIG. 29] (a) to (d) are diagrams for explaining a mechanism of generating a dislocation loop when impurities are ion-implanted into a crystal substrate and heat treatment is performed.
[図 30] (a)及び (b)は、 Si (100)基板にボロン及びヒ素をイオン注入した場合のァモ ルファス層深さと不純物'余剰原子分布のモンテカルロシミュレーション結果を示すグ ラフ図である。  [FIG. 30] (a) and (b) are graphs showing Monte Carlo simulation results of the depth of the amorphous layer and the distribution of surplus atoms of impurities when boron and arsenic are ion-implanted into a Si (100) substrate. .
[図 31]Si (100)基板にリンをイオン注入した場合のアモルファス層深さ及びリン濃度 分布のモンテカルロシミュレーション結果と、熱処理を行った後の断面 TEM観察像 を示した図である。  FIG. 31 shows Monte Carlo simulation results of amorphous layer depth and phosphorus concentration distribution when phosphorus is ion-implanted into a Si (100) substrate, and a cross-sectional TEM observation image after heat treatment.
[図 32] (a)乃至（c)は、歪み層内に形成された転位ループ力 U字型転位に成長し 歪みを緩和するメカニズムを説明する図である。  [FIG. 32] (a) to (c) are diagrams illustrating a mechanism for growing a dislocation loop force formed in a strained layer into a U-shaped dislocation and relaxing the strain.
[図 33]Si (100)基板にヒ素をイオン注入した場合のモンテカルロシミュレーションによ るアモルファス層深さのドーズ量依存性を示すグラフ図である。  FIG. 33 is a graph showing the dose dependence of the depth of an amorphous layer by Monte Carlo simulation when arsenic is ion-implanted into a Si (100) substrate.
[図 34] (a)及び (b)は、 Si (100)基板にボロン及びヒ素をイオン注入した場合の注入 直後と熱処理後の不純物分布のモンテカルロシミュレーション結果を示すグラフ図で ある。 [FIG. 34] (a) and (b) are graphs showing Monte Carlo simulation results of impurity distributions immediately after implantation and after heat treatment when boron and arsenic are ion-implanted into a Si (100) substrate.
[図 35] (a)乃至（c)は、従来構造の歪み Siチャネル MISFETを製造する方法により、 ゲート長が短い MISFETを製造する方法を工程順に示す断面図である。  [FIG. 35] (a) to (c) are cross-sectional views showing a method of manufacturing a MISFET having a short gate length by a method of manufacturing a strained Si channel MISFET having a conventional structure in the order of steps.
[図 36] (a)乃至（c)は、従来構造の歪み Siチャネル MISFETを製造する方法により、 ゲート長が短い MISFETを製造する方法を工程順に示す断面図であって図 35の次 の工程を示す図である。 [FIG. 36] (a) to (c) are cross-sectional views showing a method of manufacturing a MISFET having a short gate length by a method of manufacturing a strained Si channel MISFET having a conventional structure in the order of steps, and are steps subsequent to FIG. FIG.
符号の説明 Explanation of symbols
1 下地 SiGe層  1 Base SiGe layer
2 歪み Si層  2 strained Si layer
3 ゲート絶縁膜  3 Gate insulating film
3a ゲート絶縁膜  3a Gate insulating film
4 ゲート電極膜  4 Gate electrode film
4a ゲート電極  4a Gate electrode
5 アモルファス層 6 ソース'ドレイン領域 5 Amorphous layer 6 Source'drain region
7 U字型転位  7 U-shaped dislocation
8 転位ループ  8 Dislocation loop
9 不純物注入領域  9 Impurity injection region
10 ゲート側壁  10 Gate sidewall
11 ソース'ドレイン拡張領域  11 Source'drain extension area
12 ソース'ドレインせり上げ領域  12 Source'drain lift area
13 下地 Si層  13 Base Si layer
14 歪み Si Ge C層  14 Strained Si Ge C layer
15 キャップ Si層  15 Cap Si layer
16 埋込酸化膜  16 Buried oxide film
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0023] 本願発明者は種々の実験、演算及び考察を行った結果、 U字型転位は、イオン注 入が原因で生じた転位から成長。そうするという結論に達した。先ず、本発明者らは、 異常オフリーク電流の原因を調べるため、以下に示す種々の解析を行った。  [0023] As a result of various experiments, calculations and considerations, the inventor of the present application has found that a U-shaped dislocation grows from a dislocation caused by ion implantation. We have come to the conclusion that we do so. First, the present inventors performed the following various analyzes to investigate the cause of the abnormal off-leak current.
[0024] 図 23は、ヒ素イオン注入によりソース'ドレインを形成した場合において、異常オフリ ーク電流が流れる MISFETの出現割合（出現確率）のゲート長依存性を示す。グー ト長が 0. 4 z mより短くなると、異常リーク電流が出現することがわかる。これは、ある 有限長のリークパスが歪み Si層又は下地 SiGe層中に存在してレ、ることを示唆してレヽ る。  FIG. 23 shows the gate length dependence of the appearance ratio (appearance probability) of MISFETs in which an abnormal off-state current flows when the source and drain are formed by arsenic ion implantation. It can be seen that an abnormal leakage current appears when the gut length is shorter than 0.4 zm. This suggests that a certain finite length leak path exists in the strained Si layer or the underlying SiGe layer.
[0025] 次に、作製した MISFETのソース'ドレイン領域の TEM(transmission electron microscope：透過型電子顕微鏡)観察を行った。図 24 (a)はボロンイオン注入で形成 したソース'ドレイン領域、図 24 (b)はヒ素イオン注入で形成したソース'ドレイン領域 の TEM観察結果を示す。図 24 (a) '、 （b) 'は、夫々図 24 (a)、（b)の線状の模様をト レースした図である。  Next, TEM (transmission electron microscope) observation of the source and drain regions of the manufactured MISFET was performed. FIG. 24 (a) shows the results of TEM observation of the source and drain regions formed by boron ion implantation, and FIG. 24 (b) shows the results of TEM observation of the source and drain regions formed by arsenic ion implantation. FIGS. 24 (a) ′ and (b) ′ are traces of the linear patterns of FIGS. 24 (a) and (b), respectively.
[0026] その結果、ボロン注入の場合及びヒ素注入の場合のいずれの場合も、長い直線状 の模様が見られることが分かった。これを図中、 Aで表示する。また、ヒ素注入の場合 のみ、短い線状の模様が見られた。これを図中、 Bで表示する。 [0027] 次に、これらの模様の原因を調べるため、断面 TEM観察を行った。その結果を図 2 5に示す。図 25 (a)は、図 24 (b)の四角枠内の拡大図であり、図 25 (b)、 (c)、 (d)は 、図 25 (&)の図中（3)、 (c)、 (d)に相当する部分の断面像である。図 25 (a) '、 (b) ' 、 （c) '、 （d) 'は、夫々図 25 (a)、 （b)、 （c)、（d)の線状の模様をトレースした図である As a result, it was found that a long linear pattern was observed in both the case of boron implantation and the case of arsenic implantation. This is indicated by A in the figure. Only in the case of arsenic injection, a short linear pattern was observed. This is indicated by B in the figure. Next, in order to investigate the cause of these patterns, cross-sectional TEM observation was performed. Figure 25 shows the results. FIG. 25 (a) is an enlarged view inside the square frame of FIG. 24 (b), and FIGS. 25 (b), (c) and (d) show (3), ( It is a cross section image of a portion corresponding to c) and (d). Figures 25 (a) ', (b)', (c) ', and (d)' are traces of the linear patterns in Figures 25 (a), (b), (c), and (d), respectively. Is
[0028] 先ず、長い直線上の模様 Aは、歪み Siと SiGeの界面に生じた長レ、ミスフィット転位 であることが分かった。し力、し、この長レ、ミスフィット転位は異常オフリークの原因では ない。なぜなら、ボロンイオン注入の場合は異常リーク電流が見られず、またヒ素ィォ ン注入の場合でもゲート長が長い場合は異常リーク電流が見られないからである。 [0028] First, it was found that pattern A on a long straight line was long misfit dislocations generated at the interface between strained Si and SiGe. This misfit dislocation is not the cause of abnormal off-leakage. This is because no abnormal leakage current is observed in the case of boron ion implantation, and no abnormal leakage current is observed in the case of arsenic implantation when the gate length is long.
[0029] 次に、短い線状の模様 Bは、歪み Si中又は歪み Siと SiGeの界面にミスフィット転位 部を持ち、両端が歪み Si表面への貫通転位部をなすような U字型の有限長転位で あることが分かった。以下、この転位を U字型転位と呼ぶ。本発明者は、この U字型 転位が異常リークの原因ではなレ、かと推測した。  [0029] Next, the short linear pattern B has a U-shaped pattern in which misfit dislocations are present in the strained Si or at the interface between the strained Si and SiGe, and both ends form threading dislocations to the strained Si surface. It turned out to be a finite length dislocation. Hereinafter, this dislocation is referred to as a U-shaped dislocation. The present inventor has speculated that this U-shaped dislocation may not be a cause of abnormal leakage.
[0030] そこで、 U字型転位の分布密度と、 MISFETの異常リーク出現確率の関係につい て調べた。図 26は、ヒ素注入領域の TEM像より求めた U字型転位の長さと密度との 関係を示す。最長の U字型転位の長さは、 0. 3 /i m-0. 4 /i m程度であった。この 長さは、異常リーク電流の MISFETが出現し始めるゲート長とほぼ同じである。  [0030] Thus, the relationship between the distribution density of U-shaped dislocations and the probability of occurrence of abnormal leakage of MISFETs was examined. FIG. 26 shows the relationship between the length and density of U-shaped dislocations obtained from a TEM image of an arsenic-implanted region. The length of the longest U-shaped dislocation was about 0.3 / im-0. 4 / im. This length is almost the same as the gate length at which the MISFET with an abnormal leakage current starts to appear.
[0031] 次に、この U字型転位がソース'ドレインをまたいだときに異常オフリークが出現する と仮定して、図 26より異常リーク電流出現確率を計算した。図 27に、 U字型転位を有 する MISFETの模式図を示す。この図では、長さ a2と表される U字型転位 7が、ソー ス 'ドレイン領域 6間をまたいでおり、異常オフリーク電流が発生すると仮定される。  Next, assuming that abnormal off-leakage appears when the U-shaped dislocation crosses over the source and drain, the probability of appearance of an abnormal leak current was calculated from FIG. FIG. 27 is a schematic diagram of a MISFET having a U-shaped dislocation. In this figure, it is assumed that a U-shaped dislocation 7 represented by a length a2 straddles between the source and the drain region 6, and an abnormal off-leak current occurs.
[0032] もし、長さ aの U字型転位のみが面密度 bで分布していると仮定すれば、この U字型 転位がゲート長 L 、ゲート幅 W の MISFETのソース'ドレイン間を 1つもまたがない  [0032] If it is assumed that only U-shaped dislocations having a length a are distributed at an areal density b, the U-shaped dislocations have a distance between the source and the drain of an MISFET having a gate length L and a gate width W. There is nothing
G G  G G
確率は、 L > aの時に 1、L < aの時に exp{_b 'W (a_L ) }となる。  The probability is 1 when L> a and exp {_b 'W (a_L)} when L <a.
G G GX G  G G GX G
[0033] 実際には様々な長さ aiの U字型転位が面密度 biで分布してレ、ることを考慮すると、 U字型転位が一つも MISFETのソース'ドレイン間をまたがない確率は、 n (L く ai)  [0033] Considering that U-shaped dislocations of various lengths ai are actually distributed at an areal density bi, the probability that no U-shaped dislocation crosses between the source and the drain of the MISFET is considered. Is n (L x ai)
G  G
exp{-b W (ai-L ) }となる。ここで、 Π (L く ai)は、数歹 ljexp{_b W (ai_L ) } ix Gx G G ix Gx G の積を、 L < aiにわたつて計算することを意味する。 [0034] 従って、一つ以上の U字型転位が MISFETのソース'ドレイン間をまたぎ、異常ォ フリーク電流を生じさせる確率は、 l-n (L < ai) exp{-b W (ai_L ) }となる。 exp {-b W (ai-L)}. Here, Π (L x ai) means that the product of the numbers ljexp {_b W (ai_L)} ix GxGG ixGxG is calculated over L <ai. [0034] Accordingly, the probability that one or more U-shaped dislocations straddle between the source and the drain of the MISFET and generate an abnormal off-peak current is ln (L <ai) exp {-b W (ai_L)}. .
G ix Gx G  G ix Gx G
[0035] この計算式に従い、図 26より計算した異常リーク出現確率を図 28に実線にて示す 。図 28は横軸にゲート長をとり、縦軸にソース'ドレイン間の異常オフリーク出現割合 をとつて、両者の関係を示す。図 28には、合わせて図 23の MISFETのデータも示し ているが、両者は良く一致しており、 U字型転位が、異常リーク電流の原因であると結 論できる。本願発明は、このような知見に基づいて完成されたものである。  The abnormal leak appearance probability calculated from FIG. 26 according to this calculation formula is shown by a solid line in FIG. FIG. 28 shows the relationship between the gate length on the horizontal axis and the abnormal off-leak rate between the source and drain on the vertical axis. FIG. 28 also shows the data of the MISFET of FIG. 23, which agree well with each other, and it can be concluded that the U-shaped dislocation is the cause of the abnormal leakage current. The present invention has been completed based on such findings.
[0036] 次に、基板への不純物のイオン注入について説明する。図 29 (a)乃至（d)は、基 板への不純物のイオン注入とその後の熱処理による原子の挙動を示す。結晶基板に 高濃度のイオン注入を行うと、図 29 (b)に示すように、表面がアモルファス化され、ァ モルファス層界面よりすぐ下の結晶領域に、空孔と格子間原子を生じる。このとき、格 子間原子はアモルファス層からはじき飛ばされた原子も含むため、空孔より数が多い 。ここでは、空孔より多い分の格子間原子を、余剰原子と呼ぶ。この基板を熱処理す ると、格子間原子の一部は近くの空孔に収まるが、余剰原子はそのまま格子間に残 留する。一方、アモルファス層は下地の結晶層を受け継ぎながら固層成長し、全体が 結晶化する。この様子を図 29 (c)に示す。例として、図 30 (a)、 （b)に、ボロン又はヒ 素を Si (100)結晶基板にイオン注入した直後の余剰原子の分布のモンテカルロシミ ユレーシヨン結果を破線にて示す。ボロンイオン注入に比べヒ素イオン注入の場合の 方が、余剰原子が多い。これは、同じ注入量の場合、ヒ素原子の方がボロン原子より 重ぐより沢山のシリコン原子をはじき飛ばすためである。これらイオン注入で生じた 余剰原子は、熱処理を続けると次第に析出し、小さな転位ループを形成する。この様 子を図 29 (d)に示す。  Next, ion implantation of impurities into the substrate will be described. FIGS. 29 (a) to 29 (d) show the behavior of atoms by ion implantation of impurities into the substrate and subsequent heat treatment. When high-concentration ion implantation is performed on the crystal substrate, the surface becomes amorphous, as shown in FIG. 29 (b), and vacancies and interstitial atoms are generated in the crystal region immediately below the amorphous layer interface. At this time, the number of interstitial atoms is larger than the number of vacancies because they include atoms repelled from the amorphous layer. Here, the interstitial atoms larger than the vacancies are referred to as surplus atoms. When this substrate is heat-treated, some of the interstitial atoms will fit into nearby vacancies, but excess atoms will remain in the interstitial spaces. On the other hand, the amorphous layer grows in a solid layer while inheriting the underlying crystal layer, and the whole crystallizes. This is shown in Figure 29 (c). As an example, FIGS. 30 (a) and 30 (b) show the results of Monte Carlo simulation of the distribution of surplus atoms immediately after boron or arsenic is ion-implanted into a Si (100) crystal substrate by broken lines. Arsenic ion implantation has more surplus atoms than boron ion implantation. This is because for the same implant dose, arsenic atoms repel more silicon atoms than heavier than boron atoms. The surplus atoms generated by these ion implantations gradually precipitate as heat treatment is continued, forming small dislocation loops. This is shown in Fig. 29 (d).
[0037] 図 31に、イオン注入により形成された転位ループの断面 TEM像を示す。 Si (100) 結晶に、リンを 30keV、 2 X 1015cm— 2の条件でイオン注入し、 790。C、 10秒の熱処 理を施した。モンテカルロシミュレーション計算の結果、イオン注入直後のァモルファ ス領域の深さは、 73nmと計算された。断面 TEM像では、この深さのすぐ下に、転位 が形成されていることが実際に確かめられた。このような実験結果は、他の文献でも 報告されてレ、る (非特許文献 2)。 [0038] このようなイオン注入によって生じた小さな転位ループは、無歪みの膜中では、周 囲に歪みを引き起こす。従って、更に熱処理を続けた場合は、歪みを小さくするよう に、格子間原子を再放出しながら徐々に小さくなる。再放出された格子間原子は、基 板表面に向かって拡散し、そこで新たな結晶表面の一部を形成する。しかし、歪みを 有する層に転位ループが形成された場合は、熱処理でより大きな転位ループになる と考えられる。これは、転位が大きくなることによって、歪み膜の歪みを小さくできるか らである。 FIG. 31 shows a cross-sectional TEM image of a dislocation loop formed by ion implantation. Phosphorus was implanted into the Si (100) crystal at 30 keV and 2 × 10 15 cm— 2 , 790. C, heat treatment for 10 seconds. As a result of Monte Carlo simulation calculation, the depth of the amorphous region immediately after ion implantation was calculated to be 73 nm. Cross-sectional TEM images actually confirmed that dislocations had formed just below this depth. Such experimental results have been reported in other documents (Non-Patent Document 2). [0038] The small dislocation loop generated by such ion implantation causes a peripheral distortion in an unstrained film. Therefore, when the heat treatment is further continued, the interstitial atoms are gradually reduced while re-emitting, so as to reduce the strain. The re-emitted interstitial diffuses towards the substrate surface, where it forms part of a new crystal surface. However, when dislocation loops are formed in a layer having strain, it is considered that the heat treatment results in larger dislocation loops. This is because the strain of the strained film can be reduced by increasing the dislocation.
[0039] この過程を、図 32 (a)乃至（c)を用いて考察する。図 32 (b)は、イオン注入とそれに 続く熱処理により歪み膜中に形成された小さな転位ループを示している。転位ルー プの周辺では歪みが緩和される。そのため、熱処理を施せば、原子は転位ループを 大きくするよう再配置する。ついには転位ループが表面に達し、 U字型転位になる。 この様子を図 32 (c)に示す。  [0039] This process will be considered with reference to FIGS. 32 (a) to 32 (c). FIG. 32 (b) shows a small dislocation loop formed in the strained film by ion implantation and subsequent heat treatment. The strain is relaxed around the dislocation loop. Therefore, after heat treatment, the atoms rearrange to increase the dislocation loop. Eventually, the dislocation loop reaches the surface and becomes a U-shaped dislocation. This is shown in Fig. 32 (c).
[0040] また、転位ループの元となる余剰原子の多いヒ素イオン注入の場合のみ、 U字型転 位が見られたことからも、 U字型転位がイオン注入による転位ループを元に形成され たと考えることは妥当である。  [0040] Also, only in the case of arsenic ion implantation with a large number of surplus atoms serving as a source of a dislocation loop, a U-shaped dislocation was observed. It is reasonable to think that
[0041] こうして、本発明者は、 U字型転位が、イオン注入が原因で生じた転位ループから 成長するという結論に達した。従って重要なことは、イオン注入による転位を歪み層 内に形成させないことである。次に、転位ループを歪み層に形成させないための構 造について説明する。  [0041] Thus, the present inventors have come to the conclusion that U-shaped dislocations grow from dislocation loops caused by ion implantation. Therefore, it is important that dislocations due to ion implantation are not formed in the strained layer. Next, a structure for preventing dislocation loops from being formed in the strained layer will be described.
[0042] 図 33は、ヒ素のドーズ量と、注入直後の不純物濃度が最大になる深さ（Rp)で規格 化した Si (100)結晶基板におけるアモルファス層/結晶層界面の深さとの関係を示 すグラフ図であり、モンテカルロシミュレーションにより計算した結果を示す。ソース'ド レイン形成に必要な 1 X 1015cnT2以上のドーズ量の場合、アモルファス層/結晶層 界面の深さは、 2Rp以上 2. 5Rp以下の深さに形成されることが分かる。また、イオン 注入による転位は、このアモルファス層と結晶層の界面より深いところに形成される。 従って、歪み層の厚さを 2Rpより薄くすれば、歪み Si層内にイオン注入による転位が 形成されることはなぐ U字型転位を生じることもない。 FIG. 33 shows the relationship between the dose of arsenic and the depth of the amorphous layer / crystal layer interface in the Si (100) crystal substrate, which is normalized by the depth (Rp) at which the impurity concentration immediately after implantation is maximized. FIG. 4 is a graph showing the results calculated by Monte Carlo simulation. It can be seen that when the dose is 1 × 10 15 cnT 2 or more necessary for forming the source 'drain, the depth of the amorphous layer / crystal layer interface is formed to a depth of 2 Rp or more and 2.5 Rp or less. Dislocations due to ion implantation are formed deeper than the interface between the amorphous layer and the crystal layer. Therefore, if the thickness of the strained layer is less than 2Rp, no U-shaped dislocations will be generated in the strained Si layer because dislocations are not formed by ion implantation.
[0043] 次に、図 34 (a)、 (b)に、熱処理後の不純物の濃度分布を示す。イオン注入直後の 不純物濃度が最大になる深さと、熱処理後の不純物濃度が最大になる深さとは一致 している。これは、不純物濃度が濃くなるほど、不純物の拡散速度が遅くなり、元の濃 度分布に近くなるためである。すなわち、ソース'ドレインの不純物濃度が最大になる 深さを Tとしたとき、 T =Rとなる。従って、本発明のように、ソース'ドレインの不純Next, FIGS. 34 (a) and 34 (b) show the impurity concentration distribution after the heat treatment. Immediately after ion implantation The depth at which the impurity concentration becomes maximum coincides with the depth at which the impurity concentration after heat treatment becomes maximum. This is because, as the impurity concentration becomes higher, the diffusion speed of the impurity becomes slower, and becomes closer to the original concentration distribution. That is, when the depth at which the impurity concentration of the source and drain is maximized is T, T = R. Therefore, as in the present invention, the impurity of the source
P P P P P P
物濃度が最大になる深さを Tとしたとき、歪み層の膜厚を 2T以下にすれば、歪み層  Assuming that the depth at which the substance concentration is maximum is T, if the thickness of the strained layer is 2T or less, the strained layer
P P  P P
内にイオン注入による転位が形成されることはない。従って、これらを核に歪み層に U字型転位が成長することもなぐ従って、ゲート長が短い MISFETにおいても、異 常オフリーク電流を生じることはなレ、。  No dislocation due to ion implantation is formed therein. Therefore, U-shaped dislocations do not grow in the strained layer with these nuclei, so that abnormal off-leak current does not occur even in a MISFET with a short gate length.
[0044] ここで、図 35 (a)乃至（c)及び図 36 (a)乃至（c)を用いて、従来と同じ製造方法で ゲート長の短い歪み Siチャネル MISFETを製造した場合の問題点について更に詳 しく説明する。 Here, a problem in the case where a strained Si channel MISFET having a short gate length is manufactured by the same manufacturing method as before using FIGS. 35 (a) to (c) and FIGS. 36 (a) to (c). Will be described in more detail.
[0045] 先ず、下地 SiGe層 1上に歪み Si層 2をェピタキシャル成長させる（図 35 (a) )。次に 、この上にゲート絶縁膜 3とゲート電極膜 4を成長させ（図 35 (b) )、その後パターニン グして、ゲート絶縁膜 3aと長さ 0· 4 μ m以下のゲート電極 4aを形成する（図 35 (c) )。 続いて、ゲート電極 4aをマスクにして、不純物をドーズ量 1 X 1015cm— 2以上イオン注 入する。そうすると、ソース'ドレイン領域に不純物が導入されると共に、アモルファス 層 5が形成される（図 36 (a) )。この深さは、不純物濃度が最大になる深さを Rとした First, a strained Si layer 2 is epitaxially grown on the underlying SiGe layer 1 (FIG. 35 (a)). Next, a gate insulating film 3 and a gate electrode film 4 are grown thereon (FIG. 35 (b)), and then patterned to form a gate insulating film 3a and a gate electrode 4a having a length of 0.4 μm or less. (Fig. 35 (c)). Subsequently, using the gate electrode 4a as a mask, an impurity is ion-implanted at a dose of 1 × 10 15 cm− 2 or more. Then, an impurity is introduced into the source and drain regions, and the amorphous layer 5 is formed (FIG. 36A). This depth is defined as the depth at which the impurity concentration is maximum.
P  P
とき、 2R以上である。  When is more than 2R.
P  P
[0046] 次に、不純物を活性化させるために熱処理を行う。そうすると、ソース'ドレイン領域  Next, heat treatment is performed to activate the impurities. Then, the source 'drain region
6が形成される。また、アモルファス層 5は結晶化すると共に、この直下に転位ループ 8が形成される（図 36 (b) )。不純物を十分活性化させるために更に熱処理を行うと、 歪み Si層 2の歪みを緩和させるために転位ループ 8は大きく成長し、 U字型転位 7に なる（図 36 (c) )。これら U字型転位 7の長さは最大 0. 4 z m程度になる。このため、 ゲート長が 0. 4 x m以下の MISFETは確率的に異常オフリーク電流が生じやすいこ とになる。  6 is formed. In addition, the amorphous layer 5 is crystallized, and a dislocation loop 8 is formed immediately below (FIG. 36 (b)). When heat treatment is further performed to sufficiently activate the impurities, the dislocation loop 8 grows large to relax the strain of the strained Si layer 2 and becomes a U-shaped dislocation 7 (FIG. 36 (c)). The maximum length of these U-shaped dislocations 7 is about 0.4 z m. For this reason, MISFETs with a gate length of 0.4 x m or less are prone to stochastic abnormal off-leak current.
[0047] 従って、以下に示す本発明の各実施形態においては、 U字型転位の核となるィォ ン注入による転位ループ 8が、歪み Si層 2内に形成されないようにする。  Therefore, in each of the embodiments of the present invention described below, dislocation loops 8 due to ion implantation, which are nuclei of U-shaped dislocations, are prevented from being formed in the strained Si layer 2.
[0048] なお、歪みを有する 4族半導体として歪み Siを例にして説明したが、歪み半導体膜 として Si Ge C (但し、 0≤x≤l , 0≤y≤l , 0く x + y≤ 1)を用いる場合もあ[0048] Note that although strained Si has been described as an example of a group 4 semiconductor having strain, a strained semiconductor film In some cases, Si Ge C (where 0≤x≤l, 0≤y≤l, x + y≤1) may be used.
1— 1—
る。この場合、高品質のゲート絶縁膜を形成するために、 Si Ge Cとゲート絶縁  The In this case, to form a high quality gate insulating film,
1—  1—
膜との間に 10nm以下のキャップ Si層を挟むのも有効である。この Si層を 10nm以下 にするのは、チャネルが全てキャップ Si層内のみに局在することを防ぐためである。こ のとき、表面から歪み Si Ge C層と下地層との界面までの深さを、 2T以下にす  It is also effective to sandwich a cap Si layer of 10 nm or less between the film and the film. The reason for making this Si layer 10 nm or less is to prevent all channels from being localized only in the cap Si layer. At this time, the depth from the surface to the interface between the strained Si Ge C layer and the underlayer is set to 2T or less.
1—  1—
る。  The
[0049] また、ソース'ドレインをせり上げ構造とし、このせり上げ部にイオン注入による転位 を局在させることによって、歪み膜に転位を生じないようにすることも有効である。この 場合、図 31からも分かるとおり、 3R = 3T以上の深さにはイオン注入による転位を  [0049] It is also effective to prevent the dislocation from being generated in the strained film by forming the source and the drain in a raised structure and localizing the dislocation by ion implantation in the raised portion. In this case, as can be seen from FIG. 31, dislocations due to ion implantation are present at depths of 3R = 3T or more.
Ρ Ρ  Ρ Ρ
生じないので、せり上げ膜厚を 3Τ以上にすればよい。  Since it does not occur, the thickness of the raised film should be 3 mm or more.
Ρ  Ρ
[0050] 但し、せり上げ膜厚が厚すぎると十分にせり上げ部全体に不純物をドーピングでき ないため、せり上げ膜厚を 5Τ以下にする必要がある。図 34から分かるとおり、この膜  [0050] However, if the thickness of the raised film is too large, the entire raised portion cannot be sufficiently doped with impurities. Therefore, the raised film thickness needs to be 5 mm or less. As can be seen from Figure 34, this membrane
Ρ  Ρ
厚であれば、少なくとも 1 X 1018cm— 3以上のドーピングが可能であり、ソース'ドレイン 抵抗のォーミック性を保つことが可能である。 If thick, doping of at least 1 × 10 18 cm— 3 or more is possible, and it is possible to maintain the ohmic properties of the source-drain resistance.
[0051] また、ソース'ドレイン層に、低ダメージで高ドーズのドーピングができれば、歪み Si 層に転位を生じることはなレ、。このような手法としては、プラズマドーピング法及びガス フェーズドーピング法がある。これらの方法では、不純物は歪み膜表面に気相吸着し てから内部に拡散するため、結晶層を破壊することなく高ドーズ量のドーピングが可 能となる。 Further, if the source and drain layers can be doped with low damage and high dose, dislocations will not occur in the strained Si layer. Such methods include a plasma doping method and a gas phase doping method. In these methods, impurities are vapor-adsorbed on the surface of the strained film and then diffused into the inside, so that a high dose doping can be performed without destroying the crystal layer.
[0052] 即ち、これらの方法を使用することにより、歪み層内にドーピングによって転位が形 成されることはない。従って、これらを核に歪み層に U字型転位が成長することもなく 、そのため、ゲート長が短い MISFETにおいても、異常オフリーク電流を生じることな く、低消費電力の歪み Siチャネル MISFETを実現することができる。  That is, by using these methods, dislocations are not formed in the strained layer by doping. Therefore, U-shaped dislocations do not grow in the strained layer with these as nuclei, and therefore, a low power consumption strained Si channel MISFET can be realized without an abnormal off-leak current even in a MISFET with a short gate length. be able to.
[0053] 以下、添付の図面を参照して本発明の実施の形態について詳細に説明する。  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0054] [第 1の実施の形態]  [First Embodiment]
図 1 (a)乃至（c)及び図 2 (a)乃至（c)は、本発明の第 1の実施形態の MSIFETの 製造方法を工程順に示す断面図である。先ず、下地 SiGe層 1上に歪み Si層 2をェピ タキシャル成長させる（図 1 (a) )。この歪み Si層 2の膜厚は、最終的な MISFETのソ ース'ドレインの不純物濃度が最大となる深さを Tとしたとき、 2Τ以下にする。次に、 1A to 1C and 2A to 2C are cross-sectional views illustrating a method for manufacturing the MSIFET according to the first embodiment of the present invention in the order of steps. First, a strained Si layer 2 is epitaxially grown on the underlying SiGe layer 1 (FIG. 1 (a)). The thickness of this strained Si layer 2 depends on the final MISFET When the depth at which the impurity concentration of the source 'drain is maximized is T, the depth is set to 2 mm or less. next,
Ρ Ρ  Ρ Ρ
この上にゲート絶縁膜 3とゲート電極膜 4を成長させ（図 1 (b) )、その後パターユング して、ゲート絶縁膜 3aと長さ 0. 4 / m以下のゲート電極 4aを形成する（図 1 (c) )。続 いて、ゲート電極 4aをマスクにして、歪み Si層 2及び下地 SiGe層 1に、不純物を 1 X 1015cm_2以上イオン注入する。そうすると、ソース'ドレイン形成予定領域に高濃度 の不純物が導入され、この領域にアモルファス層 5が形成される。このアモルファス層 5の深さは、不純物濃度が最大になる深さを Rとしたとき、 2R以上である（図 2 (a) )。 A gate insulating film 3 and a gate electrode film 4 are grown thereon (FIG. 1 (b)), and then patterned to form a gate insulating film 3a and a gate electrode 4a having a length of 0.4 / m or less ( Figure 1 (c)). Continued stomach, and the gate electrode 4a as a mask, the strained Si layer 2 and the underlying SiGe layer 1, is 1 X 10 15 CM_ 2 or more ion implantation of impurities. Then, a high concentration impurity is introduced into the source / drain formation scheduled region, and the amorphous layer 5 is formed in this region. The depth of the amorphous layer 5 is 2R or more, where R is the depth at which the impurity concentration becomes maximum (FIG. 2 (a)).
P P  P P
[0055] 次に、不純物を活性化させるために熱処理を行う。そうすると、ソース'ドレイン領域  Next, heat treatment is performed to activate the impurities. Then, the source 'drain region
6が形成される。また、アモルファス層 5は結晶化すると共に、この直下に転位ループ 8が形成される。但し、転位ループ 8は歪み Si層 2内には形成されず、全て無歪みの 下地 SiGe層 1内に形成される（図 2 (b) )。不純物を十分活性化させるために更に熱 処理を行う。但し、転位ループ 8は無歪みの下地 SiGe層 1内に形成されているため、 前記熱処理により消失するか又は小さくなり、 U字型転位は形成されない（図 2 (c) )。 従って、完成した MISFETに異常オフリーク電流は生じない。  6 is formed. The amorphous layer 5 is crystallized, and a dislocation loop 8 is formed immediately below the amorphous layer. However, the dislocation loops 8 are not formed in the strained Si layer 2 but are all formed in the unstrained underlying SiGe layer 1 (FIG. 2 (b)). Further heat treatment is performed to sufficiently activate the impurities. However, since the dislocation loop 8 is formed in the unstrained underlying SiGe layer 1, it disappears or becomes smaller by the heat treatment, and no U-shaped dislocation is formed (FIG. 2 (c)). Therefore, no abnormal off-leak current occurs in the completed MISFET.
[0056] [第 2の実施の形態]  [Second Embodiment]
図 3 (a)乃至（c)、図 4 (a)乃至（c)及び図 5 (a)、 (b)は、本発明の第 2の実施形態 の MSIFETの製造方法を工程順に示す断面図である。先ず、下地 SiGe層 1上に歪 み Si層 2をェピタキシャル成長させる。この歪み Si層 2の膜厚は、最終的な MISFET のソース'ドレインの不純物濃度が最大となる深さを Tとしたとき、 2T以下にする（図  FIGS. 3 (a) to 3 (c), FIGS. 4 (a) to (c), and FIGS. 5 (a) and 5 (b) are cross-sectional views showing a method of manufacturing an MSIFET according to a second embodiment of the present invention in the order of steps. It is. First, a strained Si layer 2 is epitaxially grown on the underlying SiGe layer 1. The thickness of the strained Si layer 2 is set to 2T or less, where T is the depth at which the impurity concentration of the source / drain of the final MISFET is maximum (see FIG.
P P  P P
3 (a) )。次に、この上にゲート絶縁膜 3とゲート電極膜 4を成長させ（図 3 (b) )、その後 パターニングして、ゲート絶縁膜 3aと長さ 0· 4 μ ΐη以下のゲート電極 4aを形成する（ 図 3 (c) )。  3 (a)). Next, a gate insulating film 3 and a gate electrode film 4 are grown thereon (FIG. 3 (b)), and then patterned to form a gate insulating film 3a and a gate electrode 4a having a length of 0.4 μΐη or less. (Fig. 3 (c)).
[0057] 次に、ゲート電極 4aをマスクにして、歪み Si層 2にソース'ドレイン拡張領域を形成 するための不純物をイオン注入し、不純物注入領域 9を形成する（図 4 (a) )。このとき の注入エネルギーとドーズ量は、ソース'ドレイン形成のためのイオン注入より小さく する。これは、より浅くより急峻な接合を形成するためである。その後、酸化膜成長と エッチバックによりゲート側壁 10を形成する（図 4 (b) )。この後、ゲート電極 4aとゲー ト側壁 10をマスクにして、不純物を 1 X 1015cm— 2以上イオン注入する。そうすると、ソ ース'ドレイン形成予定領域に高濃度に不純物が導入されると共に、アモルファス層 5が形成される。このアモルファス層 5の深さは、不純物濃度が最大になる深さを Rと Next, using the gate electrode 4a as a mask, an impurity for forming a source / drain extension region is ion-implanted into the strained Si layer 2 to form an impurity implantation region 9 (FIG. 4 (a)). The implantation energy and dose at this time are set smaller than those for ion implantation for forming the source and drain. This is to form a shallower and steeper junction. Thereafter, a gate sidewall 10 is formed by oxide film growth and etch back (FIG. 4B). Thereafter, using the gate electrode 4a and the gate side wall 10 as a mask, impurities are ion-implanted by 1 × 10 15 cm− 2 or more. Then, The impurity is introduced at a high concentration into the region where the source 'drain is to be formed, and the amorphous layer 5 is formed. The depth of the amorphous layer 5 is R where the depth at which the impurity concentration is maximum is R.
P  P
したとき、 2R以上である（図 4 (c) )。  Then, it is 2R or more (Fig. 4 (c)).
P  P
[0058] 次に、不純物を活性化させるために熱処理を行う。そうすると、ソース'ドレイン領域  Next, heat treatment is performed to activate the impurities. Then, the source 'drain region
6とソース'ドレイン拡張領域 11が形成される。また、アモルファス層 5は結晶化すると 共に、この直下に転位ループ 8が形成される（図 5 (a) )。但し、転位ループ 8は歪み S i層 2内には形成されず、全て無歪みの下地 SiGe層 1内に形成される。このとき、不 純物注入領域 9の直下には転位ループは形成されなレ、。これは、ソース'ドレイン拡 張領域形成のためのイオン注入は、エネルギー及びドーズ量とも低ぐ転位ループを 形成するのに十分な余剰原子が生じないためである。不純物を十分活性化させるた めに更に熱処理を行う。但し、転位ループ 8は無歪みの下地 SiGe層 1内に形成され ているため、消失するか小さくなり、 U字型転位は形成されない（図 5 (b) )。従って、 完成した MISFETに異常オフリーク電流は生じない。  6 and a source / drain extension region 11 are formed. In addition, the amorphous layer 5 is crystallized, and dislocation loops 8 are formed immediately below (FIG. 5 (a)). However, the dislocation loops 8 are not formed in the strained Si layer 2 but are all formed in the unstrained underlying SiGe layer 1. At this time, no dislocation loop is formed immediately below the impurity injection region 9. This is because the ion implantation for forming the source and drain extension regions does not generate enough extra atoms to form a dislocation loop with low energy and low dose. Further heat treatment is performed to sufficiently activate the impurities. However, since the dislocation loop 8 is formed in the unstrained underlying SiGe layer 1, it disappears or becomes smaller, and no U-shaped dislocation is formed (FIG. 5 (b)). Therefore, abnormal off-leak current does not occur in the completed MISFET.
[0059] 図 6に、第 2の実施形態に従って作製した MISFETの異常オフリーク電流出現割 合のゲート長依存性を示す。ソース'ドレイン領域を形成するためのイオン注入は 3 X 1015cm— 2のドーズ量で行レヽ、 2T = 19nmであった。 2Tより歪み Si層膜厚が厚い 2 FIG. 6 shows the gate length dependence of the abnormal off-leak current appearance ratio of the MISFET manufactured according to the second embodiment. The ion implantation for forming the source / drain regions was performed at a dose of 3 × 10 15 cm− 2 , and 2T = 19 nm. Strain layer thickness greater than 2T 2
P P  P P
5nm、 35nmの場合は、ほぼ同じ程度、高い割合で異常オフリーク電流が出現して いる。一方、 2Tより歪み Si層膜厚が薄い 15nmの場合は、大幅に異常オフリーク電  In the case of 5 nm and 35 nm, an abnormal off-leak current appears at almost the same high rate. On the other hand, when the thickness of the strained Si layer is 15 nm, which is smaller than
P  P
流が減少していることが分かる。完全に異常オフリーク電流が無くなっていないのは、 歪み Si層膜厚の基板面内ばらつきによるものと考えられる。  It can be seen that the flow is decreasing. It is considered that the reason why the abnormal off-leak current is not completely eliminated is due to the in-plane variation of the strained Si layer thickness.
[0060] [第 3の実施の形態] [Third Embodiment]
図 7 (a)乃至（c)、図 8 (a)乃至（c)、図 9 (a)乃至（c)は、本発明の第 3の実施形態 の MISFETの製造方法を工程順に示す断面図である。先ず、下地 SiGe層 1上に歪 み Si層 2をェピタキシャル成長させる（図 7 (a) )。この歪み Si層 2の膜厚は、最終的な MISFETのソース'ドレインの不純物濃度が最大となる深さを Tとしたとき、 2T以上  7A to 7C, 8A to 8C, and 9A to 9C are cross-sectional views illustrating a method of manufacturing the MISFET according to the third embodiment of the present invention in the order of steps. It is. First, a strained Si layer 2 is epitaxially grown on the underlying SiGe layer 1 (FIG. 7 (a)). The thickness of this strained Si layer 2 is 2T or more, where T is the depth at which the impurity concentration of the source and drain of the final MISFET is the maximum.
P P  P P
でもよレ、。次に、この上にゲート絶縁膜 3とゲート電極膜 4を成長させ（図 7 (b) )、その 後パターユングして、ゲート絶縁膜 3aと長さ 0. 4 x m以下のゲート電極 4aを形成する (図 7 (c) )。 [0061] 次に、ゲート電極 4aをマスクにして、歪み Si層 2にソース'ドレイン拡張領域を形成 するための不純物をイオン注入し、不純物注入領域 9を形成する（図 8 (a) )。このとき のエネルギーとドーズ量は、ソース'ドレイン形成のためのイオン注入より小さくする。 これは、より浅くより急峻な接合を形成するためである。その後、酸化膜成長とエッチ バックによりゲート側壁 10を形成する（図 8 (b) )。続けて、ソース'ドレイン領域の歪み Si層 2を、その膜厚が 2T以下になるようにエッチバックする（図 8 (c) )。その後、グー But yeah. Next, a gate insulating film 3 and a gate electrode film 4 are grown thereon (FIG. 7 (b)), followed by patterning to form a gate insulating film 3a and a gate electrode 4a having a length of 0.4 × m or less. (Fig. 7 (c)). Next, using the gate electrode 4a as a mask, an impurity for forming a source / drain extension region is ion-implanted into the strained Si layer 2 to form an impurity implantation region 9 (FIG. 8A). The energy and dose at this time are set smaller than those for ion implantation for forming the source and drain. This is to form a shallower and steeper junction. Thereafter, a gate sidewall 10 is formed by oxide film growth and etch back (FIG. 8B). Subsequently, the strained Si layer 2 in the source and drain regions is etched back so that the film thickness becomes 2T or less (FIG. 8C). Then goo
P  P
ト電極 4aとゲート側壁 10をマスクにして、不純物を 1 X 1015cm— 2以上イオン注入する 。そうすると、ソース'ドレイン領域に高濃度に不純物が導入されると共に、ァモルファ ス層 5が形成される（図 9 (a) )。この深さは、不純物濃度が最大になる深さを Rとした Using the gate electrode 4a and the gate side wall 10 as a mask, impurities are ion-implanted by 1 × 10 15 cm— 2 or more. Then, high-concentration impurities are introduced into the source and drain regions, and the amorphous layer 5 is formed (FIG. 9A). This depth is defined as the depth at which the impurity concentration is maximum.
P  P
とき、 2R以上である。  When is more than 2R.
P  P
[0062] 次に、不純物を活性化させるために熱処理を行う。そうすると、ソース'ドレイン領域  Next, heat treatment is performed to activate the impurities. Then, the source 'drain region
6とソース'ドレイン拡張領域 11が形成される。また、アモルファス層 5は結晶化すると 共に、この直下に転位ループ 8が形成される（図 9 (b) )。但し、転位ループ 8は歪み S i層 2内には形成されず、全て無歪みの下地 SiGe層 1内に形成される。このとき、不 純物注入領域 9の直下には転位ループは形成されない。これは、ソース'ドレイン拡 張領域 11形成のためのイオン注入は、エネルギー及びドーズ量とも低ぐ転位ルー プを形成するのに十分な余剰原子が生じないためである。その後、不純物を十分活 性化させるために更に熱処理を行う。但し、転位ループ 8は無歪みの下地 SiGe層 1 内に形成されているため、消失するか又は小さくなり、 U字型転位は形成されない（ 図 9 (c) )。従って完成した MISFETに異常オフリーク電流は生じない。  6 and a source / drain extension region 11 are formed. In addition, the amorphous layer 5 is crystallized, and dislocation loops 8 are formed immediately below the amorphous layer 5 (FIG. 9B). However, the dislocation loops 8 are not formed in the strained Si layer 2 but are all formed in the unstrained underlying SiGe layer 1. At this time, no dislocation loop is formed immediately below the impurity injection region 9. This is because the ion implantation for forming the source / drain extension region 11 does not generate extra atoms sufficient to form a dislocation loop having low energy and low dose. Thereafter, heat treatment is further performed to sufficiently activate the impurities. However, since the dislocation loop 8 is formed in the unstrained underlying SiGe layer 1, it disappears or becomes smaller, and no U-shaped dislocation is formed (FIG. 9 (c)). Therefore, no abnormal off-leak current occurs in the completed MISFET.
[0063] [第 4の実施の形態]  [Fourth Embodiment]
図 10 (a)乃至（c)、図 11 (a)乃至（d)及び図 12 (a)乃至（b)は、本発明の第 4の実 施形態の MSIFETの製造方法を工程順に示す断面図である。先ず、下地 SiGe層 1 上に歪み Si層 2をェピタキシャル成長させる（図 10 (a) )。この歪み Si層 2の膜厚は、 最終的な MISFETのソース'ドレインの不純物濃度が最大となる深さを Tとしたとき、  FIGS. 10 (a) to (c), FIGS. 11 (a) to (d), and FIGS. 12 (a) and (b) are cross-sectional views illustrating a method of manufacturing an MSIFET according to the fourth embodiment of the present invention in the order of steps. FIG. First, the strained Si layer 2 is epitaxially grown on the underlying SiGe layer 1 (FIG. 10 (a)). The thickness of this strained Si layer 2 is T, where T is the depth at which the impurity concentration of the source and drain of the final MISFET is maximum.
P  P
2T以上でもよい。次に、この上にゲート絶縁膜 3とゲート電極膜 4を成長させ（図 10 ( It may be 2T or more. Next, a gate insulating film 3 and a gate electrode film 4 are grown thereon (see FIG.
P P
b) )、その後パターユングして、ゲート絶縁膜 3aと長さ 0. 4 z m以下のゲート電極 4a を形成する（図 10 (c) )。 [0064] 次に、ゲート電極 4aをマスクにして、ソース'ドレイン拡張領域を形成するための不 純物をイオン注入し、不純物注入領域 9を形成する（図 11 (a) )。このときのエネルギ 一とドーズ量は、ソース'ドレイン形成のためのイオン注入より小さくする。これは、より 浅くより急峻な接合を形成するためである。その後、酸化膜成長とエッチバックにより ゲート側壁 10を形成する（図 11 (b) )。続けて、ソース'ドレイン領域に、選択成長法 を用いてソース'ドレインせり上げ領域 12を形成する（図 11 (c) )。この膜厚は 3T以 b)) Then, the pattern is formed to form a gate insulating film 3a and a gate electrode 4a having a length of 0.4 zm or less (FIG. 10 (c)). Next, using the gate electrode 4a as a mask, impurities for forming a source / drain extension region are ion-implanted to form an impurity implantation region 9 (FIG. 11A). The energy and dose at this time are set smaller than those for ion implantation for forming the source and drain. This is to form a shallower and steeper junction. Thereafter, a gate sidewall 10 is formed by oxide film growth and etch back (FIG. 11B). Subsequently, the source'drain raised region 12 is formed in the source'drain region by using a selective growth method (FIG. 11C). This film thickness is 3T or less
P  P
上 5T以下とする。  Upper 5T or less.
P  P
[0065] その後、ゲート電極 4aとゲート側壁 10をマスクにして、不純物を 1 X 1015cm_2以上 イオン注入する。そうすると、ソース'ドレインせり上げ領域 12に高濃度に不純物が導 入されると共に、アモルファス層 5が形成される（図 11 (d) )。この深さは、不純物濃度 が最大になる深さを Rとしたとき、 2. 5R以下である。次に、不純物を活性化させる Thereafter, using the gate electrode 4a and the gate side wall 10 as a mask, impurities are ion-implanted by 1 × 10 15 cm — 2 or more. Then, impurities are introduced into the source / drain lift region 12 at a high concentration, and the amorphous layer 5 is formed (FIG. 11D). This depth is less than or equal to 2.5R, where R is the depth at which the impurity concentration becomes maximum. Next, activate the impurities
P P  P P
ために熱処理を行う。そうすると、ソース'ドレイン領域 6とソース'ドレイン拡張領域 11 が形成され、同時にアモルファス層 5は結晶化すると共に、この直下に転位ループ 8 が形成される（図 12 (a) )。但し、ソース'ドレインせり上げ領域 12の膜厚が 3Tより厚  Heat treatment for the purpose. Then, a source'drain region 6 and a source'drain extension region 11 are formed, and at the same time, the amorphous layer 5 is crystallized, and a dislocation loop 8 is formed immediately below this (FIG. 12 (a)). However, the thickness of the source / drain lift region 12 is greater than 3T
P  P
いので、転位ループ 8は歪み Si層 2内には形成されず、全てソース'ドレインせり上げ 領域 12内に局在する。また、せり上げ膜厚は 5Tより薄いので、ソース'ドレインせり  Therefore, the dislocation loops 8 are not formed in the strained Si layer 2, but are all localized in the source / drain lift region 12. Also, since the thickness of the raised film is less than 5T,
P  P
上げ領域 12の全てに不純物が拡散し、ソース'ドレイン拡張領域 11と接続して、ソー ス 'ドレイン領域 6が形成される（図 12 (a) )。このとき、不純物導入領域 9の直下には 転位ループは形成されない。これは、ソース'ドレイン拡張領域形成のためのイオン 注入は、エネルギー及びドーズ量とも低ぐ転位ループを形成するのに十分な余剰 原子が生じないためである。その後、不純物を十分活性化させるために更に熱処理 を行う（図 12 (b) )。但し、転位ループ 8はソース'ドレインせり上げ領域 12に局在して いるため、転位が大きくなつたとしても歪み Si層 2内に、 U字型転位は形成されない。 従って、完成した MISFETに異常オフリーク電流は生じない。  Impurities are diffused in the entire raised region 12 and connected to the source / drain extension region 11 to form the source / drain region 6 (FIG. 12A). At this time, no dislocation loop is formed immediately below the impurity introduction region 9. This is because the ion implantation for forming the source and drain extension regions does not generate enough extra atoms to form a dislocation loop having low energy and low dose. After that, further heat treatment is performed to sufficiently activate the impurities (Fig. 12 (b)). However, since the dislocation loop 8 is localized in the source / drain lift region 12, no U-shaped dislocation is formed in the strained Si layer 2 even if the dislocation increases. Therefore, no abnormal off-leak current occurs in the completed MISFET.
[0066] [第 5の実施の形態] [Fifth Embodiment]
図 13は、本発明の第 5の実施の形態を示す MISFETの断面図である。下地 Si層 1 3上にェピタキシャル成長された歪み Si Ge C層 14の膜厚は、最終的な MISF  FIG. 13 is a cross-sectional view of a MISFET according to a fifth embodiment of the present invention. The thickness of the strained Si Ge C layer 14 epitaxially grown on the underlying Si layer 13 is
1  1
ETのソース'ドレインの不純物濃度が最大となる深さを Tとしたとき、 2Τ以下にする 。チャネル材料を歪み Siから歪み Si Ge C (但し、 0≤x≤l , 0≤y≤l , 0<x When the depth at which the impurity concentration of the source and drain of ET is maximized is T, the depth should be 2 mm or less. . Channel material from strained Si to strained Si Ge C (where 0≤x≤l, 0≤y≤l, 0 <x
1— x— y x y  1— x— y x y
+y≤ 1)に変えることにより、特に正孔の移動度を増大させることが可能である。  By changing to + y≤1), it is possible to particularly increase the mobility of holes.
[0067] [第 6の実施の形態] [Sixth Embodiment]
図 14は、本発明の第 6の実施の形態を示す MISFETの断面図である。下地 Si層 1 3上にェピタキシャル成長された歪み Si Ge C層 14とキャップ Si層 15との膜厚  FIG. 14 is a sectional view of the MISFET showing the sixth embodiment of the present invention. Film thickness of strained Si Ge C layer 14 and cap Si layer 15 epitaxially grown on underlying Si layer 13
1—  1—
の和は、最終的な MISFETのソース'ドレインの不純物濃度が最大となる深さを Tと  Is the depth at which the impurity concentration of the source / drain of the final MISFET is maximized, T
P  P
したとき、 2T以下にする。キャップ Si層 15は、ゲート絶縁膜 3aの信頼性を向上させ  When it does, make it less than 2T The cap Si layer 15 improves the reliability of the gate insulating film 3a.
P  P
る働きをする。なお、キャップ Si層 15の膜厚は 10nm以下とする。この場合、キャップ Si層 15だけでなく歪み Si Ge C層 14内にもチャネルが形成され、 MISFETが  Work. The thickness of the cap Si layer 15 is set to 10 nm or less. In this case, a channel is formed not only in the cap Si layer 15 but also in the strained Si Ge C layer 14, and the MISFET is formed.
1—  1—
高性能化する。  Improve performance.
[0068] [第 7の実施の形態] [Seventh Embodiment]
図 15は、本発明の第 7の実施の形態を示す MISFETの断面図である。下地 SiGe 層 1上にェピタキシャル成長された歪み Si層 2の膜厚は、最終的な MISFETのソー ス 'ドレインの不純物濃度が最大となる深さを Tとしたとき、 2T以下にする。  FIG. 15 is a sectional view of the MISFET showing the seventh embodiment of the present invention. The thickness of the strained Si layer 2 epitaxially grown on the underlying SiGe layer 1 is 2 T or less, where T is the depth at which the impurity concentration of the source / drain of the final MISFET is maximized.
P P  P P
[0069] なお、下地 SiGe層 1と下地 Si層 13との間に、坦込酸化膜 16が形成されている。こ の構造では、ソース'ドレイン領域 6の寄生容量が低減され、 MISFETの高性能化が 可能である。  Note that between the underlying SiGe layer 1 and the underlying Si layer 13, a loaded oxide film 16 is formed. With this structure, the parasitic capacitance of the source / drain region 6 is reduced, and the performance of the MISFET can be improved.
[0070] [第 8の実施の形態]  [Eighth Embodiment]
図 16は、本発明の第 8の実施の形態を示す MISFETの断面図である。下地 Si層 1 3上に埋込酸化膜 16を有し、その上に歪み Si層 2が形成されている。この歪み Si層 2 の膜厚は、最終的な MISFETのソース'ドレインの不純物濃度が最大となる深さを T  FIG. 16 is a sectional view of an MISFET showing an eighth embodiment of the present invention. A buried oxide film 16 is provided on an underlying Si layer 13, on which a strained Si layer 2 is formed. The thickness of the strained Si layer 2 is determined by the depth at which the impurity concentration of the source / drain of the final MISFET becomes maximum.
P  P
としたとき、 2T以下にする。  And 2T or less.
P  P
[0071] この第 8実施形態が第 7実施形態と違う点は、下地 SiGe層 1が存在しないことであ る。この構造では、ソース'ドレイン 6の寄生容量が第 7実施例より更に低減可能であり 、より一層、 MISFETの高性能化が可能である。  The eighth embodiment is different from the seventh embodiment in that the underlying SiGe layer 1 does not exist. With this structure, the parasitic capacitance of the source / drain 6 can be further reduced as compared with the seventh embodiment, and the performance of the MISFET can be further improved.
[0072] 以上好ましい実施の形態について説明したが、本発明はこれらの実施の形態に限 定されるものではなぐ本発明の要旨を逸脱しない範囲内において適宜の変更が可 能なものである。また、各実施の形態を適宜組み合わせて発明の実施例とすることが できる。例えば、第 4、第 5の実施形態を組み合わせて、歪み Si Ge C層 14上に ソース'ドレインせり上げ領域 12を形成するようにしてもよぐまた、第 5、第 8の実施形 態を組み合わせて、埋込酸化膜 16上に歪み Si Ge C層 14を形成するようにし てもよい。 Although the preferred embodiments have been described above, the present invention is not limited to these embodiments, and appropriate changes can be made without departing from the spirit of the present invention. In addition, the embodiments may be appropriately combined with each other to form embodiments of the present invention. it can. For example, the fourth and fifth embodiments may be combined to form the source / drain elevated region 12 on the strained SiGeC layer 14. Alternatively, the fifth and eighth embodiments may be combined. In combination, the strained SiGeC layer 14 may be formed on the buried oxide film 16.
産業上の利用可能性 Industrial applicability
本発明は、微細化により高性能化した MISFETにおいて、異常リーク電流の防止 に有効である。  INDUSTRIAL APPLICABILITY The present invention is effective in preventing an abnormal leakage current in a MISFET whose performance is improved by miniaturization.

Claims

請求の範囲 The scope of the claims
[1] 下地層と、この下地層上に形成され歪みを有する活性半導体層と、前記活性半導体 層上に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成されたゲート電極と、 前記活性半導体層内における前記ゲート電極の両側の部分に形成されたソース'ド レイン領域と、を有し、前記ソース'ドレイン領域を形成するために導入された不純物 の濃度が最大になる深さを τとしたとき、前記下地層と前記活性半導体層との界面  [1] a base layer, an active semiconductor layer formed on the base layer and having a distortion, a gate insulating film formed on the active semiconductor layer, a gate electrode formed on the gate insulating film, A source 'drain region formed on both sides of the gate electrode in the active semiconductor layer, and a depth at which the concentration of impurities introduced to form the source' drain region is maximized. When τ, the interface between the underlayer and the active semiconductor layer
P  P
が表面から 2T以下の深さにあることを特徴とする MIS型電界効果トランジスタ。  MIS field-effect transistor, wherein the depth is less than 2T from the surface.
P  P
[2] 下地層と、この下地層上に形成され歪みを有する活性半導体層と、前記活性半導体 層上に形成されたゲート絶縁膜と、このゲート絶縁膜上に形成されたゲート電極と、 前記活性半導体層内における前記ゲート電極の両側の部分に形成されたソース'ド レイン領域と、前記ゲート電極の側面に形成されたゲート側壁と、を有し、前記活性 半導体層の前記ゲート電極及び前記ゲート側壁の下の部分は他の部分の膜厚より 厚くなつており、ソース'ドレイン領域を形成するために導入された不純物の濃度が最 大になる深さを Tとしたとき、前記活性半導体層の前記ゲート電極及び前記ゲート側  [2] a base layer, an active semiconductor layer formed on the base layer and having a distortion, a gate insulating film formed on the active semiconductor layer, a gate electrode formed on the gate insulating film, A source 'drain region formed on both sides of the gate electrode in the active semiconductor layer, and a gate sidewall formed on a side surface of the gate electrode; and the gate electrode and the gate electrode of the active semiconductor layer. The portion under the gate sidewall is thicker than the other portions, and when the depth at which the concentration of impurities introduced for forming the source and drain regions is maximized is T, the active semiconductor The gate electrode and the gate side of the layer
P  P
壁の下以外の領域では前記下地層と前記活性半導体層との界面が表面から 2T以  In regions other than below the wall, the interface between the underlayer and the active semiconductor layer is 2T or less from the surface.
P  P
下の深さにあることを特徴とする MIS型電界効果トランジスタ。  An MIS field-effect transistor characterized by being at a lower depth.
[3] 下地層と、この下地層上に形成され歪みを有する活性半導体層と、前記活性半導体 層上に形成されたゲート絶縁膜と、このゲート絶縁膜上に形成されたゲート電極と、 前記ゲート電極の両側の前記活性半導体層上に形成されソース'ドレイン領域が形 成されたせり上げ層と、を有し、ソース'ドレイン領域を形成するために導入された不 純物の濃度が最大になる深さを Tとしたとき、前記せり上げ層の膜厚が 3T以上であ [3] a base layer, an active semiconductor layer formed on the base layer and having a distortion, a gate insulating film formed on the active semiconductor layer, a gate electrode formed on the gate insulating film, A lift-up layer formed on the active semiconductor layer on both sides of the gate electrode and forming a source'drain region, wherein the concentration of impurities introduced to form the source'drain region is maximized. Where T is the depth at which the thickness of the raised layer is 3T or more.
P P  P P
ることを特徴とする MIS型電界効果トランジスタ。  MIS field effect transistor characterized by the following:
[4] 前記せり上げ層の膜厚が 5T以下であることを特徴とする請求項 3に記載の MIS型 [4] The MIS type according to [3], wherein the thickness of the raised layer is 5T or less.
P  P
電界効果トランジスタ。  Field effect transistor.
[5] 前記下地層が、 Si Ge C (但し、 0≤x≤l , 0≤y≤l, 0く x + y≤l)の組成  [5] The underlayer has a composition of Si Ge C (where 0≤x≤l, 0≤y≤l, and 0x + y≤l)
1— x— y χ y  1— x— y χ y
を有する半導体層であることを特徴とする請求項 1乃至 4のいずれ力 1項に記載の M IS型電界効果トランジスタ。  5. The MIS field-effect transistor according to claim 1, wherein the MIS field-effect transistor is a semiconductor layer having:
[6] 前記下地層が、 Si層であることを特徴とする請求項 1乃至 4のいずれ力 1項に記載の MIS型電界効果トランジスタ。 [6] The method according to any one of [1] to [4], wherein the underlayer is a Si layer. MIS field effect transistor.
[7] 前記下地層が半導体層であって前記下地層の下層に絶縁体層が形成されているこ とを特徴とする請求項 1乃至 6のいずれ力 1項に記載の MIS型電界効果トランジスタ 7. The MIS field effect transistor according to claim 1, wherein the underlayer is a semiconductor layer, and an insulator layer is formed below the underlayer.
[8] 前記下地層が絶縁体層であることを特徴とする請求項 1乃至 4のいずれ力 4項に記 載の MIS型電界効果トランジスタ。 [8] The MIS field-effect transistor according to any one of claims 1 to 4, wherein the underlayer is an insulator layer.
[9] 前記活性半導体層が、 4族半導体層であることを特徴とする請求項 1乃至 8のいずれ 力、 1項に記載の MIS型電界効果トランジスタ。 9. The MIS field effect transistor according to claim 1, wherein the active semiconductor layer is a Group 4 semiconductor layer.
[10] 前記活性半導体層が、 Si層であることを特徴とする請求項 1乃至 5、 7、 8のいずれか10. The active semiconductor layer according to claim 1, wherein the active semiconductor layer is a Si layer.
1項に記載の MIS型電界効果トランジスタ。 2. The MIS field effect transistor according to item 1.
[11] 前記活性半導体層が、 Si Ge C (但し、 0≤x≤l， 0≤y≤l, 0<x + y≤l) の組成を有する半導体層であることを特徴とする請求項 1乃至 8のいずれ力、 1項に記 載の MIS型電界効果トランジスタ。 [11] The active semiconductor layer is a semiconductor layer having a composition of Si Ge C (where 0≤x≤l, 0≤y≤l, 0 <x + y≤l). The MIS field-effect transistor according to any one of Items 1 to 8, wherein the MIS field-effect transistor is described in 1.
[12] 前記活性半導体層と前記ゲート絶縁膜との間に、 lOnm以下の膜厚の Si層を有する ことを特徴とする請求項 11に記載の MIS型電界効果トランジスタ。 12. The MIS field effect transistor according to claim 11, further comprising a Si layer having a thickness of lOnm or less between the active semiconductor layer and the gate insulating film.
[13] ゲート長が 0· 4 μ ΐη以下であることを特徴とする請求項 1乃至 12のいずれ力 1項に記 載の MIS型電界効果トランジスタ。 13. The MIS field-effect transistor according to claim 1, wherein a gate length is not more than 0.4 μ 以下 η.
[14] 前記ソース'ドレイン領域力 イオン注入法によって形成されていることを特徴とする 請求項 1乃至 13のいずれか 1項に記載の MIS型電界効果トランジスタ。 14. The MIS field effect transistor according to claim 1, wherein the MIS field effect transistor is formed by an ion implantation method.
[15] 前記ソース'ドレイン領域力 プラズマドーピング法によって形成されていることを特徴 とする請求項 1乃至 13のいずれ 1項に記載の MIS型電界効果トランジスタ。 15. The MIS field effect transistor according to claim 1, wherein the MIS field effect transistor is formed by a plasma doping method.
[16] 前記ソース'ドレイン領域力 ガスフェーズドーピング法によって形成されていることを 特徴とする請求項 1乃至 13のいずれ 1項に記載の MIS型電界効果トランジスタ。 16. The MIS field effect transistor according to claim 1, wherein the MIS field effect transistor is formed by a gas phase doping method.
[17] 前記ソース'ドレイン領域のゲート電極寄りの部分は低不純物濃度領域になされてい ることを特徴とする請求項 1乃至 16のいずれ力、 1項に記載の MIS型電界効果トラン ジスタ。 17. The MIS field effect transistor according to claim 1, wherein a portion of the source / drain region near the gate electrode is formed as a low impurity concentration region.
PCT/JP2004/019589 2004-01-08 2004-12-28 Mis field-effect transistor WO2005067058A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/585,576 US7579636B2 (en) 2004-01-08 2004-12-28 MIS-type field-effect transistor
JP2005516855A JP4892976B2 (en) 2004-01-08 2004-12-28 MIS field effect transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004002841 2004-01-08
JP2004-002841 2004-01-08

Publications (1)

Publication Number Publication Date
WO2005067058A1 true WO2005067058A1 (en) 2005-07-21

Family

ID=34747060

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2004/019589 WO2005067058A1 (en) 2004-01-08 2004-12-28 Mis field-effect transistor

Country Status (2)

Country Link
JP (1) JP4892976B2 (en)
WO (1) WO2005067058A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011030782A1 (en) * 2009-09-09 2011-03-17 学校法人神奈川大学 Method for forming a semiconductor element structure and semiconductor element

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10106966A (en) * 1996-10-01 1998-04-24 Nippon Steel Corp Manufacture of semiconductor device
JPH10214906A (en) * 1996-09-17 1998-08-11 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacture
JPH10270685A (en) * 1997-03-27 1998-10-09 Sony Corp Field-effect transistor and manufacture thereof, semiconductor device and manufacture thereof and logic circuit containing semiconductor device thereof and semiconductor substrate
JP2000286418A (en) * 1999-03-30 2000-10-13 Hitachi Ltd Semiconductor device and semiconductor substrate
JP2001217433A (en) * 2000-01-07 2001-08-10 Samsung Electronics Co Ltd Cmos integrated circuit element with buried silicon germanium layer, substrate and its manufacturing method
US20030227029A1 (en) * 2002-06-07 2003-12-11 Amberwave Systems Corporation Elevated source and drain elements for strained-channel heterojuntion field-effect transistors

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10214906A (en) * 1996-09-17 1998-08-11 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacture
JPH10106966A (en) * 1996-10-01 1998-04-24 Nippon Steel Corp Manufacture of semiconductor device
JPH10270685A (en) * 1997-03-27 1998-10-09 Sony Corp Field-effect transistor and manufacture thereof, semiconductor device and manufacture thereof and logic circuit containing semiconductor device thereof and semiconductor substrate
JP2000286418A (en) * 1999-03-30 2000-10-13 Hitachi Ltd Semiconductor device and semiconductor substrate
JP2001217433A (en) * 2000-01-07 2001-08-10 Samsung Electronics Co Ltd Cmos integrated circuit element with buried silicon germanium layer, substrate and its manufacturing method
US20030227029A1 (en) * 2002-06-07 2003-12-11 Amberwave Systems Corporation Elevated source and drain elements for strained-channel heterojuntion field-effect transistors

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
HOYT J.L. ET AL: "Strained Silicon MOSFET Technology", IEDM 2002, 2002, pages 23 - 26, XP010625981 *
TAMURA M. ET AL: "Secondary Defects in 1-10 keV As- and BF2-implanted Si", INTERNATIONAL CONFERENCE ON ION IMPLANTATION TECHNOLOGY PROCEEDINGS, 1998, pages 744 - 747, XP010362155 *
WANG H.C.H. ET AL: "substrate-Strained Silicon Technology", PROCESS INTEGRATION IEDM 2003, 2003, pages 61 - 64, XP010683959 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011030782A1 (en) * 2009-09-09 2011-03-17 学校法人神奈川大学 Method for forming a semiconductor element structure and semiconductor element
US8941092B2 (en) 2009-09-09 2015-01-27 Kanagawa University Method for forming semiconductor device structure and semiconductor device
JP5700563B2 (en) * 2009-09-09 2015-04-15 学校法人神奈川大学 Method for forming semiconductor device structure and semiconductor device

Also Published As

Publication number Publication date
JP4892976B2 (en) 2012-03-07
JPWO2005067058A1 (en) 2007-12-20

Similar Documents

Publication Publication Date Title
US8642434B2 (en) Structure and method for mobility enhanced MOSFETS with unalloyed silicide
US7023018B2 (en) SiGe transistor with strained layers
TWI495101B (en) A technique for strain engineering in si-based transistors by using embedded semiconductor layers including atoms with high covalent radius
JP5076388B2 (en) Semiconductor device and manufacturing method thereof
JP4690326B2 (en) Template layer structure
CN102593118B (en) Semiconductor device and method of manufacturing the same
JP2002237590A (en) Mos field effect transistor
WO2009093328A1 (en) Semiconductor device and method for production thereof
JP2010512006A (en) Low defect Si: C layer with retrograde carbon profile
JP2004014856A (en) Method for manufacturing semiconductor substrate and semiconductor device
CN105428228A (en) Quantum well mosfet channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains
US6849527B1 (en) Strained silicon MOSFET having improved carrier mobility, strained silicon CMOS device, and methods of their formation
WO2012055143A1 (en) Transistor and manufacturing method thereof
US8963255B2 (en) Strained silicon carbide channel for electron mobility of NMOS
KR100497919B1 (en) Method for manufacturing semiconductor device
US20070281411A1 (en) Formation of strain-inducing films
JP2009094225A (en) Method of manufacturing semiconductor device
US8642413B2 (en) Formation of strain-inducing films using hydrogenated amorphous silicon
WO2012055142A1 (en) Transistor and manufacturing method thereof
JP3488914B2 (en) Semiconductor device manufacturing method
WO2006081287A2 (en) Semiconductor device having dislocation loop located within boundary created by source/drain regions and method of manufacture
WO2005067058A1 (en) Mis field-effect transistor
KR100835424B1 (en) Method for fabricating a mos transistor
US7579636B2 (en) MIS-type field-effect transistor
CN112701044B (en) Strained germanium channel transistor and method of making the same

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2005516855

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWW Wipo information: withdrawn in national office

Country of ref document: DE

WWE Wipo information: entry into national phase

Ref document number: 10585576

Country of ref document: US

122 Ep: pct application non-entry in european phase