WO2005078769A2

WO2005078769A2 - Manufacturing integrated circuits

Info

Publication number: WO2005078769A2
Application number: PCT/IB2005/000353
Authority: WO
Inventors: Jens Hoffman; Andreas Ott; Karl-Ulrich Stahl
Original assignee: Melexis Nv
Priority date: 2004-02-13
Filing date: 2005-02-14
Publication date: 2005-08-25
Also published as: GB0403230D0; WO2005078769A3

Abstract

A method of manufacturing integrated circuits (201) comprises the steps of: forming an array of integrated circuits (201) on a wafer, each integrated circuit (201) being provided with dedicated configuration means (104, 105); configuring said integrated circuits (201) using said configuration means (104, 105); and separating the individual integrated circuits (201) from the array by cutting along scribe channels (202) provided between the integrated circuits (201) in the array wherein said dedicated configuration means (104, 105) for each integrated circuit (201) is wholly or partially formed in a scribe channel (202) adjacent to said integrated circuit (201). The configuration means (104, 105) are thus destroyed during the separation process, thus producing a smaller integrated circuits (201). As this is the case, more integrated circuits 201 can be formed on a single wafer thus using the available wafer more efficiently and providing significant cost savings.

Description

MAMJFACTU ING INTEGRATED CIRCUITS

The preset invention relates to the manufacture of integrated circuits.

In conventional methods of manufacturing integrated circuits, a large number of identical integrated circuits are formed in a rectangular array on a single wafer. The individual integrated circuits in the array are then separated by cutting the wafer. To facilitate this separation process, spaces are provided between each of the integrated circuits in the array through which cuts can be made without damaging the integrated circuits.

Due to the rectangular nature of the array the spaces between the integrated circuits comprise two series of parallel channels, the channels of each series running in mutually perpendicular directions. These channels are known as scribe channels. The width of the scribe channels is determined by the thickness of the saw blade used to make the cuts and the width of areas adjacent to the cut which are damaged during the cutting process. A typical scribe channel may be 100 microns wide. hi order to make integrated circuits as efficiently as possible, it is desirable to fit as many integrated circuits as possible on to a single wafer. The requirement to leave scribe channels between each integrated circuit effectively limits the number of individual integrated circuits that may be provided on a single wafer, hi order to fit more integrated circuits on to a wafer it is thus necessary to either make the integrated circuits smaller or the scribe channels narrower. It is difficult to reduce the width of the scribe channels by any considerable amount as their width is at least partially determined by the width of the saw blade used to cut the wafer. In the semiconductor industry, limitations on the number of integrated circuits that can be formed on a single wafer due to the provision of scribe channels have been accepted as inevitable.

Many modern integrated circuits incorporate testing and or configuration means allowing the circuit to be tested and or configured as part of the manufacturing process. This typically takes place only once, before the individual integrated circuits are separated. The testing and or configuration means typically allows this to be carried out conveniently with standard probe testing.

The benefit of configuring the integrated circuit at this stage is that a manufacturer can adjust a parameter more accurately than normal manufacturing tolerance allows, select a particular set of parameters for the intended application, set up a unique identity for the individual integrated circuit, or any other such function as the integrated circuit designer may conceive. In order to achieve this, the testing and or configuration means comprises electrical connection means or additional circuitry or more typically both electrical connection means and additional circuitry. There are many known arrangements in the semiconductor industry for providing such connection means and/or circuitry, the particular details of which do not form part of this invention.

Once testing and or configuration have been carried out then there is no further need for the testing and or configuration means. As this is the case, the area of the integrated circuit comprising the testing and or configuration means is no longer useful. This means that the separated integrated circuits are each larger than they need to be to perform their designated function. This means limits the number of integrated circuits that can fit on to a single wafer thus increasing the cost of manufacture per integrated circuit.

It is therefore an object of the present invention to provide a method of manufacturing integrated circuits which overcomes or alleviates the above problems. According to a first aspect of the present invention there is provided a method of manufacturing integrated circuits comprising the following steps: forming an array of integrated circuits on a wafer, each integrated circuit being provided with dedicated configuration means; configuring said integrated circuits using said configuration means; and separating the individual integrated circuits from the array by cutting along scribe channels provided between the integrated circuits in the array wherein said dedicated configuration means for each integrated circuit is wholly or partially formed in a scribe channel adjacent to said integrated circuit.

If the configuration means are implemented within the scribe channels in this manner, they are destroyed during the separation process thus producing a smaller integrated circuits. As this is the case, more integrated circuits can be formed on a single wafer thus using the available wafer more efficiently and providing significant cost savings.

Preferably the configuration means are operative to test the integrated circuit in addition to configuring the integrated circuit. h a preferred embodiment, the configuration means configure the integrated circuit by writing parameters to a non-volatile memory means (TSTVM) incorporated in the integrated circuit. Preferably, the configuration means comprises writing means connected to said NVM and one or more connection means for connecting the writing means to external circuitry. In alternative embodiments, either the writing means or the connection means may be omitted if desired, h further alternative embodiments the configuration means may comprise additional components or circuitry having particular desired functions.

Preferably, the integrated circuits are formed in a square or rectangular array and the scribe channels comprise two series of parallel channels, each series of channels rumiing in a direction orthogonal to the other series. If the integrated circuits are formed in an array other than a rectangular or square array, appropriate scribe channels may be provided as necessary. hi a square or rectangular arrays, the configuration means may be provided either in a single scribe channel adjacent to one side of the integrated circuit or may alternatively be provided in two or more scribe channels running adjacent to two or more sides of the integrated circuit. In any of the above cases, the limitation on the positioning of configuration means in the scribe channels other than their physical size and the convenience of the integrated circuit designer is that the overall shape of the combined integrated circuit and configuration means should tessellate when provided in an array.

Preferably each integrated circuit additionally incorporates interface means for connecting said NNM to said configuration means. Most preferably, said interface means is provided towards the periphery of said integrated circuit between said ΝNM and said configuration means. Preferably, the interface means is switchable between a configuration mode and a non-configuration mode and is operative to connect said configuration means to said NNM only when switched to said configuration mode. Preferably the interface means is disabled when in non-configuration mode. Preferably, said connection means are adapted to facilitate connection to a probe tester. Preferably the interface means may only be switched to said configuration mode by signals received from said probe tester. Preferably the connection means and the interface means may also enable faster testing of the integrated circuit by enabling testing to be carried out in configuration mode in a more effective and faster manner than can be carried out in normal mode. The time saved per integrated circuit may be small but the time saving per wafer can be considerable as up to 10,000 integrated circuits may be formed on a single wafer.

When the integrated circuits are separated, each dedicated configuration means is destroyed and electrical connections between the configuration means and the integrated circuit are broken. Preferably, the saw used to make the cuts is sufficiently thick to ensure the configuration means is destroyed. The separation process may cause the broken connections to be shorted together. The interface means is thus preferably adapted to be able to withstand such effects.

Destruction of the configuration means also has the beneficial effect that it is not possible for persons to reconfigure the integrated circuits and thus prevents illicit reprogramming of such integrated circuits. According to a second aspect of the present invention there is provided an integrated circuit manufactured by the method of the first aspect of the present invention.

The integrated circuit may incorporate any or all of the features described in relation to the first aspect of the invention as appropriate. hi order that the invention is more clearly understood, it will now be described further herein, by way of example only and with reference to the following drawings in which:

Figure 1 is a schematic diagram showing testing and configuration means provided on an integrated circuit;

Figure 2 is a schematic diagram showing how integrated circuits such as that shown in figure 1 may be manufactured as part of an array;

Figure 3 is a schematic diagram showing how integrated circuits may be manufactured as part of an array according to the present invention; and

Figure 4 is a schematic diagram of an integrated circuit of the type shown in figure 3 showing an interface means for testing and configuration means.

Referring now to figure 1, a conventional integrated circuit, 101 is formed on a silicon wafer and has one or more configurable parameters. The configurable parameters are stored in non- volatile memory means (NNM) 102. ΝVM may include any of the known means of non volatile storage including such means as fusible links, zener zapping, and one time programmable memory. Parameter data is written into the NNM 102 by configuration means 103, said configuration means 103 being provided for the purpose of writing data to the ΝNM 102. The configuration means 103 comprises connection means 105, for facilitating connection to external circuitry, and writing means 104. In alternative embodiments the configuration means 103 may comprise writing means only or connection means only, said connection means connecting the ΝNM 102 to external writing means.

The integrated circuit 101 is one of an array of like integrated circuits 101 formed on a silicon wafer 200 as shown in figure 2. Once formed the integrated circuits 101 are tested and configured before being separated. The configuration means 103 (as above comprising connection means 105 and writing means 104) is adapted such that it can be used for testing as well as configuration by connection to a standard testing probe. Each integrated circuit 101 has bond pads 107, for making connections to other circuitry during normal use. Each integrated circuit 101 is also surrounded by scribe channels 202, along which cuts are made to separate the individual integrated circuits 101.

The width 207, of the scribe channels 202 is determined by the width of the saw making the cuts and by the width of the areas adjacent to the cut damaged by the cutting process. In figure 2, the width 207 of the scribe channels 202 is a significant percentage of the width 206 of each integrated circuit 101. This means that a

considerable proportion of the area of silicon wafer 200 is lost during the cutting process. Losing a proportion of the silicon wafer 200 in this manner decreases the amount of integrated circuits it is possible to fit on to a single silicon wafer and consequently increases the cost of manufacturing such integrated circuits 101.

Figure 3 shows an array of integrated circuits 201 manufactured according to the method of the present invention. Each integrated circuit 201 is identical to integrated circuits 101 shown in figures 1 & 2 except that in integrated circuits 201 the configuration means 103 (as above comprising connection means 105 and writing means 104) is provided in the area of the scribe channels 202. The configuration means 103 are used to both to test and configure the integrated circuits in the manner described above. The connection means 105 are typically adapted such that a standard probe tester may be used for the testing and configuration process.

Once testing and configuration is complete, the individual integrated circuits 201 are separated by cutting along the scribe channels 202. This destroys the configuration means 103 provided in the scribe channels 202. By providing the configuration means 103 in a scribe channel, the width of each integrated circuit 201 is reduced relative to integrated circuit 101. This is shown by comparing the width 206 of integrated circuit 101 with the width of integrated circuits 201 as is shown in figure 3. As the integrated circuits 201 are narrower than the integrated circuits 101, more integrated circuits 201 can be formed on a single wafer 200. This reduces the overall cost of manufacturing each integrated circuit 201.

In the embodiment of figure 3, the scribe channels 207 pass through the array in two orthogonal directions and the configuration means are shown only in the scribe channels 207 running in one of the two directions. It is however possible that the configuration means can be implemented in scribe channels 207 running in both directions. For instance, some parts of the configuration means may be provided in the portions of the scribe channels 207 directly below each integrated circuit 201 in figure 3. In further alternative embodiments wherein the integrated circuits are not formed in a square or rectangular array, there may be scribe channels 207 in more than two directions and said scribe channel directions may or may not be orthogonal. In all cases, the overall shape of the integrated circuit 201 and its dedicated configuration means 103 should tessellate in order that the integrated circuits 201 can conveniently be manufactured in an array formed on a wafer. Referring now to figure 4, the integrated circuit 201 additionally comprises interface means 401 provided on the integrated circuit 201 between the writing means 104 and the NNM 102. The interface 401 means are adapted to isolate the configuration means 103 (as above comprising connection means 105 and writing means 104) from the ΝNM 102 unless they are switched to configuration mode. In this manner the interface means 401 can be switched to configuration mode after the circuit is formed to allow testing and configuration to occur and can then be immediately switched out of configuration mode before separation preventing the integrated circuit 201 from being reconfigured inadvertently at a later date. Conveniently, the interface means 401 can be arranged to switched in to and out of configuration mode by signals received from a testing probe. Preferably the interface means is arranged to default to non configuration mode on power on. Preferably the interface means is arranged to default to non configuration mode after a period of inactivity. The interface means 401 is additionally adapted to withstand effects caused by the destruction of the configuration means 103 during the separation process and potential shorts after separation between electrical connections provided to run between said interface means 401 and said configuration means 103. It is of course to be understood that the invention is not to be limited to the details of the above embodiment which is described by way of example only.

Claims

1. A method of manufacturing integrated circuits comprising the following steps: forming an array of integrated circuits on a wafer, each integrated circuit being provided with dedicated configuration means; configuring said integrated circuits using said configuration means; and separating the individual integrated circuits from the array by cutting along scribe channels provided between the integrated circuits in the array wherein said dedicated configuration means for each integrated circuit is wholly or partially formed in a scribe channel adjacent to said integrated circuit.

2. A method as claimed in claim 1 wherein the configuration means are operative to test the integrated circuit in addition to configuring the integrated circuit.

3. A method as claimed in claim 1 or claim 2 wherein the configuration means configure the integrated circuit by writing parameters to a non-volatile memory means (NNM) incorporated in the integrated circuit.

4. A method as claimed in claim 3 wherein the configuration means comprises writing means connected to said ΝNM and one or more connection means for connecting the writing means to external circuitry.

5. A method as claimed in any preceding claim wherein the integrated circuits are formed in a square or rectangular array.

6. A method as claimed in claim 5 wherein the scribe channels comprise two series of parallel channels, each series of channels running in a direction orthogonal to the other series.

7. A method as claimed in any preceding claim wherein the configuration means are provided in a single scribe channel adjacent to one side of the integrated circuit.

8. A method as claimed in any preceding claim wherein the configuration means are provided in two or more scribe channels rumiing adjacent to two or more sides of the integrated circuit.

9. A method as claimed in any one of claims 3 to 8 wherein each integrated circuit additionally incorporates interface means for connecting said NNM to said configuration means.

10. A method as claimed in claim 9 wherein said interface means is provided towards the periphery of said integrated circuit between said ΝNM and said configuration means.

11. A method as claimed in claim 9 or claim 10 wherein the interface means is switchable between a configuration mode and a non-configuration mode.

12. A method as claimed in claim 11 wherein the interface means is is operative to connect said configuration means to said ΝNM only when switched to said configuration mode.

13. A method as claimed in claim 12 wherein the interface means is disabled when in non-configuration mode.

14. A method as claimed in any one of claims 4 to 13 wherein said connection means are adapted to facilitate connection to a probe tester.

15. A method as claimed in claim 14 wherein the interface means may only be switched to said configuration mode by signals received from said probe tester.

16. A method as claimed in any preceding claim wherein when the integrated circuits are separated, each dedicated configuration means is destroyed and electrical connections between the configuration means and the integrated circuit are broken.

17. A method as claimed in any preceding claim wherein the cuts are made by a saw which is sufficiently thick to ensure the configuration means is destroyed.

18. A method as claimed in any one of claims 9 to 17 wherein the interface means is adapted to be able to withstand shorting and other effects caused during separation of the integrated circuits.

19. An integrated circuit manufactured according to the method of any preceding claim.