WO2005091714A2 - Apparatus and methods for multi-level sensing in a memory array - Google Patents

Apparatus and methods for multi-level sensing in a memory array Download PDF

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Publication number
WO2005091714A2
WO2005091714A2 PCT/IL2004/001107 IL2004001107W WO2005091714A2 WO 2005091714 A2 WO2005091714 A2 WO 2005091714A2 IL 2004001107 W IL2004001107 W IL 2004001107W WO 2005091714 A2 WO2005091714 A2 WO 2005091714A2
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Prior art keywords
analog voltage
cell
signal
memory
time delay
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PCT/IL2004/001107
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French (fr)
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WO2005091714A3 (en
Inventor
Oleg Dadashev
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Saifun Semiconductors Ltd.
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Publication of WO2005091714A2 publication Critical patent/WO2005091714A2/en
Publication of WO2005091714A3 publication Critical patent/WO2005091714A3/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells

Definitions

  • the present invention relates generally to semiconductor memories, and more particularly to devices for multi-level sensing of signals received from a memory cell.
  • RAM random access memory
  • ROM devices such as random access memory (RAM), read-only memory
  • a memory device includes an array of memory cells and peripheral supporting systems for managing, programming/erasing and data retrieval operations.
  • SA sense amplifier
  • sense amplifiers determine the logical value stored in a cell by comparing the output of the cell (voltage or current) with a threshold level (voltage or current). If the output is above the threshold, the cell is determined to be erased (with a logical value of 1) and if the output is below the threshold, the cell is determined to be programmed (with a logical value of 0).
  • the threshold level is typically set as a level between the expected erased and programmed levels, which is high enough (or sufficiently far from both expected levels) so that noise on the output will not cause false results.
  • FIG. 1 An example of a prior art sense amplifier circuit is shown in Fig. 1. This sense amplifier circuit is similar to a sense amplifier described in US Patent 6,469,929 to
  • FIG. 1 illustrates a prior art sensing system for a memory array 110, which includes a plurality of memory cells arranged in any number of rows and columns.
  • a memory cell 111 is to be read (i.e. sensed).
  • Memory cell 111 has its drain and source terminals coupled to array bit lines BN and BN+1 and its control terminal coupled to a word line Wl.
  • Memory cell 111 is selectively coupled to a system bit line BL using a column decoder 104 (for selecting the array bit lines) and a row decoder 103 (for selecting the word lines).
  • the system bit line BL may include an associated parasitic capacitance CBL that is proportional to the number of memory cells coupled to the selected array bit line.
  • a memory cell 113 has its drain and source terminals coupled to array bit lines BM and BM+1 and its control terminal coupled to a word line Wl.
  • Memory cell 113 is selectively coupled to a system bit line BL_REF using a column decoder 105 (for selecting the array bit lines) and a row decoder 106 (for selecting the word lines).
  • the system bit line BL may include an associated parasitic capacitance CREF_BL that is proportional to the number of memory cells coupled to the selected array bit line.
  • the array bit line BN is coupled to the system bit line BL, the array bit line BN+1 is coupled to a predetermined voltage (e.g. ground), and the word line Wl is coupled to a read voltage (e.g., 3 volts).
  • a predetermined voltage e.g. ground
  • the word line Wl is coupled to a read voltage (e.g., 3 volts).
  • the system bit line BL may be charged to a predetermined level (e.g., approximately 2N) before the sensing of memory cell 111.
  • the optimal charging of the system bit line BL may facilitate a quick transition to the predetermined voltage without overshooting this predetermined voltage.
  • This charging operation may be initiated using a charge initiation device P2 and advantageously controlled using a control unit 120 (control unit 121 for the right side of Fig. 1) that quickly and efficiently charges the system bit line BL.
  • an active signal CHARGE turns on charge initiation device P2 (P7 for the right side of Fig. 1).
  • Charge initiation device P2 may comprise a P OS (p-channel metal oxide semiconductor) transistor, wherein the active signal CHARGE is a logic 0.
  • P OS p-channel metal oxide semiconductor
  • charge initiation device P2 transfers a pull-up signal provided by the sense amplifier 145 (explained in detail below) to control unit 120.
  • Control unit 12O may comprise a static clamp including an ⁇ MOS
  • the transistor Nl may have its drain connected to charge initiation device P2 and its source connected to system bit line BL.
  • Transistor Nl receives a bias voltage NB on its gate.
  • Bias voltage NB is the gate bias voltage for transistor ⁇ l as defined by: NT ⁇ VB ⁇ NBLD+VT ⁇ wherein VBLD is the desired voltage on bit line BL and VTN is the threshold voltage of the n-type transistor (e.g., 0.6N).
  • VBLD is the desired voltage on bit line BL
  • VTN is the threshold voltage of the n-type transistor (e.g., 0.6N).
  • transistor ⁇ l charges bit line BL very quickly to VB-VT ⁇ .
  • transistor ⁇ l transitions to non-conducting, i.e. the static clamp deactivates, and the dynamic clamp is activated (as explained below).
  • the dynamic clamp of control unit 120 may include PMOS transistor
  • the dynamic clamp further comprises a comparator Cl (C2 for the right side of Fig. 1), which compares a reference voltage BIAS and the bit line voltage BL and then outputs a signal VG representative of that comparison. Specifically, comparator Cl outputs a low signal VG if VBL is less than BIAS and outputs a high signal VG if VBL is greater than BIAS (or if comparator Cl is disabled).
  • the reference voltage BIAS may be approximately equal to the desired bit line voltage VBLD on the system bit line BL.
  • the transistor PI receives the signal VG on its control gate.
  • Sense amplifier 145 may include first stages 130 and 131 and second stage
  • the first stage 130 includes a pull-up device N4, which is an NMOS transistor having its drain and gate connected to a supply voltage VDD and its source connected to charge initiation device P2, and a current sensing device P3, which is a PMOS transistor having its drain and gate connected to charge initiation device P2 and its source connected to the supply voltage VDD. Note that in this configuration, current sensing device P3 advantageously functions as a diode, which is explained in further detail below. [0016]
  • the first stage 131 has an identical configuration to first stage 130.
  • first stage 131 includes a pull-up device N3, which is an NMOS transistor having its drain and gate connected to a supply voltage VDD and its source connected to charge initiation device P7, and a current sensing device P6, which is a PMOS transistor having its drain and gate connected to charge initiation device P7 and its source connected to the supply voltage VDD.
  • a pull-up device N3 which is an NMOS transistor having its drain and gate connected to a supply voltage VDD and its source connected to charge initiation device P7
  • a current sensing device P6 which is a PMOS transistor having its drain and gate connected to charge initiation device P7 and its source connected to the supply voltage VDD.
  • both pull-up transistor N4 (N3) and current sensing device P3 (P6) conduct strongly.
  • the system bit line BL initially receives a pull-up voltage of NDD-VTN via pull-up transistor N4 ( 3).
  • the voltage on the system bit line BL increases to NDD-NTP, wherein NTP is the threshold voltage of the PMOS transistor.
  • NTP is the threshold voltage of the PMOS transistor.
  • the voltage NDD-NTP is substantially equal to the desired system bit line voltage VBLD. At this point, this increased voltage on the system bit line BL turns off pull-up transistor ⁇ 4 (N3).
  • current sensing device P3 (P6) is connected as a diode, only current IBL (IBL_REF) is detected. Therefore, depending on the state of the sensed memory cell, a predetermined current can flow through current sensing device P3 (P6).
  • a latch circuit 141 may amplify and compare currents II and 12.
  • VDD_MLN a minimum voltage
  • VDD_MIN VDIODE_MAX + VBL_MIN + Vp ⁇ /p 8 + Vp 2 /p (1)
  • VDIODE_MAX is the maximum voltage drop across
  • VBL_MIN is the minimum acceptable bit line voltage for the non- volatile memory technology
  • VP1/P8 is the drain-to-source voltage drop of PMOS transistor PI (or PMOS transistor P8)
  • VP2/P7 equal to the drain-to-source voltage drop on PMOS transistor P2 (or PMOS transistor P7).
  • VDIODE_MAX is equal to 1.0 Volt
  • VBL_MLN is equal to 1.8 Volts
  • VP1/P8 and VP2/P7 are equal to 0.05 Volts
  • the minimum supply voltage VDD_MIN is equal to 2.9 Volts (1.8V + IV + 0.05V + 0.05V). In such a case, memory device 100 would not be usable in applications that use a VDD supply voltage lower than 2.9 Volts.
  • sense amplifier first stages 130 and 131 are sensitive to noise in the VDD supply voltage. If, during a read operation, the VDD supply voltage rises to an increased voltage of VDD_OVERSHOOT, then the voltages VSAl and VSA2 on the drains of PMOS transistors P3 and P6 rise to a level approximately equal to VDD_OVERSHOOT minus a diode voltage drop. If the VDD supply voltage then falls to a reduced voltage of VDDJUNDERSHOOT, then transistors P3 and P6 may be turned off. At this time, sense amplifier first stages 130 and 131 cannot operate until the cell currents IBL and IBL_REF discharge the voltages VSAl and VSA2. If the cell cunent IBL is low, then sense amplifier first stage 130 will remain turned off until the end of the read operation, thereby causing the read operation to fail.
  • the present invention seeks to provide apparatus and methods for multi-level sensing in a memory array, as is described more in detail hereinbelow. [0025] The present invention enables multi-level sensing at a lower voltage operation. The multi-level sensing may not be sensitive to Vdd noise (over/under shoots). [0026] There is thus provided in accordance with an embodiment of the invention a method for sensing a signal received from an anay cell within a memory anay, the method including the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory anay, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal.
  • the method further includes providing a reference unit with a reference cell having a similar structure and a similar cunent path therethrough to that of the array cell, and providing a drain driver for driving drain bit lines of the memory array and reference drain bit lines of the reference unit, wherein the drain driver generates the analog voltage Vddr.
  • the method further includes discharging the memory array and the reference unit, charging the memory array and the reference unit so as to generate an array cell signal and a reference signal, respectively, and a timing signal, generating a read signal when the timing signal reaches a predefined voltage level, and generating a sensing signal from the difference of the cell and reference signals once the read signal is generated.
  • a method for sensing a memory cell including the steps of transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell.
  • the time delay may include a digital signal delay.
  • At least one of rise and fall times of the time delays may be compared.
  • Transforming the signal from the memory cell to the time delay may include generating an analog voltage Vddr proportional to a cunent of the memory cell.
  • the analog voltage Vddr may be compared with a reference analog voltage Vcomp to generate an output digital signal.
  • apparatus for sensing a signal received from an array cell within a memory array, the apparatus including a drain driver adapted to generate an analog voltage Vddr proportional to a current of a selected anay cell of the memory anay, and a comparator adapted to compare the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal.
  • a reference unit may be provided with a reference cell having a similar structure and a similar cunent path therethrough to that of the anay cell, wherein the drain driver is adapted to drive drain bit lines of the memory array and reference drain bit lines of the reference unit.
  • a data unit may receive the output digital signal.
  • the comparator compares the analog voltage Vddr with a reference analog voltage Vcomp and generates the output digital signal in the following manner: if the analog voltage Vddr is greater than the reference analog voltage Vcomp then a low output digital signal is output, and if the analog voltage Vddr is not greater than the reference analog voltage Vcomp then a high output digital signal is output.
  • apparatus for sensing a memory cell including a driver adapted to transform a signal from a memory cell to a time delay, and a comparator adapted to compare the time delay to a time delay of a reference cell.
  • FIG. 1 is a simplified illustration of a prior art sensing system for a memory anay, which includes a plurality of memory cells arranged in any number of rows and columns;
  • FIG. 2 is a simplified block diagram of a memory sensing system, constructed and operative in accordance with an embodiment of the present invention
  • FIG. 3 is a simplified block diagram of a memory cell anay, which may be read by the memory sensing system, in accordance with an embodiment of the present invention
  • Fig. 4 is a simplified block dia ram of a drain driver of the memory sensing system, constructed and operative in accordance with an embodiment of the present invention
  • Fig. 5 is a simplified graphical illmstration of waveforms of the drain driver signals, in accordance with an embodiment of th-e present invention
  • Fig. 6 is a simplified graphical illustration of waveforms of comparator signals of the memory sensing system of Fig. 2, in accordance with an embodiment of the present invention
  • Fig. 7 is a simplified block diagram of a data unit of the memory sensing system, constructed and operative in accordance with an embodiment of the present invention
  • Fig. 8 is a simplified graphical illustration of the distribution of the threshold voltages of reference memory cells of the memory sensing system, in accordance with an embodiment of the present invention
  • Fig. 9 is a simplified graphical illustration of waveforms of the drain driver signals, in accordance with another embodiment of the present invention, different from that of Fig. 5;
  • FIG. 10 is a simplified block diagram of " a memory sensing system, in accordance with another embodiment of the present invention.
  • Fig. 11 is a simplified block diagram- of the drain driver for the embodiment of Fig. 10, constructed and operative in accordance with an embodiment of the present invention.
  • Fig. 12 is a simplified graphical illustration of the waveforms of the drain driver signals, for the embodiment of Fig. 10.
  • FIG. 2 illustrates a memory sensing system, constructed and operative in accordance with an embodiment of the present invention.
  • Fig. 3 illustrates a memory cell anay 10, which may be read by the memory sensing system, in accordance with an embodiment of the present invention.
  • Memory cells of array 10 are ananged in row and columns, and each memory cell is accessed during read, program, or erase operations by applying appropriate voltages associated word and bit lines.
  • the gate terminal of memory cell MCji is preferably connected to an associated word line (WL) WLi, and the drain and source terminals are preferably connected to associated bit lines (BLs) BLj and BLj+1.
  • Memory cells of anay 10 may be addressed using a word line control circuit, i.e., row decoder 12, and a bit line control circuit, i.e., column decoder 14, according to input addresses signals Xaddr ⁇ h:0> and Yaddr ⁇ p:0>, respectively.
  • Row decoder 12 provides an appropriated word line voltage to WL.
  • Column decoder 14 connects selected drain bit lines (DBL) and source bit lines (SBL) of a memory cell to DBL and SBL inputs conespondingly.
  • DBL drain bit lines
  • SBL source bit lines
  • a plurality of memory cells connected to the same selected word line may be accessed simultaneously.
  • k+1 memory cells may be accessed simultaneously.
  • column decoder 14 may have k+1 DBL and SBL nodes: DBL ⁇ k:0>, SBL ⁇ k:0>.
  • the nodes SBL ⁇ k:0> may be connected to ground (GND) during the read operation.
  • the source voltage of the selected memory cells may be close to GND.
  • the memory sensing system may comprise one or more reference units 16 with one or more reference memory cells (RMCs) having a structure and cunent path therethrough similar to that of the array cells.
  • the refere-nce unit may emulate the elements found in the cunent path from node DBL through MC to be read to node SBL. This may provide RC (resistance-capacitance) matching of the two paths.
  • Drain drivers 18 may be provided for driving the drain bit line s of anay 10 and the reference drain bit lines of reference units 16. Reference is now ma.de to Fig. 4, wliich illustrates an example of a suitable drain driver 18, in accordance with an embodiment of the present invention.
  • Drain driver 18 may comprise a PMOS (p-channel metal oxide semiconductor) pull-up transistor M0, wherein its gate terminal receives a logical signal input (chargeb), its source terminal receives a voltage input Nps and its drain tenninal is connected to a node 20.
  • An ⁇ MOS (n-channel metal oxide semiconductor) clamp transistor Ml may provided whose drain terminal is connected to the drain terminal of PMOS pull-up transistor M0 via node 20, whose gate terminal receives an input Vblr and whose source terminal is connected to the DBL input of the column decoder 14.
  • An integrated capacitor Cint may be com ected to a node 21, which is connected to a node 20 and a node ddr.
  • Drain driver 18 may execute two functions during a read opera-tion: a. provision of the required drain voltage of a memory cell during the read operation, and b. generation of a signal at node ddr (voltage Vddr) proportional to t e cunent of a selected memory cell.
  • the voltage Nps enters the drain of the ⁇ MOS clamp transistor Ml through the open PMOS pull-up tiransistor M0.
  • the reduced voltage is transfened from the column decoder 14 to the drain terminal of the memory cell of the anay 10.
  • Fig. 5 which illustrates waveforms of the drain driver signals, in accordance with an embodiment of the present invention.
  • a logical signal chargeb is high and therefore PMOS pull-up transistor M0 is turned off (not conducting).
  • the signal chargeb goes down to 0V and turns on PMOS pull-up transistor M0 (i.e., it is now conducting).
  • the signal ddr rises to Vps, and the drain bit line of the selected memory cell (both DBL nodes) becomes charged to voltage Vd.
  • Cunent begins to flow through the memory cell.
  • the cunent of the path asymptotically stabilizes at the memory cell (MC) read cunent level, IMC.
  • the signal chargeb returns to its high level Vps, thereby turning off PMOS transistor M0 again.
  • a signal boost may be optionally coupled to ground.
  • the signal boost may rise from OV to Vboost.
  • the voltage of node ddr rises from its previous level Vps to voltage Vps + Vbst, where
  • Vbst Vboost*C ⁇ /C in t (2) wherein C ⁇ is the total capacity of the node ddr; [0058] Since the capacity Cint is significantly greater than other (parasitic)
  • I ⁇ is the cunent through node DBL ⁇ , which equals I MC - [0060]
  • cunent IMCij is integrated on capacitor Ciot.
  • the voltage Nddr varies linearly with respect to the selected MC cunent IMCji and varies inversely with respect to the capacitance of capacitor Cint.
  • the ⁇ MOS transistor Ml works in saturation.
  • the capacitance of the node ddr may be independent from the drain bit line capacitance, which may be a few orders of magnitude greater than Cint.
  • the voltage of the nodes DBL and BL may remain at Nd duiing the time that Nddr(t) is developing, and therefore the drain-source voltage of the selected memory cell MCji remains constant as well.
  • the drain drivers 18 for driving the drain bit lines of array 10 are preferably identical to the drain drivers for the reference units 16 (i.e., drain drivers ⁇ ref0:refm> in Fig. 2). Therefore, the signals rddr ⁇ m:0> are developed similarly to ddr(t):
  • I ⁇ is the read cunent of ⁇ -th reference memory cell.
  • the memory sensing system may comprise one or morre comparators 22 for anay 10 (i.e., comparators ⁇ 0:k>) and for reference units 16 (i.e., comparators ⁇ ref0:refm>).
  • Comparator 22 compares the analog voltage Vddr with a reference analog voltage Vcomp and generates an output digital signal cmp according "to the follow rule shown in Table 1 : Table 1
  • a voltage of the signal Vcomp is disposed in an interval [Vd, Vps + Vbst]. Hence, in the time interval TI to T2, all signals cmp ⁇ 0:k> are low (logical level "0"). The signal cmp may be inverted to a high logical level at time:
  • each comparator signal of the comparators 22 may be transmitted to the input of a data unit 24 together with the output signals lat ⁇ m:0> of the reference comparators.
  • Fig. 7 illustrates one example of data unit 24, constructed and operative in accordance with an embodiment of the present invention.
  • the signal cmp is provided to the D-input of m digital latches 26.
  • Each digital latch 26 may receive one of the lat signals of the reference comparators at its Eb-input.
  • the digital latches 26 may function according to the follow rule shown in Table 3 : Table 3 Eb Q
  • the reference units 16 may comprise reference memory cells (RefO to Refm). Reference is now made to Fig. 8, which illustrates a distribution of the threshold voltages (VtrefO to Ntrefm) of the reference memory cells, in accordance with an embodiment of the present invention.
  • the threshold voltages may be distributed in m+1 zones in intervals along the Nt axis.
  • the threshold voltage Nto of some cell which corresponds with the channel number ⁇ of the sensing (dbl ⁇ >-ddr ⁇ >-cmp ⁇ >), may be in zone ⁇ .
  • the threshold voltage Nto is greater than the threshold voltages in the previous zones (that is, NtrefO to Ntref( ⁇ -1)), and less than the threshold voltages in the next zones (that is, Ntref ⁇ to Vtrefm).
  • the cunent Io of that cell is greater than the cunent in the next zones (Iref ⁇ to Irefm), and less than the current in the previous zones (IrefO to Iref( ⁇ -1)).
  • An operation voltage Vps of the memory sensing system may equal:
  • VpS_ m in NMl ds + V cd + V M Cds + V c d, (7)
  • N M i ds is the drain/source voltage of the transistor Ml in the drain driver
  • V cd is the column decoder voltage drop
  • Vi ic d s is the drain/source voltage of the memory cell.
  • VDIODE_MAX the minimum supply voltage Vps_min is less than the prior art VDD_MIN (see equation (1) above in the background of the invention) by VDIODE_MAX, and approaches the minimal voltage VBL_MLN.
  • VDIODE_MAX may be approximately equal to one volt, for example. This means that the present invention may be used in applications that use a VDD supply voltage lower than 2.9 V, down to 1.9 V, an improvement of over 34%.
  • the present invention may transform a signal (e.g., current) from the memory cell to a time delay (e.g., a digital signal delay) and compare the time delay to a time delay of a reference cell (e.g., the rise or fall times of the signals).
  • the drain driver operates at a low (close to minimal) voltage to generate the analog signal Vddr.
  • the signal Vddr is preferably linearly dependent upon the memory cell cunent.
  • the memory cell current is preferably integrated on the local capacitor.
  • the present invention may be used as a multi-level sensing system for a multiplicity of reference units.
  • the invention may also be used for a single reference unit.
  • signals from the memory cells are coupled in a one-to-one correspondence to the sense amplifiers.
  • the reference memory cells are coupled in parallel to all of the sense amplifiers. This results in a significant mismatch between two sense amplifier input signals, because one of them (from the array) is connected to a single sense amplifier whereas the other (from the reference) is connected to all of the sense amplifiers. The mismatch may lead to enors in read data.
  • all the analog signals from the anay cells and the reference cells are matched, as described hereinabove.
  • Fig. 9 illustrates waveforms of the drain driver signals, in accordance with another embodiment of the present invention, different from that of Fig. 5.
  • node Vps is connected to the system voltage supply Vdd until a time Tps, when power dissipation is maximal for charging the read path parasitic capacitors. At time Tps, the cunent through node Vps is significantly lower
  • node Vps is switched to a higher voltage supply than
  • Vdd This embodiment may be useful to increase the possible range of boosting Vddr.
  • Fig. 10 illustrates a memory sensing system, in accordance with another embodiment of the present invention
  • Fig. 11 illustrates the drain driver for the embodiment of Fig. 10.
  • the nodes SBL ⁇ k:0> may be connected to the comparator inputs instead of the ddr ⁇ k:0> signals, as shown in Fig. 10.
  • the drain driver circuit is a simplified version of the drain driver circuit of Fig. 4.
  • Fig. 12 illustrates the waveforms of the drain driver signals, in accordance with this embodiment of the invention. The development of the signals
  • SBL ⁇ k:0> may be as described in US Patent 6,128,226 to Eitan and Dadashev, assigned to the common assignee of the present application.

Abstract

A method for sensing a signal (DBL) received from an array cell within a memory array (10), the method comprising the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory array (10), and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal (cmp). A method is also provided for sensing a memory cell by transforming a signal (DBL) from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell (ref. DBL).

Description

Apparatus And Methods For Multi-Level Sensing In A Memory Array
FIELD OF THE INVENTION
[001] The present invention relates generally to semiconductor memories, and more particularly to devices for multi-level sensing of signals received from a memory cell.
BACKGROUND OF THE INVENTION
[002] Memory devices, such as random access memory (RAM), read-only memory
(ROM), non-volatile memory (NVM) and the like, are well known in the art. A memory device includes an array of memory cells and peripheral supporting systems for managing, programming/erasing and data retrieval operations.
[003] These devices provide an indication of the data, which is stored, therein by providing an output electrical signal. A device called a sense amplifier (SA) is used for detecting the signal and determining the logical content thereof.
[004] In general, sense amplifiers determine the logical value stored in a cell by comparing the output of the cell (voltage or current) with a threshold level (voltage or current). If the output is above the threshold, the cell is determined to be erased (with a logical value of 1) and if the output is below the threshold, the cell is determined to be programmed (with a logical value of 0).
[005] The threshold level is typically set as a level between the expected erased and programmed levels, which is high enough (or sufficiently far from both expected levels) so that noise on the output will not cause false results.
[006] An example of a prior art sense amplifier circuit is shown in Fig. 1. This sense amplifier circuit is similar to a sense amplifier described in US Patent 6,469,929 to
Alexander Kushnarenlco and Oleg Dadashev, entitled "Structure and method for high speed sensing of memory array". [007] Fig. 1 illustrates a prior art sensing system for a memory array 110, which includes a plurality of memory cells arranged in any number of rows and columns. For purposes of illustration, assume that a memory cell 111 is to be read (i.e. sensed). Memory cell 111 has its drain and source terminals coupled to array bit lines BN and BN+1 and its control terminal coupled to a word line Wl. Memory cell 111 is selectively coupled to a system bit line BL using a column decoder 104 (for selecting the array bit lines) and a row decoder 103 (for selecting the word lines). The system bit line BL may include an associated parasitic capacitance CBL that is proportional to the number of memory cells coupled to the selected array bit line.
[008] Similarly for a memory array 112, a memory cell 113 has its drain and source terminals coupled to array bit lines BM and BM+1 and its control terminal coupled to a word line Wl. Memory cell 113 is selectively coupled to a system bit line BL_REF using a column decoder 105 (for selecting the array bit lines) and a row decoder 106 (for selecting the word lines). The system bit line BL may include an associated parasitic capacitance CREF_BL that is proportional to the number of memory cells coupled to the selected array bit line.
[009] To read (i.e. sense) the state of memory cell 111 in memory array 110, the array bit line BN is coupled to the system bit line BL, the array bit line BN+1 is coupled to a predetermined voltage (e.g. ground), and the word line Wl is coupled to a read voltage (e.g., 3 volts). The operation of decoders 103 and 104 to provide the above-described coupling is well known and therefore not described in detail herein. [0010] The previous paragraph and the following description hold true, mutatis mutandis, for memory cell 113 in memory array 112, that is, the circuitry on the right side of Fig. 1. [001 1] To ensure that a sense amplifier 145 correctly senses the logic state of memory cell 111, the system bit line BL may be charged to a predetermined level (e.g., approximately 2N) before the sensing of memory cell 111. The optimal charging of the system bit line BL may facilitate a quick transition to the predetermined voltage without overshooting this predetermined voltage. This charging operation may be initiated using a charge initiation device P2 and advantageously controlled using a control unit 120 (control unit 121 for the right side of Fig. 1) that quickly and efficiently charges the system bit line BL.
[0012] Specifically, to initiate a charge operation, an active signal CHARGE turns on charge initiation device P2 (P7 for the right side of Fig. 1). Charge initiation device P2 may comprise a P OS (p-channel metal oxide semiconductor) transistor, wherein the active signal CHARGE is a logic 0. When conducting, charge initiation device P2 transfers a pull-up signal provided by the sense amplifier 145 (explained in detail below) to control unit 120.
[0013] Control unit 12O may comprise a static clamp including an ΝMOS
(n-channel metal oxide semiconductor) transistor Νl (Ν2 for the right side of Fig. 1) and a dynamic clamp including a PMOS transistor PI (P8 for the right side of Fig. 1). The transistor Nl may have its drain connected to charge initiation device P2 and its source connected to system bit line BL. Transistor Nl receives a bias voltage NB on its gate. Bias voltage NB is the gate bias voltage for transistor Νl as defined by: NTΝ<VB<NBLD+VTΝ wherein VBLD is the desired voltage on bit line BL and VTN is the threshold voltage of the n-type transistor (e.g., 0.6N). In this manner, transistor Νl charges bit line BL very quickly to VB-VTΝ. At this point, transistor Νl transitions to non-conducting, i.e. the static clamp deactivates, and the dynamic clamp is activated (as explained below). [0014] The dynamic clamp of control unit 120 may include PMOS transistor
PI having its source connected to charge initiation device P2 (also the drain of transistor Nl) and its drain coupled to bit line BL (also the source of transistor Nl). The dynamic clamp further comprises a comparator Cl (C2 for the right side of Fig. 1), which compares a reference voltage BIAS and the bit line voltage BL and then outputs a signal VG representative of that comparison. Specifically, comparator Cl outputs a low signal VG if VBL is less than BIAS and outputs a high signal VG if VBL is greater than BIAS (or if comparator Cl is disabled). The reference voltage BIAS may be approximately equal to the desired bit line voltage VBLD on the system bit line BL. The transistor PI receives the signal VG on its control gate.
[0015] Sense amplifier 145 may include first stages 130 and 131 and second stage
140. The first stage 130 includes a pull-up device N4, which is an NMOS transistor having its drain and gate connected to a supply voltage VDD and its source connected to charge initiation device P2, and a current sensing device P3, which is a PMOS transistor having its drain and gate connected to charge initiation device P2 and its source connected to the supply voltage VDD. Note that in this configuration, current sensing device P3 advantageously functions as a diode, which is explained in further detail below. [0016] The first stage 131 has an identical configuration to first stage 130.
Specifically, first stage 131 includes a pull-up device N3, which is an NMOS transistor having its drain and gate connected to a supply voltage VDD and its source connected to charge initiation device P7, and a current sensing device P6, which is a PMOS transistor having its drain and gate connected to charge initiation device P7 and its source connected to the supply voltage VDD.
[0017] After charge initiation device P2 (P7 for the right side of Fig. 1) is activated, both pull-up transistor N4 (N3) and current sensing device P3 (P6) conduct strongly. During the charge operation, the system bit line BL initially receives a pull-up voltage of NDD-VTN via pull-up transistor N4 ( 3). Then, via current sensing device P3 (P6), the voltage on the system bit line BL increases to NDD-NTP, wherein NTP is the threshold voltage of the PMOS transistor. Note that the voltage NDD-NTP is substantially equal to the desired system bit line voltage VBLD. At this point, this increased voltage on the system bit line BL turns off pull-up transistor Ν4 (N3). Because current sensing device P3 (P6) is connected as a diode, only current IBL (IBL_REF) is detected. Therefore, depending on the state of the sensed memory cell, a predetermined current can flow through current sensing device P3 (P6).
[0018] Current sensing devices P3 and P6 in first stages 130 and 131, respectively, have current min-ors provided in second stage 140. Specifically, the current IBL through cunent sensing device P3 is reflected in the current II through a PMOS transistor P4, whereas the current IBL_REF through cunent sensing device P6 is reflected in the cunent 12 through a PMOS transistor P5. The ratio of the currents through current sensing device P3 and PMOS transistor P4 defines the gain of first stage 130, whereas the ratio of the current through cunent sensing device P6 and PMOS transistor P6 defines the gain of first stage 131. A latch circuit 141 (e.g., amplifier block) may amplify and compare currents II and 12.
[0019] The sense amplifier 145 may not operate properly unless the VDD supply voltage is greater than a minimum voltage VDD_MLN, which is defined as follows:
VDD_MIN = VDIODE_MAX + VBL_MIN + Vpι/p8 + Vp2/p (1)
[0020] In equation (1), VDIODE_MAX is the maximum voltage drop across
PMOS transistor P3 or PMOS transistor P6, VBL_MIN is the minimum acceptable bit line voltage for the non- volatile memory technology, VP1/P8 is the drain-to-source voltage drop of PMOS transistor PI (or PMOS transistor P8), and VP2/P7 equal to the drain-to-source voltage drop on PMOS transistor P2 (or PMOS transistor P7). [0021] For example, if VDIODE_MAX is equal to 1.0 Volt, VBL_MLN is equal to 1.8 Volts, and VP1/P8 and VP2/P7 are equal to 0.05 Volts, then the minimum supply voltage VDD_MIN is equal to 2.9 Volts (1.8V + IV + 0.05V + 0.05V). In such a case, memory device 100 would not be usable in applications that use a VDD supply voltage lower than 2.9 Volts.
[0022] In addition, sense amplifier first stages 130 and 131 are sensitive to noise in the VDD supply voltage. If, during a read operation, the VDD supply voltage rises to an increased voltage of VDD_OVERSHOOT, then the voltages VSAl and VSA2 on the drains of PMOS transistors P3 and P6 rise to a level approximately equal to VDD_OVERSHOOT minus a diode voltage drop. If the VDD supply voltage then falls to a reduced voltage of VDDJUNDERSHOOT, then transistors P3 and P6 may be turned off. At this time, sense amplifier first stages 130 and 131 cannot operate until the cell currents IBL and IBL_REF discharge the voltages VSAl and VSA2. If the cell cunent IBL is low, then sense amplifier first stage 130 will remain turned off until the end of the read operation, thereby causing the read operation to fail.
[0023] Accordingly, it is desirable to provide a sensing system that can accommodate low supply voltages and tolerate supply voltage fluctuations.
SUMMARY OF THE INVENTION
[0024] The present invention seeks to provide apparatus and methods for multi-level sensing in a memory array, as is described more in detail hereinbelow. [0025] The present invention enables multi-level sensing at a lower voltage operation. The multi-level sensing may not be sensitive to Vdd noise (over/under shoots). [0026] There is thus provided in accordance with an embodiment of the invention a method for sensing a signal received from an anay cell within a memory anay, the method including the steps of generating an analog voltage Vddr proportional to a current of a selected array cell of the memory anay, and comparing the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal. [0027] In accordance with an embodiment of the invention the method further includes providing a reference unit with a reference cell having a similar structure and a similar cunent path therethrough to that of the array cell, and providing a drain driver for driving drain bit lines of the memory array and reference drain bit lines of the reference unit, wherein the drain driver generates the analog voltage Vddr.
[0028] Further in accordance with an embodiment of the invention if the analog voltage Vddr is greater than the reference analog voltage Vcomp then a low output digital signal is output, and if the analog voltage Vddr is not greater than the reference analog voltage Vcomp then a high output digital signal is output.
[0029] In accordance with an embodiment of the invention the method further includes discharging the memory array and the reference unit, charging the memory array and the reference unit so as to generate an array cell signal and a reference signal, respectively, and a timing signal, generating a read signal when the timing signal reaches a predefined voltage level, and generating a sensing signal from the difference of the cell and reference signals once the read signal is generated. [0030] There is also provided in accordance with an embodiment of the invention a method for sensing a memory cell, the method including the steps of transforming a signal from a memory cell to a time delay, and sensing the memory cell by comparing the time delay to a time delay of a reference cell. The time delay may include a digital signal delay. At least one of rise and fall times of the time delays may be compared. Transforming the signal from the memory cell to the time delay may include generating an analog voltage Vddr proportional to a cunent of the memory cell. The analog voltage Vddr may be compared with a reference analog voltage Vcomp to generate an output digital signal.
[0031] There is also provided in accordance with an embodiment of the invention apparatus for sensing a signal received from an array cell within a memory array, the apparatus including a drain driver adapted to generate an analog voltage Vddr proportional to a current of a selected anay cell of the memory anay, and a comparator adapted to compare the analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal.
[0032] In accordance with an embodiment of the invention a reference unit may be provided with a reference cell having a similar structure and a similar cunent path therethrough to that of the anay cell, wherein the drain driver is adapted to drive drain bit lines of the memory array and reference drain bit lines of the reference unit. A data unit may receive the output digital signal.
[0033] Further in accordance with an embodiment of the invention the comparator compares the analog voltage Vddr with a reference analog voltage Vcomp and generates the output digital signal in the following manner: if the analog voltage Vddr is greater than the reference analog voltage Vcomp then a low output digital signal is output, and if the analog voltage Vddr is not greater than the reference analog voltage Vcomp then a high output digital signal is output.
[0034] There is also provided in accordance with an embodiment of the invention apparatus for sensing a memory cell including a driver adapted to transform a signal from a memory cell to a time delay, and a comparator adapted to compare the time delay to a time delay of a reference cell.
BRIEF DESCRIPTION O-F THE DRAWINGS
[0035] The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the appended drawings in which:
[0036] Fig. 1 is a simplified illustration of a prior art sensing system for a memory anay, which includes a plurality of memory cells arranged in any number of rows and columns;
[0037] Fig. 2 is a simplified block diagram of a memory sensing system, constructed and operative in accordance with an embodiment of the present invention;
[0038] Fig. 3 is a simplified block diagram of a memory cell anay, which may be read by the memory sensing system, in accordance with an embodiment of the present invention;
[0039] Fig. 4 is a simplified block dia ram of a drain driver of the memory sensing system, constructed and operative in accordance with an embodiment of the present invention;
[0040] Fig. 5 is a simplified graphical illmstration of waveforms of the drain driver signals, in accordance with an embodiment of th-e present invention;
[0041] Fig. 6 is a simplified graphical illustration of waveforms of comparator signals of the memory sensing system of Fig. 2, in accordance with an embodiment of the present invention;
[0042] Fig. 7 is a simplified block diagram of a data unit of the memory sensing system, constructed and operative in accordance with an embodiment of the present invention; [0043] Fig. 8 is a simplified graphical illustration of the distribution of the threshold voltages of reference memory cells of the memory sensing system, in accordance with an embodiment of the present invention;
[0044] Fig. 9 is a simplified graphical illustration of waveforms of the drain driver signals, in accordance with another embodiment of the present invention, different from that of Fig. 5;
[0045] Fig. 10 is a simplified block diagram of" a memory sensing system, in accordance with another embodiment of the present invention;
[0046] Fig. 11 is a simplified block diagram- of the drain driver for the embodiment of Fig. 10, constructed and operative in accordance with an embodiment of the present invention; and
[0047] Fig. 12 is a simplified graphical illustration of the waveforms of the drain driver signals, for the embodiment of Fig. 10.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
[0048] Reference is now made to Fig. 2, which illustrates a memory sensing system, constructed and operative in accordance with an embodiment of the present invention. Reference is also made to Fig. 3, which illustrates a memory cell anay 10, which may be read by the memory sensing system, in accordance with an embodiment of the present invention.
[0049] Memory cells of array 10 are ananged in row and columns, and each memory cell is accessed during read, program, or erase operations by applying appropriate voltages associated word and bit lines. For example, as indicated in Fig. 3, the gate terminal of memory cell MCji is preferably connected to an associated word line (WL) WLi, and the drain and source terminals are preferably connected to associated bit lines (BLs) BLj and BLj+1.
[0050] Memory cells of anay 10 may be addressed using a word line control circuit, i.e., row decoder 12, and a bit line control circuit, i.e., column decoder 14, according to input addresses signals Xaddr<h:0> and Yaddr<p:0>, respectively. Row decoder 12 provides an appropriated word line voltage to WL. Column decoder 14 connects selected drain bit lines (DBL) and source bit lines (SBL) of a memory cell to DBL and SBL inputs conespondingly.
[0051 ] As seen in Figs. 2 and 3, a plurality of memory cells connected to the same selected word line may be accessed simultaneously. For example, k+1 memory cells may be accessed simultaneously. Accordingly, column decoder 14 may have k+1 DBL and SBL nodes: DBL<k:0>, SBL<k:0>. As seen in Fig. 3, in accordance with one embodiment of the sensing method, the nodes SBL<k:0> may be connected to ground (GND) during the read operation. The source voltage of the selected memory cells may be close to GND. [0052] As seen in Fig. 2, the memory sensing system may comprise one or more reference units 16 with one or more reference memory cells (RMCs) having a structure and cunent path therethrough similar to that of the array cells. The refere-nce unit may emulate the elements found in the cunent path from node DBL through MC to be read to node SBL. This may provide RC (resistance-capacitance) matching of the two paths. [0053] Drain drivers 18 may be provided for driving the drain bit line s of anay 10 and the reference drain bit lines of reference units 16. Reference is now ma.de to Fig. 4, wliich illustrates an example of a suitable drain driver 18, in accordance with an embodiment of the present invention. Drain driver 18 may comprise a PMOS (p-channel metal oxide semiconductor) pull-up transistor M0, wherein its gate terminal receives a logical signal input (chargeb), its source terminal receives a voltage input Nps and its drain tenninal is connected to a node 20. An ΝMOS (n-channel metal oxide semiconductor) clamp transistor Ml may provided whose drain terminal is connected to the drain terminal of PMOS pull-up transistor M0 via node 20, whose gate terminal receives an input Vblr and whose source terminal is connected to the DBL input of the column decoder 14. An integrated capacitor Cint may be com ected to a node 21, which is connected to a node 20 and a node ddr. [0054] Drain driver 18 may execute two functions during a read opera-tion: a. provision of the required drain voltage of a memory cell during the read operation, and b. generation of a signal at node ddr (voltage Vddr) proportional to t e cunent of a selected memory cell.
[0055] In order to provide the required drain voltage, the voltage Nps enters the drain of the ΝMOS clamp transistor Ml through the open PMOS pull-up tiransistor M0. The ΝMOS transistor Ml, controlled by voltage Vblr at its gate, clamps its <lrain voltage Vps and transmits a reduced voltage Vd=Vblr-VgsMl to the DBL input of the column decoder 14. The reduced voltage is transfened from the column decoder 14 to the drain terminal of the memory cell of the anay 10.
[0056] The generation of the signal at node ddr is now explained with reference to
Fig. 5, which illustrates waveforms of the drain driver signals, in accordance with an embodiment of the present invention. Before time TI, a logical signal chargeb is high and therefore PMOS pull-up transistor M0 is turned off (not conducting). At time TI, the signal chargeb goes down to 0V and turns on PMOS pull-up transistor M0 (i.e., it is now conducting). During the period of time right after time TI and up to time T2, the signal ddr rises to Vps, and the drain bit line of the selected memory cell (both DBL nodes) becomes charged to voltage Vd. Cunent begins to flow through the memory cell. After the charging process to Vd is completed, the cunent of the path asymptotically stabilizes at the memory cell (MC) read cunent level, IMC.
[0057] Afterwards, at time T2, the signal chargeb returns to its high level Vps, thereby turning off PMOS transistor M0 again. Up until time T2, a signal boost may be optionally coupled to ground. Immediately after time T2, the signal boost may rise from OV to Vboost. In response to the signal boost, the voltage of node ddr rises from its previous level Vps to voltage Vps + Vbst, where
Vbst = Vboost*C∑/Cint (2) wherein C∑ is the total capacity of the node ddr; [0058] Since the capacity Cint is significantly greater than other (parasitic)
capacitors of the node ddr, CΣ∞Cint and Vbs Vboost.
[0059] After time T2, the voltage Vddr decreases according to the equation
Vddrαrø = Vps + VboOSt - Iα*t/Cint, CC=0,k (3) wherein Iα is the cunent through node DBLα, which equals IMC- [0060] As seen from equation (3), cunent IMCij is integrated on capacitor Ciot.
The voltage Nddr varies linearly with respect to the selected MC cunent IMCji and varies inversely with respect to the capacitance of capacitor Cint.
[0061] As long as Nddr is greater than Nd by some margin (e.g., on the order of about 0.2-0.3N) the ΝMOS transistor Ml works in saturation. The capacitance of the node ddr may be independent from the drain bit line capacitance, which may be a few orders of magnitude greater than Cint. The voltage of the nodes DBL and BL may remain at Nd duiing the time that Nddr(t) is developing, and therefore the drain-source voltage of the selected memory cell MCji remains constant as well.
[0062] As mentioned previously, the drain drivers 18 for driving the drain bit lines of array 10 (i.e., drain drivers <0:k> in Fig. 2) are preferably identical to the drain drivers for the reference units 16 (i.e., drain drivers <ref0:refm> in Fig. 2). Therefore, the signals rddr<m:0> are developed similarly to ddr(t):
Vrddrβ(t) = Vps + Vboost - Iβ*t/Cint, β=0,m (4) wherein
Iβ is the read cunent of α-th reference memory cell.
[0063] As seen in Fig. 2, the memory sensing system may comprise one or morre comparators 22 for anay 10 (i.e., comparators <0:k>) and for reference units 16 (i.e., comparators <ref0:refm>). Comparator 22 compares the analog voltage Vddr with a reference analog voltage Vcomp and generates an output digital signal cmp according "to the follow rule shown in Table 1 : Table 1
Figure imgf000016_0001
[0064] A voltage of the signal Vcomp is disposed in an interval [Vd, Vps + Vbst]. Hence, in the time interval TI to T2, all signals cmp<0:k> are low (logical level "0"). The signal cmp may be inverted to a high logical level at time:
Tcsα = T2 + (Vps + Vboost - Vcomp)* Cint/Iα, α=0,k (5)
[0065] A similar equation determines a time when output signals of the comparators <ref0 ÷ refm> may be inverted:
Trcsβ = T2 + (Vps + Vboost - Vcomp)*Cint/Iβ5 β=0,m (6)
[0066] As can be seen from equations (6) and (7), the values Tcsα and Trcsβ are an inverse function of the memory cell current. [0067] Fig. 6 illustrates waveforms of the comparator signals, in accordance with an embodiment of the present invention and the above explanation. [0068] Refening again to Fig. 2, each comparator signal of the comparators 22 may be transmitted to the input of a data unit 24 together with the output signals lat<m:0> of the reference comparators. The data unit 24 may compare the rising time of the comparator signal Trise(cmp) with the rising time Trise(latξ), (ξ=0,...,m) of the output signals lat<m:0> of the reference comparators. Examples of output signals of the data unit 24 are shown in Table 2: Table 2
Figure imgf000017_0001
[0069] Reference is now made to Fig. 7, which illustrates one example of data unit 24, constructed and operative in accordance with an embodiment of the present invention. The signal cmp is provided to the D-input of m digital latches 26. Each digital latch 26 may receive one of the lat signals of the reference comparators at its Eb-input. The digital latches 26 may function according to the follow rule shown in Table 3 : Table 3
Figure imgf000018_0001
Eb Q
[0070] When the Eb signal is a low level (logical "0"), the digital latch 26 transmits input signal D to output Q. When the Eb signal goes to a high level (logical "1"), the digital latch 26 transmits whatever the previous value was to output Q. [0071] The reference units 16 (numbered 0 to m) shown in Fig. 2 may comprise reference memory cells (RefO to Refm). Reference is now made to Fig. 8, which illustrates a distribution of the threshold voltages (VtrefO to Ntrefm) of the reference memory cells, in accordance with an embodiment of the present invention. The threshold voltages may be distributed in m+1 zones in intervals along the Nt axis. For example, the threshold voltage Nto of some cell, which corresponds with the channel number α of the sensing (dbl<α>-ddr<α>-cmp<α>), may be in zone τ. This means that the threshold voltage Nto is greater than the threshold voltages in the previous zones (that is, NtrefO to Ntref(τ-1)), and less than the threshold voltages in the next zones (that is, Ntrefτ to Vtrefm). Accordingly, the cunent Io of that cell is greater than the cunent in the next zones (Irefτto Irefm), and less than the current in the previous zones (IrefO to Iref(τ-1)). Hence, the signal cmp<α> conesponding to that cell rises earlier than signals lat<τ>÷lat<m>, and later than signals lat<0>÷lat<τ-l>. Accordingly, internal signals Q<m:0> of the data unit number α are given by the following equation: Q<(τ-1):0>=0, Q<m:τ>=l. [0072] A data decoder may convert signals Q<m:0> to a final data bus dt<y:0> according to the rule (in decimal form): dtdecimai = Q<0>+Q<l>+Q<2>+...+Q<m-l>+Q<m>. [0073] A binary form of the data may be obtained by a conventional formula for decimal to binary conversion: dtdecimai= dq<0>*2Λ0 + dq<l>*2Λl + dq<2>*2Λ2 + dq<3>*2Λ3 + ... + dq<y>*2Λy, or in table form in Table 4: Table 4
Figure imgf000019_0001
[0074] The relation between the reference channel number (m) and the bit number of the signal dt (y) may be expressed as follows: m = 2Λy - l, or in table form in Table 5: Table 5
Figure imgf000019_0002
[0075] An operation voltage Vps of the memory sensing system may equal:
VpS_min = NMl ds + Vcd + VMCds + Vcd, (7) where NMids is the drain/source voltage of the transistor Ml in the drain driver; Vcd is the column decoder voltage drop; and Vi icds is the drain/source voltage of the memory cell. [0076] As mentioned previously in the background of the invention, the minimum supply voltage VDD_MIN of the prior art is equal to 2.9 V, and the prior art memory device 100 cannot be used in applications that use a VDD supply voltage lower than 2.9 V. However, in the present invention, the minimum supply voltage Vps_min is less than the prior art VDD_MIN (see equation (1) above in the background of the invention) by VDIODE_MAX, and approaches the minimal voltage VBL_MLN. VDIODE_MAX may be approximately equal to one volt, for example. This means that the present invention may be used in applications that use a VDD supply voltage lower than 2.9 V, down to 1.9 V, an improvement of over 34%.
[0077] Thus, the present invention may transform a signal (e.g., current) from the memory cell to a time delay (e.g., a digital signal delay) and compare the time delay to a time delay of a reference cell (e.g., the rise or fall times of the signals). The drain driver operates at a low (close to minimal) voltage to generate the analog signal Vddr. The signal Vddr is preferably linearly dependent upon the memory cell cunent. The memory cell current is preferably integrated on the local capacitor.
[0078] The present invention may be used as a multi-level sensing system for a multiplicity of reference units. In addition, the invention may also be used for a single reference unit.
[0079] It is noted that in the prior art, signals from the memory cells are coupled in a one-to-one correspondence to the sense amplifiers. There is the same number of signals as there are sense amplifiers. However, the reference memory cells are coupled in parallel to all of the sense amplifiers. This results in a significant mismatch between two sense amplifier input signals, because one of them (from the array) is connected to a single sense amplifier whereas the other (from the reference) is connected to all of the sense amplifiers. The mismatch may lead to enors in read data. In contrast, in the present invention, all the analog signals from the anay cells and the reference cells are matched, as described hereinabove.
[0080] Reference is now made to Fig. 9, which illustrates waveforms of the drain driver signals, in accordance with another embodiment of the present invention, different from that of Fig. 5. In this embodiment, node Vps is connected to the system voltage supply Vdd until a time Tps, when power dissipation is maximal for charging the read path parasitic capacitors. At time Tps, the cunent through node Vps is significantly lower
(e.g., practical equal to IMC), and node Vps is switched to a higher voltage supply than
Vdd. This embodiment may be useful to increase the possible range of boosting Vddr.
[0081] Reference is now made to Fig. 10, which illustrates a memory sensing system, in accordance with another embodiment of the present invention, and to Fig. 11 , which illustrates the drain driver for the embodiment of Fig. 10. In this embodiment, the nodes SBL<k:0> may be connected to the comparator inputs instead of the ddr<k:0> signals, as shown in Fig. 10. The drain driver circuit is a simplified version of the drain driver circuit of Fig. 4. Fig. 12 illustrates the waveforms of the drain driver signals, in accordance with this embodiment of the invention. The development of the signals
SBL<k:0> may be as described in US Patent 6,128,226 to Eitan and Dadashev, assigned to the common assignee of the present application.
[0082] It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described hereinabove. Rather the scope of the present invention includes both combinations and subcombinations of the features described hereinabove as well as modifications and variations thereof which would occur to a person of skill in the art upon reading the foregoing description and which are not in the prior art.

Claims

CLAIMSWhat is claimed is:
1. A method for sensing a signal received from an anay cell within a memory array, the method comprising the steps of: generating an analog voltage Vddr proportional to a cunent of a selected anay cell of said memory anay; and comparing said analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal.
2. The method according to claim 1, further comprising providing a reference unit with a reference cell having a similar structure and a similar cunent path therethrough to that of said anay cell, and providing a drain driver for driving drain bit lines of said memory anay and reference drain bit lines of said reference unit, wherein said drain driver generates the analog voltage Vddr.
3. The method according to claim 1, wherein if said analog voltage Vddr is greater than the reference analog voltage Vcomp then a low output digital signal is output, and if said analog voltage Vddr is not greater than the reference analog voltage Vcomp then a high output digital signal is output.
4. The method according to claim 1, further comprising: discharging said memory anay and said reference unit; charging said memory anay and said reference unit so as to generate an array cell signal and a reference signal, respectively, and a timing signal; generating a read signal when said timing signal reaches a predefined voltage level; and generating a sensing signal from the difference of said cell and reference signals once said read signal is generated.
5. A method for sensing a memory cell, the method comprising the steps of: transforming a signal from a memory cell to a time delay; and sensing said memory cell by comparing said time delay to a time delay of a reference cell.
6. The method according to claim 5, wherein said time delay comprises a digital signal delay.
7. The method according to claim 5, wherein comparing said time delay to the time delay of the reference cell comprises comparing at least one of rise and fall times of said time delays.
8. The method according to claim 5, wherein transforming the signal from the memory cell to the time delay comprises generating an analog voltage Vddr proportional to a cunent of said memory cell.
9. The method according to claim 8, wherein comparing said time delay to the time delay of the reference cell comprises comparing said analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal.
10. Apparatus for sensing a signal received from an anay cell within a memory anay, the apparatus comprising: a drain driver adapted to generate an analog voltage Vddr proportional to a cunent of a selected array cell of said memory anay; and a comparator adapted to compare said analog voltage Vddr with a reference analog voltage Vcomp to generate an output digital signal.
11. The apparatus according to claim 10, further comprising a reference unit with a reference cell having a similar structure and a similar cunent path therethrough to that of said anay cell, wherein said drain driver is adapted to drive drain bit lines of said memory anay and reference drain bit lines of said reference unit.
12. The apparatus according to claim 10, wherein said comparator compares said analog voltage Vddr with a reference analog voltage Vcomp and generates said output digital signal in the following manner: if said analog voltage Vddr is greater than the reference analog voltage Vcomp then a low output digital signal is output, and if said analog voltage Vddr is not greater than the reference analog voltage Vcomp then a high output digital signal is output.
13. The apparatus according to claim 10, further comprising a data unit that receives said output digital signal.
14. Apparatus for sensing a memory cell comprising: a driver adapted to transform a signal from a memory cell to a time delay; and a comparator adapted to compare said time delay to a time delay of a reference cell.
15. The apparatus according to claim 14, wherein said time delay comprises a digital signal delay.
16. The apparatus according to claim 14, wherein said comparator compares at least one of rise and fall times of said time delays.
17. The apparatus according to claim 14, wherein said comparator compares said analog voltage Vddr with a reference analog voltage Vcomp and generates said output digital signal in the following manner: if said analog voltage Vddr is greater than the reference analog voltage Vcomp then a low output digital signal is output, and if said analog voltage Vddr is not greater than the reference analog voltage Vcomp then a high output digital signal is output.
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Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7312641B2 (en) * 2004-12-28 2007-12-25 Spansion Llc Sense amplifiers with high voltage swing
CN101095275B (en) * 2004-12-30 2010-06-16 Nxp股份有限公司 Monitoring the temperature dependence of the external capacitors of a charge pump and improved charge pumps based thereon
US7558149B2 (en) * 2006-01-24 2009-07-07 Macronix International Co., Ltd. Method and apparatus to control sensing time for nonvolatile memory
WO2008056294A1 (en) * 2006-11-08 2008-05-15 Nxp B.V. Read enhancement for memory
US7580297B2 (en) * 2007-03-30 2009-08-25 Infineon Technologies Ag Readout of multi-level storage cells
US20090129166A1 (en) * 2007-11-15 2009-05-21 Eduardo Maayan Method, circuit and system for sensing a cell in a non-volatile memory array
US8717802B2 (en) 2010-09-13 2014-05-06 International Business Machines Corporation Reconfigurable multi-level sensing scheme for semiconductor memories
CN103366804B (en) 2012-03-30 2017-10-13 硅存储技术公司 The Nonvolatile memory devices of sense amplifier are injected with electric current
US20140233339A1 (en) * 2013-02-18 2014-08-21 Spansion Llc. Apparatus and method to reduce bit line disturbs
US9911492B2 (en) 2014-01-17 2018-03-06 International Business Machines Corporation Writing multiple levels in a phase change memory using a write reference voltage that incrementally ramps over a write period
US9830999B2 (en) 2014-06-05 2017-11-28 Micron Technology, Inc. Comparison operations in memory
US9898252B2 (en) 2014-09-03 2018-02-20 Micron Technology, Inc. Multiplication operations in memory
US9747961B2 (en) 2014-09-03 2017-08-29 Micron Technology, Inc. Division operations in memory
US9589602B2 (en) 2014-09-03 2017-03-07 Micron Technology, Inc. Comparison operations in memory
US9904515B2 (en) 2014-09-03 2018-02-27 Micron Technology, Inc. Multiplication operations in memory
US10032493B2 (en) 2015-01-07 2018-07-24 Micron Technology, Inc. Longest element length determination in memory
US9460760B2 (en) * 2015-01-23 2016-10-04 Globalfoundries Inc. Data-dependent self-biased differential sense amplifier
US9583163B2 (en) 2015-02-03 2017-02-28 Micron Technology, Inc. Loop structure for operations in memory
US9741399B2 (en) 2015-03-11 2017-08-22 Micron Technology, Inc. Data shift by elements of a vector in memory
US9898253B2 (en) 2015-03-11 2018-02-20 Micron Technology, Inc. Division operations on variable length elements in memory
US10146537B2 (en) 2015-03-13 2018-12-04 Micron Technology, Inc. Vector population count determination in memory
US9892767B2 (en) 2016-02-12 2018-02-13 Micron Technology, Inc. Data gathering in memory
US9697876B1 (en) 2016-03-01 2017-07-04 Micron Technology, Inc. Vertical bit vector shift in memory
US9910637B2 (en) 2016-03-17 2018-03-06 Micron Technology, Inc. Signed division in memory
US10607665B2 (en) 2016-04-07 2020-03-31 Micron Technology, Inc. Span mask generation
US10153008B2 (en) 2016-04-20 2018-12-11 Micron Technology, Inc. Apparatuses and methods for performing corner turn operations using sensing circuitry
US9659605B1 (en) 2016-04-20 2017-05-23 Micron Technology, Inc. Apparatuses and methods for performing corner turn operations using sensing circuitry
US10042608B2 (en) 2016-05-11 2018-08-07 Micron Technology, Inc. Signed division in memory
US11029951B2 (en) 2016-08-15 2021-06-08 Micron Technology, Inc. Smallest or largest value element determination
US10147467B2 (en) 2017-04-17 2018-12-04 Micron Technology, Inc. Element value comparison in memory
US10043570B1 (en) 2017-04-17 2018-08-07 Micron Technology, Inc. Signed element compare in memory
CN112242172A (en) * 2019-07-19 2021-01-19 四川省豆萁科技股份有限公司 NOR flash memory and reference current comparison circuit thereof
US11342010B2 (en) * 2019-10-01 2022-05-24 Macronix International Co., Ltd. Managing bit line voltage generating circuits in memory devices

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6128227A (en) * 1998-03-28 2000-10-03 Hyundai Electronics Industries Co., Ltd. Sense amplifier circuit in a flash memory device
US6163484A (en) * 1998-04-27 2000-12-19 Nec Corporation Non-volatile semiconductor storage device having improved program/erase/over erase verify
US6219290B1 (en) * 1998-10-14 2001-04-17 Macronix International Co., Ltd. Memory cell sense amplifier
US6400607B1 (en) * 1999-10-29 2002-06-04 Stmicroelectronics S.R.L. Reading circuit for a non-volatile memory

Family Cites Families (242)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1392599A (en) 1971-07-28 1975-04-30 Mullard Ltd Semiconductor memory elements
US3881180A (en) 1971-11-30 1975-04-29 Texas Instruments Inc Non-volatile memory cell
US3895360A (en) * 1974-01-29 1975-07-15 Westinghouse Electric Corp Block oriented random access memory
US4016588A (en) * 1974-12-27 1977-04-05 Nippon Electric Company, Ltd. Non-volatile semiconductor memory device
US4017888A (en) * 1975-12-31 1977-04-12 International Business Machines Corporation Non-volatile metal nitride oxide semiconductor device
US4151021A (en) * 1977-01-26 1979-04-24 Texas Instruments Incorporated Method of making a high density floating gate electrically programmable ROM
US4145703A (en) 1977-04-15 1979-03-20 Supertex, Inc. High power MOS device and fabrication method therefor
US4173791A (en) 1977-09-16 1979-11-06 Fairchild Camera And Instrument Corporation Insulated gate field-effect transistor read-only memory array
US4173766A (en) 1977-09-16 1979-11-06 Fairchild Camera And Instrument Corporation Insulated gate field-effect transistor read-only memory cell
US4373248A (en) 1978-07-12 1983-02-15 Texas Instruments Incorporated Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like
DE2832388C2 (en) * 1978-07-24 1986-08-14 Siemens Ag, 1000 Berlin Und 8000 Muenchen Process for the production of MNOS and MOS transistors in silicon gate technology on a semiconductor substrate
US4360900A (en) 1978-11-27 1982-11-23 Texas Instruments Incorporated Non-volatile semiconductor memory elements
US4247861A (en) 1979-03-09 1981-01-27 Rca Corporation High performance electrically alterable read-only memory (EAROM)
DE2923995C2 (en) 1979-06-13 1985-11-07 Siemens AG, 1000 Berlin und 8000 München Process for the production of integrated MOS circuits with MOS transistors and MNOS memory transistors in silicon gate technology
JPS5656677A (en) 1979-10-13 1981-05-18 Toshiba Corp Semiconductor memory device
US4281397A (en) * 1979-10-29 1981-07-28 Texas Instruments Incorporated Virtual ground MOS EPROM or ROM matrix
DE2947350A1 (en) * 1979-11-23 1981-05-27 Siemens AG, 1000 Berlin und 8000 München METHOD FOR PRODUCING MNOS STORAGE TRANSISTORS WITH A VERY SHORT CHANNEL LENGTH IN SILICON GATE TECHNOLOGY
JPS56120166A (en) 1980-02-27 1981-09-21 Hitachi Ltd Semiconductor ic device and manufacture thereof
US4342102A (en) * 1980-06-18 1982-07-27 Signetics Corporation Semiconductor memory array
US4380057A (en) 1980-10-27 1983-04-12 International Business Machines Corporation Electrically alterable double dense memory
US4521796A (en) * 1980-12-11 1985-06-04 General Instrument Corporation Memory implant profile for improved channel shielding in electrically alterable read only memory semiconductor device
EP0056195B1 (en) 1980-12-25 1986-06-18 Fujitsu Limited Nonvolatile semiconductor memory device
US4448400A (en) 1981-07-13 1984-05-15 Eliyahou Harari Highly scalable dynamic RAM cell with self-signal amplification
US4404747A (en) 1981-07-29 1983-09-20 Schur, Inc. Knife and sheath assembly
US4389705A (en) * 1981-08-21 1983-06-21 Mostek Corporation Semiconductor memory circuit with depletion data transfer transistor
US4388705A (en) * 1981-10-01 1983-06-14 Mostek Corporation Semiconductor memory circuit
US4435786A (en) 1981-11-23 1984-03-06 Fairchild Camera And Instrument Corporation Self-refreshing memory cell
US4494016A (en) 1982-07-26 1985-01-15 Sperry Corporation High performance MESFET transistor for VLSI implementation
US4527257A (en) * 1982-08-25 1985-07-02 Westinghouse Electric Corp. Common memory gate non-volatile transistor memory
JPS5949022A (en) * 1982-09-13 1984-03-21 Toshiba Corp Multi-value logical circuit
US4613956A (en) 1983-02-23 1986-09-23 Texas Instruments Incorporated Floating gate memory with improved dielectric
US4769340A (en) 1983-11-28 1988-09-06 Exel Microelectronics, Inc. Method for making electrically programmable memory device by doping the floating gate by implant
US4725984A (en) 1984-02-21 1988-02-16 Seeq Technology, Inc. CMOS eprom sense amplifier
JPS60182174A (en) 1984-02-28 1985-09-17 Nec Corp Non-volatile semiconductor memory
US4663645A (en) 1984-05-23 1987-05-05 Hitachi, Ltd. Semiconductor device of an LDD structure having a floating gate
US5352620A (en) 1984-05-23 1994-10-04 Hitachi, Ltd. Method of making semiconductor device with memory cells and peripheral transistors
US4665426A (en) 1985-02-01 1987-05-12 Advanced Micro Devices, Inc. EPROM with ultraviolet radiation transparent silicon nitride passivation layer
US4761764A (en) 1985-04-18 1988-08-02 Nec Corporation Programmable read only memory operable with reduced programming power consumption
US4667217A (en) * 1985-04-19 1987-05-19 Ncr Corporation Two bit vertically/horizontally integrated memory cell
JPH0831789B2 (en) 1985-09-04 1996-03-27 沖電気工業株式会社 Output circuit
US4742491A (en) * 1985-09-26 1988-05-03 Advanced Micro Devices, Inc. Memory cell having hot-hole injection erase mode
US4760555A (en) 1986-04-21 1988-07-26 Texas Instruments Incorporated Memory array with an array reorganizer
JPH0828431B2 (en) * 1986-04-22 1996-03-21 日本電気株式会社 Semiconductor memory device
US4758869A (en) 1986-08-29 1988-07-19 Waferscale Integration, Inc. Nonvolatile floating gate transistor structure
US5168334A (en) 1987-07-31 1992-12-01 Texas Instruments, Incorporated Non-volatile semiconductor memory
US4780424A (en) 1987-09-28 1988-10-25 Intel Corporation Process for fabricating electrically alterable floating gate memory devices
US4870470A (en) 1987-10-16 1989-09-26 International Business Machines Corporation Non-volatile memory cell having Si rich silicon nitride charge trapping layer
US4839705A (en) 1987-12-16 1989-06-13 Texas Instruments Incorporated X-cell EEPROM array
JPH07120720B2 (en) * 1987-12-17 1995-12-20 三菱電機株式会社 Nonvolatile semiconductor memory device
US5159570A (en) 1987-12-22 1992-10-27 Texas Instruments Incorporated Four memory state EEPROM
US4888735A (en) 1987-12-30 1989-12-19 Elite Semiconductor & Systems Int'l., Inc. ROM cell and array configuration
US4857770A (en) 1988-02-29 1989-08-15 Advanced Micro Devices, Inc. Output buffer arrangement for reducing chip noise without speed penalty
US5268870A (en) * 1988-06-08 1993-12-07 Eliyahou Harari Flash EEPROM system and intelligent programming and erasing methods therefor
US4941028A (en) * 1988-08-10 1990-07-10 Actel Corporation Structure for protecting thin dielectrics during processing
JPH0271493A (en) * 1988-09-06 1990-03-12 Mitsubishi Electric Corp Semiconductor memory device
US5042009A (en) * 1988-12-09 1991-08-20 Waferscale Integration, Inc. Method for programming a floating gate memory device
US5293563A (en) * 1988-12-29 1994-03-08 Sharp Kabushiki Kaisha Multi-level memory cell with increased read-out margin
US5120672A (en) 1989-02-22 1992-06-09 Texas Instruments Incorporated Fabricating a single level merged EEPROM cell having an ONO memory stack substantially spaced from the source region
US5142495A (en) 1989-03-10 1992-08-25 Intel Corporation Variable load for margin mode
DE3931596A1 (en) 1989-03-25 1990-10-04 Eurosil Electronic Gmbh VOLTAGE MULTIPLIER
US5172338B1 (en) 1989-04-13 1997-07-08 Sandisk Corp Multi-state eeprom read and write circuits and techniques
US4961010A (en) 1989-05-19 1990-10-02 National Semiconductor Corporation Output buffer for reducing switching induced noise
US5104819A (en) * 1989-08-07 1992-04-14 Intel Corporation Fabrication of interpoly dielctric for EPROM-related technologies
US5027321A (en) * 1989-11-21 1991-06-25 Intel Corporation Apparatus and method for improved reading/programming of virtual ground EPROM arrays
US4992391A (en) 1989-11-29 1991-02-12 Advanced Micro Devices, Inc. Process for fabricating a control gate for a floating gate FET
US5204835A (en) * 1990-06-13 1993-04-20 Waferscale Integration Inc. Eprom virtual ground array
EP0461904A3 (en) * 1990-06-14 1992-09-09 Creative Integrated Systems, Inc. An improved semiconductor read-only vlsi memory
US5075245A (en) 1990-08-03 1991-12-24 Intel Corporation Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal steps
US5618710A (en) * 1990-08-03 1997-04-08 Vertex Pharmaceuticals, Inc. Crosslinked enzyme crystals
US5289406A (en) * 1990-08-28 1994-02-22 Mitsubishi Denki Kabushiki Kaisha Read only memory for storing multi-data
US5117389A (en) * 1990-09-05 1992-05-26 Macronix International Co., Ltd. Flat-cell read-only-memory integrated circuit
US5892013A (en) * 1990-09-13 1999-04-06 Novo Nordisk A/S Lipase variants
KR920006991A (en) * 1990-09-25 1992-04-28 김광호 High Voltage Generation Circuit of Semiconductor Memory Device
US5081371A (en) 1990-11-07 1992-01-14 U.S. Philips Corp. Integrated charge pump circuit with back bias voltage reduction
JP2987193B2 (en) * 1990-11-20 1999-12-06 富士通株式会社 Semiconductor storage device
US5094968A (en) 1990-11-21 1992-03-10 Atmel Corporation Fabricating a narrow width EEPROM with single diffusion electrode formation
US5086325A (en) 1990-11-21 1992-02-04 Atmel Corporation Narrow width EEPROM with single diffusion electrode formation
JP2612969B2 (en) * 1991-02-08 1997-05-21 シャープ株式会社 Method for manufacturing semiconductor device
US6002614A (en) * 1991-02-08 1999-12-14 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
US5218569A (en) * 1991-02-08 1993-06-08 Banks Gerald J Electrically alterable non-volatile memory with n-bits per memory cell
JPH04311900A (en) 1991-04-10 1992-11-04 Sharp Corp Semiconductor read only memory
JP2930440B2 (en) 1991-04-15 1999-08-03 沖電気工業株式会社 Semiconductor integrated circuit
US5424567A (en) * 1991-05-15 1995-06-13 North American Philips Corporation Protected programmable transistor with reduced parasitic capacitances and method of fabrication
US5142496A (en) * 1991-06-03 1992-08-25 Advanced Micro Devices, Inc. Method for measuring VT 's less than zero without applying negative voltages
DE59209604D1 (en) * 1991-07-01 1999-02-11 Basf Ag USE OF LIPASES FOR THE PRODUCTION OF MEDICINAL PRODUCTS
US5245572A (en) * 1991-07-30 1993-09-14 Intel Corporation Floating gate nonvolatile memory with reading while writing capability
JP2965415B2 (en) * 1991-08-27 1999-10-18 松下電器産業株式会社 Semiconductor storage device
JP3720358B2 (en) * 1991-08-29 2005-11-24 ヒュンダイ エレクトロニクス インダストリーズ カムパニー リミテッド Self-aligned dual bit split gate flash EEPROM cell
US5305262A (en) * 1991-09-11 1994-04-19 Kawasaki Steel Corporation Semiconductor integrated circuit
US5175120A (en) 1991-10-11 1992-12-29 Micron Technology, Inc. Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors
JPH05110114A (en) * 1991-10-17 1993-04-30 Rohm Co Ltd Nonvolatile semiconductor memory device
JP3358663B2 (en) * 1991-10-25 2002-12-24 ローム株式会社 Semiconductor storage device and storage information reading method thereof
US5338954A (en) * 1991-10-31 1994-08-16 Rohm Co., Ltd. Semiconductor memory device having an insulating film and a trap film joined in a channel region
US5357134A (en) 1991-10-31 1994-10-18 Rohm Co., Ltd. Nonvolatile semiconductor device having charge trap film containing silicon crystal grains
JPH05129284A (en) 1991-11-06 1993-05-25 Sony Corp Method of setting condition of plasma sin forming film and manufacture of semiconductor device
US5260593A (en) 1991-12-10 1993-11-09 Micron Technology, Inc. Semiconductor floating gate device having improved channel-floating gate interaction
JP2564067B2 (en) * 1992-01-09 1996-12-18 株式会社東芝 Readout output circuit having sense circuit
US6222762B1 (en) * 1992-01-14 2001-04-24 Sandisk Corporation Multi-state memory
JP2851962B2 (en) 1992-01-21 1999-01-27 シャープ株式会社 Semiconductor read-only memory
DE69231356T2 (en) * 1992-01-22 2000-12-28 Macronix Int Co Ltd Non-volatile memory cell and device architecture
US5324675A (en) * 1992-03-31 1994-06-28 Kawasaki Steel Corporation Method of producing semiconductor devices of a MONOS type
JPH05290584A (en) * 1992-04-08 1993-11-05 Nec Corp Semiconductor memory
US5657332A (en) * 1992-05-20 1997-08-12 Sandisk Corporation Soft errors handling in EEPROM devices
WO1993024959A1 (en) * 1992-05-29 1993-12-09 Citizen Watch Co., Ltd. Semiconductor nonvolatile storage device, semiconductor device, and its manufacture method
JPH065823A (en) 1992-06-19 1994-01-14 Toshiba Corp Nonvolatile semiconductor memory device and its application method
US5289412A (en) * 1992-06-19 1994-02-22 Intel Corporation High-speed bias-stabilized current-mirror referencing circuit for non-volatile memories
US5315541A (en) * 1992-07-24 1994-05-24 Sundisk Corporation Segmented column memory array
GB9217743D0 (en) * 1992-08-19 1992-09-30 Philips Electronics Uk Ltd A semiconductor memory device
JP3036565B2 (en) 1992-08-28 2000-04-24 日本電気株式会社 Manufacturing method of nonvolatile semiconductor memory device
US5450354A (en) * 1992-08-31 1995-09-12 Nippon Steel Corporation Non-volatile semiconductor memory device detachable deterioration of memory cells
US5450341A (en) * 1992-08-31 1995-09-12 Nippon Steel Corporation Non-volatile semiconductor memory device having memory cells, each for at least three different data writable thereinto selectively and a method of using the same
US5412601A (en) * 1992-08-31 1995-05-02 Nippon Steel Corporation Non-volatile semiconductor memory device capable of storing multi-value data in each memory cell
US5412238A (en) * 1992-09-08 1995-05-02 National Semiconductor Corporation Source-coupling, split-gate, virtual ground flash EEPROM array
US5280420A (en) 1992-10-02 1994-01-18 National Semiconductor Corporation Charge pump which operates on a low voltage power supply
US5350568A (en) * 1992-11-09 1994-09-27 Tetra Alfa Holdings, S.A. Method and apparatus for sterilizing cartons and breaking carton score lines
US5377153A (en) * 1992-11-30 1994-12-27 Sgs-Thomson Microelectronics, Inc. Virtual ground read only memory circuit
US5418743A (en) * 1992-12-07 1995-05-23 Nippon Steel Corporation Method of writing into non-volatile semiconductor memory
US5319593A (en) * 1992-12-21 1994-06-07 National Semiconductor Corp. Memory array with field oxide islands eliminated and method
DK154292D0 (en) * 1992-12-23 1992-12-23 Novo Nordisk As NEW ENZYM
JPH07114792A (en) * 1993-10-19 1995-05-02 Mitsubishi Electric Corp Semiconductor memory
US5424978A (en) * 1993-03-15 1995-06-13 Nippon Steel Corporation Non-volatile semiconductor memory cell capable of storing more than two different data and method of using the same
DK39693D0 (en) * 1993-04-02 1993-04-02 Novo Nordisk As ENZYME
US5393701A (en) * 1993-04-08 1995-02-28 United Microelectronics Corporation Layout design to eliminate process antenna effect
US5335198A (en) * 1993-05-06 1994-08-02 Advanced Micro Devices, Inc. Flash EEPROM array with high endurance
US5463586A (en) * 1993-05-28 1995-10-31 Macronix International Co., Ltd. Erase and program verification circuit for non-volatile memory
US5350710A (en) 1993-06-24 1994-09-27 United Microelectronics Corporation Device for preventing antenna effect on circuit
US5400286A (en) * 1993-08-17 1995-03-21 Catalyst Semiconductor Corp. Self-recovering erase scheme to enhance flash memory endurance
US5477499A (en) 1993-10-13 1995-12-19 Advanced Micro Devices, Inc. Memory architecture for a three volt flash EEPROM
US5828601A (en) * 1993-12-01 1998-10-27 Advanced Micro Devices, Inc. Programmed reference
JP3076185B2 (en) * 1993-12-07 2000-08-14 日本電気株式会社 Semiconductor memory device and inspection method thereof
US5435481A (en) * 1994-01-18 1995-07-25 Motorola, Inc. Soldering process
US5440505A (en) * 1994-01-21 1995-08-08 Intel Corporation Method and circuitry for storing discrete amounts of charge in a single memory element
FR2715782B1 (en) * 1994-01-31 1996-03-22 Sgs Thomson Microelectronics Programmable non-volatile bistable flip-flop, with predefined initial state, in particular for memory redundancy circuit.
FR2715758B1 (en) * 1994-01-31 1996-03-22 Sgs Thomson Microelectronics Source-programmable, non-volatile flip-flop, especially for memory redundancy circuits.
US5418176A (en) * 1994-02-17 1995-05-23 United Microelectronics Corporation Process for producing memory devices having narrow buried N+ lines
DE4408152A1 (en) * 1994-03-11 1995-09-14 Studiengesellschaft Kohle Mbh Immobilized lipases in hydrophobic sol-gel materials
EP0678871B1 (en) * 1994-03-22 2000-05-31 STMicroelectronics S.r.l. Memory array cell reading device
DK0755442T3 (en) * 1994-05-04 2003-04-14 Genencor Int Lipases with improved resistance to surfactants
US5568085A (en) * 1994-05-16 1996-10-22 Waferscale Integration Inc. Unit for stabilizing voltage on a capacitive node
US5523972A (en) * 1994-06-02 1996-06-04 Intel Corporation Method and apparatus for verifying the programming of multi-level flash EEPROM memory
US5508968A (en) * 1994-08-12 1996-04-16 International Business Machines Corporation Dynamic random access memory persistent page implemented as processor register sets
US5822256A (en) * 1994-09-06 1998-10-13 Intel Corporation Method and circuitry for usage of partially functional nonvolatile memory
KR100372905B1 (en) * 1994-09-13 2003-05-01 애질런트 테크놀로지스, 인크. A device and method of manufacture for frotection against plasma charging damage in advanced mos technologies
US5583808A (en) 1994-09-16 1996-12-10 National Semiconductor Corporation EPROM array segmented for high performance and method for controlling same
US5523251A (en) * 1994-10-05 1996-06-04 United Microelectronics Corp. Method for fabricating a self aligned mask ROM
US5694356A (en) 1994-11-02 1997-12-02 Invoice Technology, Inc. High resolution analog storage EPROM and flash EPROM
US5537358A (en) * 1994-12-06 1996-07-16 National Semiconductor Corporation Flash memory having adaptive sensing and method
US5661060A (en) * 1994-12-28 1997-08-26 National Semiconductor Corporation Method for forming field oxide regions
CA2142644C (en) * 1995-02-16 1996-11-26 Marc Etienne Bonneville Standby power circuit arrangement
US5518942A (en) * 1995-02-22 1996-05-21 Alliance Semiconductor Corporation Method of making flash EPROM cell having improved erase characteristics by using a tilt angle implant
US6353554B1 (en) * 1995-02-27 2002-03-05 Btg International Inc. Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell
EP0740307B1 (en) 1995-04-28 2001-12-12 STMicroelectronics S.r.l. Sense amplifier circuit for semiconductor memory devices
KR100187656B1 (en) * 1995-05-16 1999-06-01 김주용 Method for manufacturing a flash eeprom and the programming method
ATE287725T1 (en) * 1995-05-31 2005-02-15 Medzyme N V COMPOSITIONS FOR IMPROVING THE DIGESTIBILITY AND UTILIZATION OF NUTRIENTS
US6034896A (en) * 1995-07-03 2000-03-07 The University Of Toronto, Innovations Foundation Method of fabricating a fast programmable flash E2 PROM cell
KR970008496A (en) * 1995-07-04 1997-02-24 모리시다 요이치 MIS semiconductor device, manufacturing method thereof, and diagnostic method thereof
EP0753859B1 (en) * 1995-07-14 2000-01-26 STMicroelectronics S.r.l. Method for setting the threshold voltage of a reference memory cell
JP2830800B2 (en) * 1995-09-29 1998-12-02 日本電気株式会社 Current differential amplifier circuit
US5633603A (en) * 1995-12-26 1997-05-27 Hyundai Electronics Industries Co., Ltd. Data output buffer using pass transistors biased with a reference voltage and a precharged data input
US5748534A (en) * 1996-03-26 1998-05-05 Invox Technology Feedback loop for reading threshold voltage
US5777923A (en) * 1996-06-17 1998-07-07 Aplus Integrated Circuits, Inc. Flash memory read/write controller
US5712815A (en) * 1996-04-22 1998-01-27 Advanced Micro Devices, Inc. Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells
US5847441A (en) 1996-05-10 1998-12-08 Micron Technology, Inc. Semiconductor junction antifuse circuit
US5715193A (en) * 1996-05-23 1998-02-03 Micron Quantum Devices, Inc. Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks
WO2004090908A1 (en) * 1996-06-11 2004-10-21 Nobuyoshi Takeuchi Nonvolatile memory having verifying function
WO1997050089A1 (en) * 1996-06-24 1997-12-31 Advanced Micro Devices, Inc. A method for a multiple bits-per-cell flash eeprom with page mode program and read
KR100265574B1 (en) * 1996-06-29 2000-09-15 김영환 Sense amplifier for semiconductor memory apparatus
US5787484A (en) * 1996-08-08 1998-07-28 Micron Technology, Inc. System and method which compares data preread from memory cells to data to be written to the cells
US5812456A (en) * 1996-10-01 1998-09-22 Microchip Technology Incorporated Switched ground read for EPROM memory array
US5717632A (en) * 1996-11-27 1998-02-10 Advanced Micro Devices, Inc. Apparatus and method for multiple-level storage in non-volatile memories
TW367503B (en) * 1996-11-29 1999-08-21 Sanyo Electric Co Non-volatile semiconductor device
JP3532725B2 (en) 1997-02-27 2004-05-31 株式会社東芝 Semiconductor integrated circuit
JP3920415B2 (en) * 1997-03-31 2007-05-30 三洋電機株式会社 Nonvolatile semiconductor memory device
US6252799B1 (en) * 1997-04-11 2001-06-26 Programmable Silicon Solutions Device with embedded flash and EEPROM memories
US5805500A (en) * 1997-06-18 1998-09-08 Sgs-Thomson Microelectronics S.R.L. Circuit and method for generating a read reference signal for nonvolatile memory cells
JP3189740B2 (en) * 1997-06-20 2001-07-16 日本電気株式会社 Data repair method for nonvolatile semiconductor memory
JP3039458B2 (en) * 1997-07-07 2000-05-08 日本電気株式会社 Non-volatile semiconductor memory
IL125604A (en) * 1997-07-30 2004-03-28 Saifun Semiconductors Ltd Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge
US6768165B1 (en) * 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US5926409A (en) * 1997-09-05 1999-07-20 Information Storage Devices, Inc. Method and apparatus for an adaptive ramp amplitude controller in nonvolatile memory application
US5940332A (en) * 1997-11-13 1999-08-17 Stmicroelectronics, Inc. Programmed memory with improved speed and power consumption
US5867429A (en) * 1997-11-19 1999-02-02 Sandisk Corporation High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates
JP3599541B2 (en) * 1997-11-27 2004-12-08 シャープ株式会社 Nonvolatile semiconductor memory device
US5949728A (en) * 1997-12-12 1999-09-07 Scenix Semiconductor, Inc. High speed, noise immune, single ended sensing scheme for non-volatile memories
KR100327421B1 (en) * 1997-12-31 2002-07-27 주식회사 하이닉스반도체 Program system of non-volatile memory device and programming method thereof
US6046591A (en) * 1998-03-16 2000-04-04 General Electric Company MRI system with fractional decimation of acquired data
US5946258A (en) * 1998-03-16 1999-08-31 Intel Corporation Pump supply self regulation for flash memory cell pair reference circuit
US6030871A (en) * 1998-05-05 2000-02-29 Saifun Semiconductors Ltd. Process for producing two bit ROM cell utilizing angled implant
US6348711B1 (en) * 1998-05-20 2002-02-19 Saifun Semiconductors Ltd. NROM cell with self-aligned programming and erasure areas
US6215148B1 (en) * 1998-05-20 2001-04-10 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
US6042823A (en) * 1998-07-02 2000-03-28 Amano Pharmaceuticals Co., Ltd. Enzyme composition and use thereof
GB9818548D0 (en) * 1998-08-25 1998-10-21 Microbiological Res Authority Treatment of mucas hypersecretion
JP3999900B2 (en) 1998-09-10 2007-10-31 株式会社東芝 Nonvolatile semiconductor memory
EP0987715B1 (en) * 1998-09-15 2005-02-09 STMicroelectronics S.r.l. Method for maintaining the memory of non-volatile memory cells
US6044019A (en) * 1998-10-23 2000-03-28 Sandisk Corporation Non-volatile memory with improved sensing and method therefor
US6147904A (en) 1999-02-04 2000-11-14 Tower Semiconductor Ltd. Redundancy method and structure for 2-bit non-volatile memory cells
US6134156A (en) * 1999-02-04 2000-10-17 Saifun Semiconductors Ltd. Method for initiating a retrieval procedure in virtual ground arrays
US6128226A (en) * 1999-02-04 2000-10-03 Saifun Semiconductors Ltd. Method and apparatus for operating with a close to ground signal
US6108240A (en) * 1999-02-04 2000-08-22 Tower Semiconductor Ltd. Implementation of EEPROM using intermediate gate voltage to avoid disturb conditions
US6233180B1 (en) * 1999-02-04 2001-05-15 Saifun Semiconductors Ltd. Device for determining the validity of word line conditions and for delaying data sensing operation
US6075724A (en) * 1999-02-22 2000-06-13 Vantis Corporation Method for sorting semiconductor devices having a plurality of non-volatile memory cells
US6044022A (en) * 1999-02-26 2000-03-28 Tower Semiconductor Ltd. Programmable configuration for EEPROMS including 2-bit non-volatile memory cell arrays
US6084794A (en) * 1999-05-28 2000-07-04 Winbond Electronics Corp. High speed flat-cell mask ROM structure with select lines
US6108241A (en) * 1999-07-01 2000-08-22 Micron Technology, Inc. Leakage detection in flash memory cell
US6469935B2 (en) * 1999-08-05 2002-10-22 Halo Lsi Design & Device Technology, Inc. Array architecture nonvolatile memory and its operation methods
JP3912937B2 (en) 1999-08-10 2007-05-09 スパンション インク Multi-bit non-volatile memory using non-conductive charge trap gate
JP3348432B2 (en) * 1999-09-14 2002-11-20 日本電気株式会社 Semiconductor device and semiconductor storage device
US6181605B1 (en) * 1999-10-06 2001-01-30 Advanced Micro Devices, Inc. Global erase/program verification apparatus and method
US6331950B1 (en) 1999-10-19 2001-12-18 Fujitsu Limited Write protect input implementation for a simultaneous operation flash memory device
US6175523B1 (en) * 1999-10-25 2001-01-16 Advanced Micro Devices, Inc Precharging mechanism and method for NAND-based flash memory devices
US6272047B1 (en) * 1999-12-17 2001-08-07 Micron Technology, Inc. Flash memory cell
US6201737B1 (en) * 2000-01-28 2001-03-13 Advanced Micro Devices, Inc. Apparatus and method to characterize the threshold distribution in an NROM virtual ground array
US6185143B1 (en) * 2000-02-04 2001-02-06 Hewlett-Packard Company Magnetic random access memory (MRAM) device including differential sense amplifiers
US6266281B1 (en) * 2000-02-16 2001-07-24 Advanced Micro Devices, Inc. Method of erasing non-volatile memory cells
US6215702B1 (en) * 2000-02-16 2001-04-10 Advanced Micro Devices, Inc. Method of maintaining constant erasing speeds for non-volatile memory cells
US6205056B1 (en) * 2000-03-14 2001-03-20 Advanced Micro Devices, Inc. Automated reference cell trimming verify
US6240040B1 (en) * 2000-03-15 2001-05-29 Advanced Micro Devices, Inc. Multiple bank simultaneous operation for a flash memory
US6396741B1 (en) * 2000-05-04 2002-05-28 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
CA2310295C (en) * 2000-05-31 2010-10-05 Mosaid Technologies Incorporated Multiple match detection circuit and method
KR100597060B1 (en) * 2000-08-03 2006-07-06 후지쯔 가부시끼가이샤 Nonvolatile semiconductor memory and method of reading data
JP2002184190A (en) * 2000-12-11 2002-06-28 Toshiba Corp Non-volatile semiconductor memory
US6614692B2 (en) * 2001-01-18 2003-09-02 Saifun Semiconductors Ltd. EEPROM array and method for operation thereof
JP4467815B2 (en) 2001-02-26 2010-05-26 富士通マイクロエレクトロニクス株式会社 Nonvolatile semiconductor memory read operation method and nonvolatile semiconductor memory
US6351415B1 (en) * 2001-03-28 2002-02-26 Tower Semiconductor Ltd. Symmetrical non-volatile memory array architecture without neighbor effect
US6535434B2 (en) * 2001-04-05 2003-03-18 Saifun Semiconductors Ltd. Architecture and scheme for a non-strobed read sequence
JP2002319287A (en) 2001-04-20 2002-10-31 Fujitsu Ltd Nonvolatile semiconductor memory
US6636440B2 (en) 2001-04-25 2003-10-21 Saifun Semiconductors Ltd. Method for operation of an EEPROM array, including refresh thereof
US6522585B2 (en) * 2001-05-25 2003-02-18 Sandisk Corporation Dual-cell soft programming for virtual-ground memory arrays
US6574139B2 (en) * 2001-06-20 2003-06-03 Fujitsu Limited Method and device for reading dual bit memory cells using multiple reference cells with two side read
US6643178B2 (en) 2001-07-31 2003-11-04 Fujitsu Limited System for source side sensing
US6525969B1 (en) * 2001-08-10 2003-02-25 Advanced Micro Devices, Inc. Decoder apparatus and methods for pre-charging bit lines
US6469929B1 (en) * 2001-08-21 2002-10-22 Tower Semiconductor Ltd. Structure and method for high speed sensing of memory arrays
US6510082B1 (en) * 2001-10-23 2003-01-21 Advanced Micro Devices, Inc. Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold
TW506123B (en) 2001-10-24 2002-10-11 Macronix Int Co Ltd Multi-level NROM memory cell and its operating method
US6885585B2 (en) * 2001-12-20 2005-04-26 Saifun Semiconductors Ltd. NROM NOR array
US6529412B1 (en) * 2002-01-16 2003-03-04 Advanced Micro Devices, Inc. Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge
US6975536B2 (en) * 2002-01-31 2005-12-13 Saifun Semiconductors Ltd. Mass storage array and methods for operation thereof
US6639844B1 (en) * 2002-03-13 2003-10-28 Advanced Micro Devices, Inc. Overerase correction method
US6594181B1 (en) * 2002-05-10 2003-07-15 Fujitsu Limited System for reading a double-bit memory cell
US6917544B2 (en) * 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
JP4260434B2 (en) * 2002-07-16 2009-04-30 富士通マイクロエレクトロニクス株式会社 Nonvolatile semiconductor memory and operation method thereof
US6813189B2 (en) * 2002-07-16 2004-11-02 Fujitsu Limited System for using a dynamic reference in a double-bit cell memory

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6128227A (en) * 1998-03-28 2000-10-03 Hyundai Electronics Industries Co., Ltd. Sense amplifier circuit in a flash memory device
US6163484A (en) * 1998-04-27 2000-12-19 Nec Corporation Non-volatile semiconductor storage device having improved program/erase/over erase verify
US6219290B1 (en) * 1998-10-14 2001-04-17 Macronix International Co., Ltd. Memory cell sense amplifier
US6400607B1 (en) * 1999-10-29 2002-06-04 Stmicroelectronics S.R.L. Reading circuit for a non-volatile memory

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