WO2005101929A1

WO2005101929A1 - Printed circuit board including track gap-filled resin and fabricating method thereof

Info

Publication number: WO2005101929A1
Application number: PCT/KR2004/000891
Authority: WO
Inventors: Young-Ha Bae
Original assignee: Youngeun Electronics Co., Ltd
Priority date: 2004-04-19
Filing date: 2004-04-19
Publication date: 2005-10-27
Also published as: TW200536445A; TWI303143B; CN1875669A

Abstract

The present invention relates to a printed circuit board (PCB) including a track gap-filled resin (TGFR). In the inventive PCB, a new resin TGFR (10) having a special composition is filled in a track gap (6), so that delamination is prevented to improve the electrical insulation and dielectric strength between tracks. Also, since the track gap (6) on the dielectric layer (1) is filled with the TGFR (10), a product where the thickness of a dielectric layer (1) is smaller than that of the track can be produced. Furthermore, as the synthetic resin TGFR is used, the PCBs or electrical components mounted thereon show an excellent cooling effect in their operation, and also have excellent reliability against their use environments (heat, humidity and insulation). In addition, as the TGFR (10) is filled in the cavity of the track gap (6), the inventive PCB shows low flexibility, so that inferior rate in a process of mounting and assembling components on the PCB is significantly reduced. Also, the TGFR (10) prevents a portion of the copper foil at the wall of the conductor pad (2) from being exposed to the external environment, so that a short-circuit phenomenon in the mounting and soldering of components on the PCB can be prevented.

Description

PRINTED CIRCUIT BOARD INCLUDING TRACK GAP-FILLED RESIN AND FABRICATING METHOD THEREOF

Technical Field

The present invention relates to a printed circuit board (PCB) , and more particularly, to a PCB including a track gap-filled resin (TGFR) (hereinafter, also referred to as TGFR PCB) , and a fabricating method thereof, in which the TGFR having a special composition is applied in a track gap formed on the PCB, and planarized, so that the electrical insulation and dielectric strength between tracks can be improved and a short-circuit phenomenon in the mounting and soldering of electrical components on the PCB can be prevented.

Background, Art Generally, a PCB is a thin board to which electrical components, such as integrated circuits, resistors and switches, are soldered. In the fabrication of the PCB, a copper foil is attached on a thin board formed of an electrical insulating resin, such as epoxy or bakelite, and then, resist is applied on a portion of the copper foil, which is intended to be used as circuit interconnections. Then, when the board having the resist applied thereon is dipped in an etchant capable of melting copper, a portion of the copper foil, which was not stained with the resist, is etched. Then, when the resist is removed, a desired pattern of the copper foil remains on the board. A portion of the patterned copper foil, in which electrical components are put, is drilled to form holes, and blue solder resist is printed on other portions of the copper foil, which need to be prevented from being stained with solder. FIG. 1 is a schematic cross-sectional view showing the structure of the prior PCB. As shown in FIG. 1, the prior PCB has a dielectric layer 1 formed on the middle portion thereof. On each of the outer surfaces of the dielectric layer 1, a conductor pad 2 and a trace 3 are formed. A track gap 6 is formed between the conductor pad 2 and the trace 3 at a given width. On the conductor pad 2 and the trace 3, a solder mask 4 or a surface finish 5 is formed in a given pattern. The dielectric layer 1 is also called "prepreg", and prepared by a method where a cloth for PCB as a reinforcement made of paper or glass fiber is thermally treated, and then its surface is treated with a silane coupling agent and coated with various resins (or dipped in resins) . The prepreg is laminated with a copper foil and press- formed to make a copper foil-laminated dielectric plate. A plurality of the dielectric plates are stacked on each other, and completely cured by heat and pressure. During this stacking process, the copper foil layer is adhered to the surface of one or two laminates. Then, a portion of the copper foil, which is intended for circuits, is applied with ink or dry film resists, after which a portion of the copper foil, which was not applied with the resists, is etched. The copper foil portion remaining after the etching process is perforated, and plated with metal for connection. Then, various electrical components are soldered in place on the copper foil. In some cases, the electrical components may also be attached using an epoxy adhesive. Thus, in a fabricating process of the PCB according to the prior art, a product where the dielectric layer 1 has a smaller thickness than that of the track cannot be produced. Also, the prior PCB is significantly influenced by its use environments, such as heat, humidity and insulation. For example, when its cooling effect is reduced, delimination in the prior PCB occurs due to an increase in temperature. Moreover, when the prior PCB is mounted with electrical components and operated, the reliability of the product can be reduced due to heat generated from the PCB or the electrical components. In addition, since the prior PCB shows high flexibility due to the track gap 6, many inferior products can be caused during processes of mounting and assembling the electrical components on the PCB. Particularly, in a case of heavy copper PCBs, the copper foil forming the conductor pad 2 is exposed to the external environment upon soldering, such that short-circuit phenomenon can be caused. Also, because of a possibility of incomplete resin impregnation, the dielectric layer 1 must be used at a large thickness.

Disclosure of Invention

Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a printed circuit board (PCB) including a track gap-filled resin (TGFR) , the PCB being fabricated by a method comprising the steps of: etching and surface-cleaning a board; treating the surface and wall of a track with oxide or by soft etching; applying TGFR in a track gap; curing and planarizing the applied TGFR, thereby completing a PCB board where the TGFR is filled in the track gap. Also, the present invention provides a multi-layer heavy copper PCB board, which is fabricated by a method comprising: the steps described in the above object; oxide treatment, lay-up and lamination steps, which are conducted on an internal track; and surface cleaning, PSF application and drying, light exposure, development, PSR curing and silk printing steps, which are conducted on an external track.

Brief Description of Drawings FIG. 1 is a schematic cross-sectional view showing the structure of the prior PCB. FIG. 2 is a schematic cross-sectional view showing the structure of a TGFR PCB according to the present invention. FIG. 3 is a schematic cross-sectional view showing that pluralities of TGFR PCBs according to the present invention are stacked on each other. FIG. 4 is a schematic flow chart showing a process for fabrication a TGFR PCB according to the present invention.

Best Mode for Carrying Out the Invention

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings, in which: FIG. 2 is a schematic cross-sectional view showing the structure of a TGFR PCB according to the present invention; FIG. 3 is a schematic cross-sectional view showing that pluralities of TGFR PCBs according to the present invention are stacked on each other; and FIG. 4 is a schematic flow chart showing a process for fabricating a TGFR PCB according to the present invention. As shown in FIG. 2, a TGFR PCB according to the present invention has a dielectric layer 1 formed in the middle portion thereof. On each of the outer surfaces of the dielectric layer 1, a conductor pad 2 and a trace 3 are formed, and a track gap-filled resin (TGFR) 10 is filled between the conductor pad 2 and the trace 3. On the conductor pad 2 and the trace pad 3, a solder mask 4 or a surface finish 5 is formed in a given pattern. The TGFR 10 is a new synthetic resin having a composition to increase the insulation and dielectric strength between tracks. In one embodiment of the present invention, the TGFR preferably comprises 18-23 wt% of DGEBPA (diglycidyl ether of bisphenol A) , 3-7 wt% of modified cyclo-epoxy, 27-33 wt% of DBDO, 3-7 wt% of antimony trioxide, 30-35 wt% of aluminum hydrate, and 3-7 wt% of dicyandiamide. In another embodiment, the TGFR 10 preferably comprises 5-10 wt% of modified cyclo-epoxy, 40-50 wt% of aluminum hydrate, 20-30 wt% of mineral water, and about 10 wt% of flame retardants, curing agents and pigments. This composition shows excellent heat sink effect. The solder mask 4 is a portion of the PCB, which is formed by applying ink in order to prevent the attachment of solder on undesired portions upon the mounting of components on the PCB and to protect circuits on the PCB surface from the external environment. It is also called "solder resist" or "solder mask". In the present invention, for the convenience of description, the portion applied with ink designates the solder mask 4. The solder mask 4 can be formed by a process which is suitably selected depending on use environments and conditions. Examples of such a process includes: a photo solder resist (PSR) process where ink having a viscosity of 150-300 poise is applied on the entire surface of a substrate having circuits formed thereon, exposed to light and developed; a liquid photo imaging (LPI) process which is conducted in the same manner as the PSR process and uses ink having a viscosity below 100 poise; and infrared (IR) , masking and carbon processes where ink is applied on the desired portions of a substrate surface through a plate making net and printed without light exposure. In one embodiment of the present invention, the solder mask 4 is formed by the PSR process. Furthermore, in the present invention, the solder mask 4 is formed at a somewhat higher position than the surface finish 5 formed on the conductor pad 2, so that the electrical insulation between tracks is improved and the short-circuit phenomenon caused by exposure of the copper foil to the external environment are prevented. Meanwhile, the TGFR PCB may also be formed in a multilayer structure. In one embodiment of the present invention, a multi-layer heavy copper PCB having a three-layer structure is shown in FIG. 3. As shown in FIG. 3, the multi-layer heavy copper PCB according to the present invention has an upper dielectric layer 1 at the upper portion thereof. On the upper surface of the dielectric layer 1, an external track 12 is formed which consists of the conductor pad 2, the trace 3, and the TGFR 10 filled in the track gap between the conductor pad 2 and the trace 3. On the conductor pad 2 and the trace 3, the solder mask 4 or the surface finish 5 is formed in a given pattern. Furthermore, on the lower surface of the dielectric layer 1, an internal track 11 is formed which consists of the conductor pad 2, the trace 3, and the TGFR 10 filled in the track gap between the conductor pad 2 and the trace 3. The internal track 11 is treated with oxide to enhance its adhesion to a middle dielectric layer 1 which is disposed on the lower surface of the internal track 11. Then, the internal track 11 is adhered closely to the middle dielectric layer 1. On the lower surface of the middle dielectric layer 11, an internal track 11 is formed which consists of the conductor pad 2, the trace 3, and the TGFR 10 filled in the track gap between the conductor pad 2 and the trace 3. On the lower surface of this internal track 11, a lower dielectric layer 11 is adhered. On the lower surface of the lower dielectric layer 1, an external track 12 is formed which consists of the conductor pad 2, the trace 3, and the TGFR 10 filled in the track gap between the conductor pad 2 and the trace 3. On the conductor pad 2 and the trace 3, the solder mask 4 or the surface finish 5 is formed in a given pattern. As described above, by disposing the dielectric layer 1 between the internal tracks 11 of the single-layer TGFR PCBs, the multi-layer heavy copper PCB can be easily fabricated. Hereinafter, each step of a method for fabricating the TGFR PCB according to the present invention will be described with reference to a flow chart shown FIG. 4. According to a designed circuit diagram, necessary holes are first formed in a PCB board by a hole drilling step SI. In order to form electrical interconnections on the PCB board, a chemical and electrical copper plating step S2 is then performed on the PCB board. The copper-plated PCB board is subjected to etching steps S3 and step S4 to form a track gap 6 having a given width. The PCB substrate having the track gap 6 formed therein is subjected to a surface cleaning step S5 to remove foreign substances. In the surface cleaning step, soft etching and/or oxide treatment is conducted to treat the surface and inner wall of the track gap. After completion of the surface cleaning step S5, a step Sβ of applying a track gap filled resin 10 on the track gap 10 is conducted. The application of the TGFR 10 is performed by printing or roller coating, and the applied TGFR 10 is rapidly cured by a hot air machine or a heater placed in the outside. As the TGFR 10 is cured, a step S7 of planarizing the TGFR surface is conducted by sanding, brushing, cutting or a combination thereof. Subsequent steps are performed with the difference between the internal track 11 and the external track 12. For the internal track 11, a step Sll of treating the internal track surface with oxide to increase the adhesion of the internal track 11 to a resin forming the dielectric layer 1 is performed. Then, a lay-up step S12 and a lamination step S13 are sequentially conducted. Subsequent steps are the same as those in a general process for fabricating a multi-layer PCB, and thus, the description thereof will be omitted herein. For the external track 12, a surface cleaning step 21 is conducted before applying PSR. In the surface cleaning step 21, soft etching or oxide treatment is performed to treat the surface and wall of the track. On the surface of the PCB board on which the surface cleaning step S21 was performed, a step S22 of applying and drying photo solder resist (PSR), a light exposure step S23, a development step S24, a PSR curing step S25 and a silk printing step S26 are sequentially performed. Such steps and subsequent steps are the same as those in a general process for fabricating a multi-layer PCB, and thus, the description thereof will be omitted herein. Although a preferred embodiment of the present invention has been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Industrial Applicability

As described above, in the TGFR PCB according to the present invention, the new resin TGFR 10 having a special composition is filled in the track gap 6, so that delamination is prevented to improve the electrical insulation and dielectric strength between the tracks. Also, since the track gap 6 on the dielectric layer 1 is filled with the TGFR, a product where the thickness of the dielectric layer 1 is smaller than that of the track can be produced. Furthermore, as the synthetic resin is used, the PCBs or electrical components mounted thereon show an excellent cooling effect in their operation, and also have excellent reliability against their use environments (heat, humidity and insulation) . In addition, as the TGFR 10 is filled in the track gap 6, the inventive PCB shows flexibility, so that inferior rate in a process of mounting and assembling components on the PCB is significantly reduced. Also, the TGFR 10 prevents a portion of the copper foil at the wall of the conductor pad 2 from being exposed to the external environment, so that the short-circuit phenomenon in the mounting and soldering of components on the PCB can be prevented.

Claims

What Is Claimed Is:

1. A printed circuit board (PCB) including a track gap-filled resin (TGFR) , the PCB comprising a dielectric layer 1, a conductor pad 2 and a trace 3 formed on each of both surfaces of the dielectric layer 1, and a track gap 6 formed between the conductor pad 2 and the trace 3 at a given width, wherein the track gap 6 is filled with a track gap-filled resin (TGFR) 10 to increase insulation and dielectric strength, and a solder mask 3, which is formed on the trace 3 and the TGFR 10, is formed at a higher position than a surface finish 5, which is formed on the conductor pad 2.

2. The PCB of Claim 1, wherein the TGFR 10 comprises 18-23 wt% of DGEBPA (diglycidyl ether of bisphenol A) , 3-7 wt% of modified cyclo-epoxy, 27-33 wt% of DBDO, 3-7 wt% of antimony trioxide, 30-35 wt% of aluminum hydrate, and 3-7 wt% of dicyandiamide.

3. The PCB of Claim 1, wherein the TGFR 10 comprises 5-10 wt% of modified cyclo-epoxy, 40-50 wt% of aluminum hydrate, 20-30 wt% of mineral water, and about 10 wt% of flame retardants, curing agents and pigments.

4. A method for fabricating a PCB containing a TGFR, which comprises: a hole drilling step SI of forming necessary holes in a PCB board; a chemical and electrical copper plating step S2 of forming electrical interconnections on the PCB board; etching steps S3 and S4 of forming a track gap 6 in the copper-plated PCB board; a surface cleaning step S5 of removing foreign substances from the PCB board having the track gap 6 formed therein; an applying and curing step Sβ of filling a track gap filled resin (TGFR) 10 in the track gap 6; a TGFR surface planarization step S7 of planarizing the surface of the cured TGFR 10 by sanding, brushing, cutting or a combination thereof; an oxide treatment step Sll to increase the adhesion of an internal track 11 to a resin forming a dielectric layer 1, a lay-up step S12 and a lamination step S13, which are sequentially conducted on the internal track 11; and a surface cleaning step S21, a PSR (photo solder resist) application and drying step S22, a light exposure step S23, a development step S24, a PSR curing step S25 and a silk printing step S26, which are sequentially conducted on an external track 12.

5. The method of Claim 4, wherein the surface treatment steps S5 and S21 are performed by oxide treatment or soft etching. β. The method of Claim 4, wherein, in the TGFR application and curing step Sβ, the application is formed by printing or roller coating, and the applied TGFR 10 is rapidly cured by an external hot air machine or heater.