WO2005114726A2 - Stacked module systems and methods - Google Patents
Stacked module systems and methods Download PDFInfo
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- WO2005114726A2 WO2005114726A2 PCT/US2005/016764 US2005016764W WO2005114726A2 WO 2005114726 A2 WO2005114726 A2 WO 2005114726A2 US 2005016764 W US2005016764 W US 2005016764W WO 2005114726 A2 WO2005114726 A2 WO 2005114726A2
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- WO
- WIPO (PCT)
- Prior art keywords
- csp
- form standard
- circuit module
- lower major
- major surface
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
Definitions
- the present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits in chip-scale packages.
- the predominant package configuration employed during the past decade has encapsulated an integrated circuit (IC) in a plastic surround typically having a rectangular configuration.
- IC integrated circuit
- the enveloped integrated circuit is connected to the application environment through leads emergent from the edge periphery of the plastic encapsulation.
- Such "leaded packages” have been the constituent elements most commonly employed by techniques for stacking packaged integrated circuits.
- CSP chip scale packaging
- CSPs that provides a thermally efficient, reliable structure that performs well at higher frequencies but does not add excessive height to the stack yet allows production at reasonable cost with readily understood and managed materials and methods.
- CSPs CSPs into modules that conserve PWB or other board surface area.
- the present invention is applied most frequently to chip scale packages that contain one die, it may be employed with chip scale packages that include more than one integrated circuit die.
- Multiple numbers of CSPs may be stacked in accordance with the present invention.
- the CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry. That flex circuitry may exhibit one or two or more conductive layers with preferred embodiments having two conductive layers.
- a form standard is disposed along the planar surface of one or more
- the form standard is disposed along the lower planar surface and extends laterally beyond the package of the CSP with which it is associated.
- the form standard can take many configurations and may be used where flex circuits are used to connect CSPs to one another in stacked modules.
- the form standard provides a physical form that allows many of the varying package sizes found in the broad family of CSP packages to be used to advantage while employing a standard connective flex circuitry design.
- the form standard will be devised of heat transference material, a metal such as copper, for example, would be preferred.
- Fig. 1 is an elevation view of a high-density circuit module devised in accordance with a preferred embodiment of the present invention
- Fig. 2 is an elevation view of a four-level module devised in accordance with a preferred embodiment of the present invention.
- FIG. 3 is an enlarged depiction of the area marked "A" in Fig. 2.
- Fig. 4 is a view of a form standard employed in a preferred embodiment of the present invention.
- Fig. 5 is a plan view with partial cutaway from below of a preferred embodiment of the present invention.
- Fig. 6 is a plan view from below of a preferred embodiment of the present invention.
- Fig. 7 is a perspective depiction of a preferred embodiment of the present invention.
- Fig. 8 depicts a unit that may be employed in preferred embodiments of the present invention.
- Fig. 9 depicts a sectional view of a connective area and a layered construction for a preferred flex circuitry employed in a preferred embodiment of the present invention.
- Fig. 10 depicts a sectional view of a connective area and layered construction for an alternative preferred flex circuitry employed in a preferred embodiment of the present invention. Description of Preferred Embodiments:
- Fig. 1 is an elevation view of module 10 devised in accordance with a preferred embodiment of the present invention.
- module 10 includes upper CSP 16 and lower CSP 18.
- Each of the constituent CSPs has an upper surface 20 and a lower surface 22 and opposite lateral edges 24 and 26 and includes at least one integrated circuit typically surrounded by a plastic body 27.
- the body need not be plastic, but a large majority of packages in CSP technologies are plastic.
- the present invention may be devised to create modules with different size CSPs and that the constituent CSPs may be of different types within the same module 10.
- one of the constituent CSPs may be a typical CSP having lateral edges 24 and 26 that have an appreciable height to present a "side" while other constituent CSPs of the same module 10 may be devised in packages that have lateral edges 24 and 26 that are more in the character of an edge rather than a side having appreciable height.
- CSP packages of a variety of types and configurations such as, for example, those that are die-sized, as well those that are near chip-scale as well as the variety of ball grid array packages known in the art. It may also be used with those CSP-like packages that exhibit bare die connectives on one major surface.
- CSP should be broadly considered in the context of this application. Collectively, these will be known herein as chip scale packaged integrated circuits (CSPs) and preferred embodiments will be described in terms of CSPs, but the particular configurations used in the explanatory figures are not, however, to be construed as limiting. For example, the elevation view of Fig.
- CSPs chip scale packaged integrated circuits
- FIG. 1 depicts a CSP of a particular profile known to those in the art, but it should be understood that the figures are exemplary only.
- the invention may be employed to advantage in the wide range of CSP configurations available in the art where an array of connective elements is available from at least one major surface.
- the invention is advantageously employed with CSPs that contain memory circuits, but may be employed to advantage with logic and computing circuits where added capacity without commensurate PWB or other board surface area consumption is desired.
- Typical CSPs such as, for example, ball-grid-array (“BGA”), micro- ball-grid array, and fine-pitch ball grid array (“FBGA”) packages have an array of connective contacts embodied, for example, as leads, bumps, solder balls, or balls that extend from lower surface 22 of a plastic casing in any of several patterns and pitches. An external portion of the connective contacts is often finished with a ball of solder. Shown in Fig. 1 are contacts 28 along lower surfaces 22 of the illustrated constituent CSPs 16 and 18. Contacts 28 provide connection to the integrated circuit or circuits within the respective packages. The depicted contacts 28 have been compressed prior to the complete construction of module 10.
- BGA ball-grid-array
- FBGA fine-pitch ball grid array
- contacts 28 as depicted in Fig. 1 are preferably compressed prior to construction of module 10, contacts 28 of CSPs employed in embodiments of the invention need not be necessarily compressed or reduced in their height above the planar surface above which such contacts typically rise.
- Flex circuits 30 and 32 are shown connecting the constituent CSPs of the module of Fig. 1.
- the entire flex circuit may be flexible or, as those of skill in the art will recognize, a PCB structure made flexible in certain areas to allow conformability around CSPs and rigid in other areas for planarity along CSP surfaces may be employed as an alternative flex circuit in the present invention.
- structures known as rigid-flex may be employed.
- More than one flex circuit may be employed to implement the connections between constituent CSPs in a module 10.
- a form standard 34 is disposed along lower planar surface 22 and laterally beyond edges 26 and 24 of body 27 of CSPs 16 and 18 in stacked module 10.
- Form standard 34 is disposed along a surface of a CSP even if literally separated from that surface by adhesive, for example.
- Form standard 34 may take many configurations, with examples of embodiments having a downward opening form standard shown in pending U.S. Pat. App. No. 10/453,398, filed June 3, 2003, commonly owned by the assignee of the present invention, which is incorporated by reference.
- embodiments that employ downward opening form standards that are disposed across the upper surface of and arc underneath the lower surface of the CSP with which the form standard is associated may exhibit higher profiles.
- Module 10 exhibits module contacts 38 through which module 10 connects to application environments in a preferred embodiment. Those of skill will recognize that module contacts 38 are not required to connect module 10 to an application environment and other connective strategies may be employed such as, for example, direct pad to pad connection schemes.
- Fig. 2 depicts a four-level high embodiment of module 10 that employs four form standards 34 with a form standard 34 associated with each of CSPs 12, 14, 16 and 18. Those of skill will recognize that each level in module 10 need not have a form standard but where maximum heat extraction is desired, use of multiple form standards 34 is preferred.
- Fig. 2 depicts an imaginary plane "P" defined by upper surface 20 of CSP 12. Those of skill will note that in the depicted embodiment of Fig.
- Fig. 3 is an enlarged depiction of the area marked "A" in Fig. 2.
- the connection strategy employed in module 10 as depicted in Fig. 2 and shown in greater detail in Fig. 3, includes a connective element 29 which, in a preferred embodiment, is a low profile contact formed from reflowed solder paste.
- the depiction of Fig. 3 is not to scale and typically, connective element 29 will exhibit less height than contact 28 in a preferred embodiment.
- module 10 When module 10 includes more than two CSPs, use of connective elements 29 to connect the flex circuitry at one level to the flex circuitry at a next level is preferred.
- the upper CSP 16 will not, in a preferred embodiment, have flex circuitry about it and, consequently, will not, in preferred embodiments, employ connective elements 29.
- contacts 28 of upper CSP 16 directly contact the flex circuitry that is associated with lower CSP 18.
- Form standard 34 may be fixed to the lower (or upper) surface of the respective CSP with an adhesive 36 which preferably is thermally conductive.
- Form standard 34 is, in a preferred embodiment, devised from nickel-plated copper to create a mandrel that mitigates thermal accumulation while providing a standard sized form about which flex circuitry is disposed.
- Form standard 34 may take other shapes and forms that are coincident with the respective CSP body. It also need not be thermally enhancing although such attributes are preferable.
- the form standard 34 allows the invention to be employed with CSPs of varying sizes, while articulating a single set of connective structures useable with the varying sizes of CSPs.
- a single set of connective structures such as flex circuits 30 and 32 (or a single flexible circuit in the mode where a single flex is used in place of the flex circuit pair 30 and 32) may be devised and used with the form standard 34 method and/or systems disclosed herein to create stacked modules with CSPs having different- sized packages.
- This will allow the same flex circuitry design to be employed to create iterations of a stacked module 10 from constituent CSPs having a first arbitrary dimension X across attribute Y (where Y may be, for example, package width), as well as modules 10 from constituent CSPs having a second arbitrary dimension X prime across that same attribute Y.
- CSPs of different sizes may be stacked into modules 10 with the same set of connective structures (i.e. flex circuitry). Further, as those of skill will recognize, mixed sizes of CSPs may be implemented into the same module 10.
- portions of flex circuits 30 and 32 may be attached to form standard 34 by attachments 35 which, in a preferred embodiment, are metallic bonds.
- attachments 35 which, in a preferred embodiment, are metallic bonds.
- Preferred examples of such metallic bonding of flex circuitry to a form standard are further described in co-pending U.S. Pat. App. No. 10/828,495, filed April 20, 2004, which is commonly owned by the assignee of the present invention and hereby incorporated by reference.
- Other methods for attaching form standard 34 to flex circuitry may be employed in the present invention including, for example, a tape or liquid adhesive. If an adhesive is used for the attachment 35, the adhesive will be thermally conductive.
- Fig. 4 illustrates an exemplar form standard 34 that may be employed in some preferred embodiments of the present invention.
- Form standard 34 as depicted in the preferred embodiment of Fig. 4 is comprised of nickel-plated cooper and exhibits two windows identified by references A and B to allow the array of contacts 28 that rise above lower surface 22 of the respective CSP to readily pass through form standard 34.
- Form standard 34 may take other configurations and may, for example, be devised in more than one piece.
- Fig. 5 is a plan view of an exemplar module 10 from below depicting an exemplar module 10 in which flex circuit 32 has been deleted to allow a view of the relationship between form standard 34 passing along lower planar surface 22 of CSP 18 and the flex circuitry employed in the module. On the right-hand side of the view of Fig.
- Fig. 6 is a plan view of a preferred embodiment of module 10.
- Fig. 7 is a perspective view of a module 10 devised in accordance with a preferred embodiment of the present invention. Form standard 34 is shown emerging beyond the perimeter of the body 27 of upper CSP 16 and opening upward relative to lower surface 22 of CSP 16.
- form standards in accordance with the present invention need not have an opening "direction" and may exhibit any sort of form about which the flex circuitry associated with that level in module 10 is extended to create the standard-sized template for the flex circuitry.
- flex circuit 32 On the first level of module 10 in Fig. 7, flex circuit 32 is visible while the form standard 34 associated with lower CSP 18 is just visible in the arc of flex circuit 32.
- Fig. 8 depicts unit 39 devised in accordance with a preferred embodiment of the present invention.
- the flex circuitry employed in exemplar unit 39 is a single flex circuit 31 but as depicted in other embodiments, multiple flex circuits may also provide the flex circuitry employed in preferred embodiments of the invention. Multiple iterations of unit 39 may be stacked, preferably with earlier-described connectives 29 realizing the connection between constituent levels, to create a multi-level module 10 or, when combined with an upper CSP 16, a two-level module 10.
- Fig. 8 depicts unit 39 devised in accordance with a preferred embodiment of the present invention.
- the flex circuitry employed in exemplar unit 39 is a single flex circuit 31 but as depicted in other embodiments, multiple flex circuits may also provide the flex circuitry employed in preferred embodiments of the invention. Multiple iterations of unit 39 may be stacked, preferably with earlier-described connectives 29 realizing the connection between constituent levels, to create a multi-level module 10 or, when
- FIG. 9 is a cross-sectional view of a portion of a preferred embodiment taken through a window of form standard 34 depicting a preferred construction for flex circuitry which, in the depicted embodiment, is in particular, flex circuit 30 which comprises two conductive layers 40 and 42 separated by intermediate layer 41.
- the conductive layers are metal such as alloy 110.
- optional outer layer 43 is shown over conductive layer 42 and, as those of skill will recognize, other additional layers may be included in flex circuitry employed in the invention. Flex circuits that employ only a single conductive layer such as for example, those that employ only a layer such as conductive layer 42 may be readily employed in embodiments of the invention.
- flex contact 44 at the level of conductive layer 42 and flex contact 46 at the level of conductive layer 40 provide contact sites to allow connection of module contact 38 and CSP contact 28 through via 48.
- Form standard 34 is seen in the depiction of Fig. 9 as contact 28 is within an opening of form standard 34 which, consequently, is not seen passing in front of contact 28 in the provided cross-sectional view.
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US10/845,029 | 2004-05-13 | ||
US10/845,029 US20050056921A1 (en) | 2003-09-15 | 2004-05-13 | Stacked module systems and methods |
Publications (2)
Publication Number | Publication Date |
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WO2005114726A2 true WO2005114726A2 (en) | 2005-12-01 |
WO2005114726A3 WO2005114726A3 (en) | 2006-04-27 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/US2005/016764 WO2005114726A2 (en) | 2004-05-13 | 2005-05-11 | Stacked module systems and methods |
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US (2) | US20050056921A1 (en) |
WO (1) | WO2005114726A2 (en) |
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KR100650731B1 (en) | 2004-12-28 | 2006-11-27 | 주식회사 하이닉스반도체 | stacked package |
US7888185B2 (en) * | 2006-08-17 | 2011-02-15 | Micron Technology, Inc. | Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device |
US7425758B2 (en) * | 2006-08-28 | 2008-09-16 | Micron Technology, Inc. | Metal core foldover package structures |
JP2012033875A (en) * | 2010-06-30 | 2012-02-16 | Canon Inc | Stacked-type semiconductor device |
KR101796116B1 (en) | 2010-10-20 | 2017-11-10 | 삼성전자 주식회사 | Semiconductor device, memory module and memory system having the same and operating method thereof |
US11201096B2 (en) * | 2019-07-09 | 2021-12-14 | Texas Instruments Incorporated | Packaged device with die wrapped by a substrate |
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Also Published As
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WO2005114726A3 (en) | 2006-04-27 |
US20050098873A1 (en) | 2005-05-12 |
US20050056921A1 (en) | 2005-03-17 |
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