WO2005114746A1

WO2005114746A1 - Novel structures of silicon carbide metal semiconductor field effect transistors for high voltage and high power applications

Info

Publication number: WO2005114746A1
Application number: PCT/SG2005/000152
Authority: WO
Inventors: Rusli; Chunlin Zhu
Original assignee: Nanyang Technological University
Priority date: 2004-05-21
Filing date: 2005-05-18
Publication date: 2005-12-01

Abstract

A silicon carbide metal semiconductor field effect transistor (MESFET) that includes a double-channel layer, with the lower channel being higher doped than the upper channel and a recessed gate. The higher doped lower channel layer is used to increase the channel current while the lower doped upper channel layer is used to improve the gate-drain breakdown voltage. A part of the gate nearer to the source is buried so as to allow a wider channel opening outside the buried gate region, and consequently reduce the source and drain resistances. The unburied gate nearer to the drain functions as a field plate and decreases the electric field crowding at the corner of the buried gate nearer to the drain and hence improves the gate-drain breakdown voltage. Overall a higher operating voltage and higher output power density for the MESFET is attainable.

Description

Novel Structures of Silicon Carbide Metal Semiconductor Field Effect Transistors for High Voltage and High Power Applications

Field of the Invention

This invention relates to metal semiconductor field effect transistors, and in particular to metal semiconductor field effect transistors fabricated by wide band gap semiconductor silicon carbide, which may be used in high operating voltage, high power and high frequency applications.

Background of the Invention

The metal semiconductor field effect transistor (MESFET) using the Schottky contact is preferred for high frequency applications due to the reduced gate capacitance which permits faster switching of the gate input. The MESFET was first proposed by Mead in 1966 and has been widely developed using gallium arsenide (GaAs) for both microwave and high speed applications due to the high electron mobility. Although these transistors provide high operating frequencies, they are not well suited for high power applications due to the relatively lower breakdown electric field strength and the lower thermal conductivity of GaAs.

Williams R. E. and Shaw D. W., in an article entitled Graded Channel FET's: Improved Linearity and Noise Figure published in the IEEE Transactions on Electron Devices, vol. ED-25, No. 6, June 1978, p.600 proposed a double-channel layer structure MESFET device based on GaAs semiconductor, with lower carrier concentration near the surface of the active layer, to improve the linear d.c. transfer characteristics. In addition, the step doping channel devices were observed to exhibit superior noise performance since they maintained high transconductance near pinch off and minimum noise figure is usually obtained when a device is biased near pinch off. Nishiguchi et al. disclosed in the U.S. Patent 5,027,170 that the radiation hardness of GaAs MESFET could be conspicuously improved up to a total exposure dose of about lxlO⁸ roentgens using a double-channel layer structure, as shown in the Fig. 1 of their patent. This is due to the fact that the rates of change of some electrical parameters of GaAs MESFET, such as transconductance, saturated drain current and threshold voltage are related to the channel layer parameters when radiation is applied.

Silicon carbide (SiC) possesses many favorable properties compared to Si and GaAs, making it attractive for use in higher temperature, higher power and higher frequency devices. For example, 4H-SiC has a wide band gap of about 3.26eV, high breakdown field strength of about 3 l0⁶V/cm, high electron saturation drift velocity of about 2.0x10⁷cm/sec and high thermal conductivity of about 4.9 W/cm-K. Due to the above advantages, it has been established that SiC-based devices can withstand higher voltages, respond faster and are smaller in size. Moreover, the cooling requirements for SiC-based devices are also less stringent. These characteristics of SiC-based devices enable weight and size savings as smaller transformers and capacitors are required, and overall reduce the cost of power conversion and distribution systems.

In prior art, MESFET has been fabricated using SiC semiconductor in U.S. Patent No. 5,270,554. Figure 5 shows a cross-sectional view of a conventional MESFET disclosed in Fig. 2 of U.S. Patent 5,270,554. Herein, upon a single crystal bulk SiC substrate 510 of either p type or n type conductivity, a p type SiC buffer layer 520 and an n type SiC channel layer 530 are laid. Regions of n⁺ SiC are formed into mesas 541 and 542 on the channel layer 530. Ohmic contacts 551 and 553 are formed on the mesas 541 and 542, respectively, to create the drain contact 551 and the source contact 553. A Schottky gate contact 552 is directly formed on the channel layer 530 between the drain contact 551 and the source contact 553. While this device may work relatively well under conditions of high temperature, high power and high frequency, its operation is still limited by the poor low field electron mobility of SiC. In the MESFET device geometry, the most important parameter is the gate length (L). Decreasing L will lower the gate-source capacitance Cos, increase the transconductance, and consequently improve the cutoff frequency f . On the other hand, for the gate electrode to have a good control of the current transport across the channel, the gate length must be larger than the channel thickness a, that is L/a > 1. Therefore, to reduce L and yet keep L/a > 1, the channel thickness a has to be lowered. However, a large N x a product is required to provide high output power density, where N is the channel doping. Thus, a higher channel doping is required. Unfortunately, higher doping will lower the breakdown voltage.

Compared to GaAs, one main drawback in using SiC for microwave devices lies in its poor low field electron mobility of 300 - 500 cm²/Vs, at doping levels of interest for conventional MESFETs in the range of lxlO¹⁷ cm^"3 - 5xl0¹⁷ cm^"3. To compensate for this, it is necessary that the channel layer be highly doped to increase the channel current, and the transverse electric field along the channel be large to drive the carriers into velocity saturation, to capitalize on their much higher saturation velocity (2 l0⁷cm/s) compared to GaAs. These, however, will lead to a lower gate-drain breakdown voltage for the device, despite that the breakdown electric field of SiC (3MV/cm) is much larger than that of GaAs.

Thus, there is a need for a MESFET design which overcomes one or more of the aforementioned drawbacks. There is a need for a MESFET design which provides a large transconductance, while still preserving a large breakdown voltage. There is also a need for a new MESFET in which high frequency operation, high channel current and high output power density can all be achieved simultaneously. Summary of the Invention

Metal semiconductor field effect transistors (MESFETs) fabricated using silicon carbide (SiC) with a double-channel layer and recessed gate structure for high operating voltage, high power and high frequency applications are disclosed. In one embodiment, a SiC MESFET designed in accordance with the principles of the invention comprises: a semi-insulating SiC substrate; a buffer layer of p type SiC on the substrate; a channel layer of n type SiC on the buffer layer comprises: a lower channel layer of SiC with higher carrier concentration on the buffer layer; and an upper channel layer of SiC with lower carrier concentration on the lower channel layer; a cap layer of highly doped n type SiC on the upper channel layer; a part of the cap layer where the gate will be formed is etched off by reactive ion etching (RLE) to expose the channel layer; and a first recessed section is formed that extends into the upper channel layer; a second recessed section formed by RLE that extends into the upper channel layer for the buried gate metal formation; a drain and a source contacts formed on the remained cap layer; a gate contact formed over the second recessed region, with the buried part of the gate nearer to the source contact; a dielectric layer of silicon dioxide or silicon nitride formed on the exposed surface of the device.

In another embodiment, a SiC MESFET designed in accordance with the principles of the invention comprises: a semi-insulating SiC substrate; a buffer layer of p type SiC on the substrate; a channel layer of n type SiC on the buffer layer comprises: a lower channel layer of SiC with higher carrier concentration on the buffer layer; and an upper channel layer of SiC with lower carrier concentration on the lower channel layer; a cap layer of highly doped n type SiC on the upper channel layer; a part of the cap layer where the gate will be formed is etched off by RLE to expose the channel layer; and a first recessed section is formed that extends into the upper channel layer; a thermal oxide or any dielectric layer such as silicon dioxide or silicon nitride on the surface; a second recessed section formed by etching the dielectric layer at the region where the gate is to be buried, and then extends into the upper channel layer for the buried gate metal formation using reactive ion etching; a drain and a source contacts formed on the remained cap layer after opening the dielectric layer on the cap layer; a gate contact formed over the second recessed region, with the buried part of the gate nearer to the source contact; a dielectric layer of silicon dioxide or silicon nitride formed on the exposed surface of the device.

In still another embodiment, a SiC MESFET designed in accordance with the principles of the invention comprises: a semi-insulating SiC substrate; a buffer layer of p type SiC on the substrate; a channel layer of n type SiC on the buffer layer comprises: a lower channel layer of SiC with higher carrier concentration on the buffer layer; and an upper channel layer of SiC with lower carrier concentration on the lower channel layer; a recessed section formed by RLE that extends into the upper channel layer for the buried gate metal deposition; a drain and a source contacts formed on the upper channel layer; a gate contact formed over the recessed section between the drain and the source contacts with the buried part of the gate nearer to the source contact; two regions of SiC underneath and adjacent to the source and the drain contacts, being spaced apart from the gate, and with a carrier concentration that is greater than the carrier concentration in the channel layer, formed by ion implantation with molybdenum as the mask; a dielectric layer of silicon dioxide or silicon nitride formed on the exposed surface of the device.

In still another embodiment of a SiC MESFET designed in accordance with the principles of the invention comprises: a semi-insulating SiC substrate; a buffer layer of p type SiC on the substrate; a channel layer of n type SiC on the buffer layer comprises: a lower channel layer of SiC with higher carrier concentration on the buffer layer; and an upper channel layer of SiC with lower carrier concentration on the lower channel layer; a thermal oxide or any dielectric layer such as silicon dioxide or silicon nitride on the surface; a recessed section formed by etching the dielectric layer at the region where the gate is to be buried, and then extends into the upper channel layer for the buried gate metal formation using reactive ion etching; a drain and a source contacts formed on the upper channel layer; a gate contact formed over the recessed section between the drain and the source contacts with the buried part of the gate nearer to the source contact; two regions of SiC underneath and adjacent to the source and the drain contacts, being spaced apart from the gate, and with a carrier concentration that is greater than the carrier concentration in the channel layer, formed by ion implantation with molybdenum as the mask; a dielectric layer of silicon dioxide or silicon nitride formed on the exposed surface of the device.

Other aspects, features, and techniques of the invention will be apparent to one skilled in the relevant art in view of the following detailed description.

Brief Description of the Drawings

Figure 1 shows a cross-sectional view of one embodiment of a metal semiconductor field effect transistor (MESFET) fabricated using silicon carbide (SiC) semiconductor where the unburied part of the gate is directly located on the active layer, in accordance with the principles of the invention;

Figure 2 shows a cross-sectional view of another embodiment of a SiC MESFET where the unburied part of the gate is located on a dielectric layer;

Figure 3 shows a cross-sectional view of still another embodiment of a SiC MESFET where the unburied part of the gate is directly located on the active layer and n⁺ regions are formed by selective doping to form source and drain contacts, in accordance with the principles of the invention;

Figure 4 shows a cross-sectional view of still another embodiment of a SiC MESFET where the unburied part of the gate is located on the dielectric layer and n⁺ regions are formed by selective doping to form source and drain contacts, in accordance with the principles of the invention; and

Figure 5 shows a cross-sectional view of a MESFET with a conventional structure. Detailed Description of Preferred Embodiments

One aspect of the invention is a new structure for SiC MESFETs with a double-channel layer and a recessed gate. A high channel current is possible, attributed to the higher doped lower channel layer. Simultaneously, a high gate-drain breakdown voltage may be achieved due to the lower doped upper channel layer. This layer, however, being lower doped may increase the source and drain resistances. Thus, the recessed gate nearer to the source contact may be buried with a certain depth into the upper channel layer. This may allow the active channel thickness underneath the buried gate to be controlled, while providing a wider opening for the channel outside the buried gate region. In this way, the source and drain resistances may be reduced which can lead to improvements in the dc and rf characteristics of the device.

In one embodiment, the unburied part of the gate nearer to the drain contact functions as a field plate and helps to reduce the electric field crowding at the edge of the buried gate nearer to the drain contact. This may result in SiC MESFETs that can operate at higher operating voltage and higher frequency, and provide higher output power density. The unburied part of the gate nearer to the source may be undesirable as it will increase the parasitic capacitance. While it may not be possible to entirely remove this part of the gate due to process limitations, the undesirable effects are compensated for by the improved performance using a SiC MESFET structure in accordance with the principles of the invention.

As previously mentioned, the invention relates to power metal semiconductor field effect transistors (MESFETs) fabricated using silicon carbide (SiC) semiconductor, a cross- sectional view of which one embodiment is schematically illustrated at 100 as seen in Fig. 1. In this embodiment, the structure 100 includes a double-channel layer 130 and a recessed gate 152 which are provided to increase the channel current and the gate-drain breakdown voltage, and decrease the source and drain resistances so as to provide high operating voltage, high frequency and high output power density. MESFETs according to one or more embodiments of the invention can be easily fabricated using existing fabrication techniques. MESFETs according to one or more of the embodiments of the invention can satisfy the requirements of future wireless communications system and may be used in the areas of power amplifiers, wireless transceivers such as cell phone base stations, radar systems and high definition television transmitters and so on.

Continuing to refer to Fig. 1, the MESFET 100 comprises a semi-insulating monocrystalline SiC substrate 110 which in one embodiment is of the 4H polytype. Other SiC polytypes that can be considered include the polytypes 6H, 15R, 3C, etc. The MESFET 100 is well isolated by the mesas 171 and 172 formed by etching into the substrate 110. The semi-insulating substrate 110 is used to provide good isolation between devices and reduce parasitic capacitances in integrated circuits. Semi-insulating SiC can be obtained by doping with vanadium which creates an energy level that is about midway between the valence and conduction band in SiC. Semi-insulating SiC can also be obtained without vanadium domination as disclosed in the U.S. Patents 6,218,680 and 6,639,247. Suitable semi-insulating SiC substrates are available from Cree Research, USA or Okmetic, Finland. The methods for producing them are provided in the scientific literature as well as in a number of assigned U.S. Patents, including but not limited to 6,218,680, 6,639,247 and 6,507,046.

A lower doped p type buffer layer 120 is grown on the substrate 110 and separates the active channel layer 130 from the substrate. Practical semi-insulating SiC substrates 110 have a high density of defects such as point defects, micropipes, screw and edge dislocations. In order to prevent the parasitic effects of the defects from degrading the device performance, such as leading to drain-source current collapse, hot carrier injection into the substrate, the p type buffer layer 120 may be used. The p type buffer layer 120 can be of 4H, 6H, 15R or 3C SiC polytype, according to the polytype of the SiC substrate 110. The p type buffer layer 120 may have a carrier concentration that can range from about 1.0xl0¹⁵cm^"3 to about 3.0xl0¹⁶cm^"3. Suitable dopants include aluminum, boron and gallium, although other dopants may also be consistent with the principles of the invention. In one embodiment, the p type buffer layer 120 may have a thickness of from about 0.4μm to l.Oμm. An n type channel layer 130 that comprises a lower channel layer 131 with a high carrier concentration and an upper channel layer 132 with a low carrier concentration may be grown on the p type buffer layer 120, according to one embodiment. The high doped lower channel layer 131 on the buffer layer 120 may act as a main channel for carriers drift and allows for high channel current. On the other hand, the low doped upper channel layer 132 may be grown on the lower channel layer 131 to improve the Schottky characteristics with the gate metal, in terms of improving the gate-drain breakdown voltage. The n type active layer 130 can also be formed by SiC of 4H, 6H, 15R or 3C polytype according to the polytype of the SiC substrate 110. While in one embodiment, suitable dopants include nitrogen and phosphorous, it should be appreciated that other dopants may also be consistent with the principles of the invention. The lower channel layer 131 can have a carrier concentration that ranges from about 5χl0¹⁷cm^"3 to about 1.0xl0¹⁸cm^"3 and a thickness that ranges from about 0.05μm to about O.lOμm. The upper channel layer 132 can have a carrier concentration that ranges from 5χl0¹⁶cm^"3 to about 1.0xl0¹⁷cm^"3 and a thickness that ranges from about 0.20μm to about 0.25μm.

A highly doped n type cap layer may be grown on the active layer 130 and a portion of it meant for the gate region may be etched off to expose the active layer 130. The remaining n⁺ cap layer 141 and 142 may be used to decrease the ohmic contact resistance at the drain electrode 151 and the source electrode 153 respectively. The n⁺ type cap layer 141 and 142 can also be formed by SiC of 4H, 6H, 15R or 3C polytype according to the polytype of the SiC substrate 110. The cap layer can have a carrier concentration of about 1.0xl0¹⁹cm^"3 or beyond and a thickness that can range from about O.lOμm to 0.20μm. The active region of MESFET 100 is well isolated by the mesas 171 and 172 formed by reactive ion etching (RIE) into the substrate 110.

The first recessed section between the drain electrode 151 and the source electrode 153 formed by RIE extends a distance of about 0.05μm into the active layer 130. The second recessed section with a length of a half of the gate length (L_g) formed by RIE extends a distance of about 0.05μm into the upper channel layer 132. Therefore the thickness of the upper channel layer 132 under the buried gate region will range between about O.lOμm and about 0.15 μm.

A drain electrode 151 and a source electrode 153 are formed on the n⁺type cap layer 141 and 142 respectively to form ohmic contacts. The ohmic contacts 151 and 153 can be formed by depositing a double-metal layer of nickel and gold and then annealing at a temperature of between about 900°C and about 950°C for a few minutes (for example, 3 minutes) in vacuum or nitrogen ambient using the rapid thermal processing (RTP) technology. The gold is used to reduce the contact resistance with the interconnection. A gate electrode 152 is deposited on the n type channel layer 130 and covers the second recessed section 182 between the drain electrode 151 and the source electrode 153 to form a Schottky contact. The buried gate contact 182 can be formed directly into the active channel layer 130 and the unburied parts 181 and 183 on the active layer 130 by depositing a double-metal layer of nickel and gold or a tri-metal layer of chromium (Cr), platinum (Pt) and gold, and then annealing at a temperature of between about 300°C to about 450°C for a few minutes in a nitrogen ambient. A dielectric layer 160 of silicon dioxide or silicon nitride may then be used to cover the exposed surface of the device.

The gate length is an important parameter for high frequency and high power MESFETs. According to one or more embodiments of the invention, the length of the gate 152 (L_g) can range from about 0.4μm to about 1.2μm. The gate 152 is offset towards the source side 153 to increase the gate-drain breakdown voltage and reduce the source series resistance. The length of the buried part of the gate 182 is about ^lΛ L_g, the length of the unburied part of the gate 183 nearer to the source contact 153 can range from 0 to % L_g and that of the unburied part of the gate 181 nearer to the drain contact 151 can range from Vi to ^lA L_g correspondingly. The distance between the source region 142 and the gate 152, that is, the gate-source spacing (L_gs), can range from about 0.3μm to about 0.8μm; and the distance between the gate 152 and the drain region 141, that is, the gate-drain spacing (L_gJ), can range from about 0.8μm to about 2μm.

π Figure 2 shows the cross-sectional view of another embodiment of a SiC MESFET 200 according to the principles of the invention. In this embodiment, a p type SiC buffer layer 220 is epitaxially grown on the semi-insulating SiC substrate 210. The lower channel layer 231 is grown on the buffer layer 220 and the upper channel layer 232 is laid on the lower channel layer 231 and the n+ cap layer 241 and 242 form the top epi-layer. The substrate 210, buffer layer 220, channel layer 230 and cap layer 241 and 242 in the SiC MESFET 200 shown in Fig. 2 have the same thickness and doping concentrations as those of the substrate 110, buffer layer 120, channel layer 130 and cap layer 141 and 142 in the SiC MESFET 100 shown in Fig. 1, respectively. The MESFET 200 is well isolated by the mesas 271 and 272 formed by etching into the substrate 210. The first recessed section between the drain electrode 251 and the source electrode 253 formed by RIE extends a distance of about 0.05μm into the active layer 230. A thermal oxide or any dielectric layer such as silicon oxide or silicon nitride 260 is formed on the surface with a thickness that ranges from about 0.02μm to about O.lOμm. The second recessed section 282 with a length of Vz L_g may be formed by etching to remove the dielectric layer, and then further etched by RIE that extends a distance of about 0.05μm into the upper channel layer 232. Therefore the thickness of the upper channel layer 232 under the buried gate region will range between about O.lOμm and about 0.15μm. A drain electrode 251 and a source electrode 253 are formed on the n⁺ type cap layer 241 and 242 respectively to form ohmic contacts after opening the dielectric layer on the cap layer. The ohmic contacts 251 and 253 can be formed by depositing a double-metal layer of nickel and gold and then annealing at a temperature of about between about 900°C and about 950°C for a few minutes (for example, 3 minutes) in vacuum or in nitrogen using the rapid thermal processing (RTP) technology. The gold is used to reduce the contact resistance with the interconnection. A gate electrode 252 is deposited on the dielectric layer 260 and covers the second recessed section 282 between the drain electrode 251 and the source electrode 253 to form Schottky contact. The buried gate contact 282 can be formed directly in the active channel layer 230 and the unburied parts 281 and 283 on the dielectric layer 260 by depositing a double-metal layer of nickel and gold or a tri-metal layer of chromium (Cr), platinum (Pt) and gold, and then annealing at a temperature of between about 300°C to about 450°C for a few minutes in a nitrogen ambient. A dielectric layer of silicon dioxide or silicon nitride may be used to cover the exposed surface of the device. The lateral parameters such as the length of the gate 252, the length of the buried part of the gate 282, the length of the unburied parts of the gate 281 and 283, the gate-source spacing between the source region 242 and the gate 252, the gate-drain spacing between the gate 252 and the drain region 241 are the same as those of the SiC MESFET 100 shown in Fig. 1.

Figure 3 shows the cross-sectional view of yet another embodiment of a SiC MESFET 300, in accordance with the principles of the invention. The MESFET 300 is well isolated by the mesas 371 and 372 formed by etching into the substrate 310. In this embodiment, a p type SiC buffer layer 320 is epitaxially grown on the semi-insulating SiC substrate 310. The lower channel layer 331 is grown on the buffer layer 320 and the upper channel layer 332 is laid on the lower channel layer 331. The substrate 310, buffer layer 320 and lower channel layer 331 in the SiC MESFET 300 shown in Fig. 3 have the same thickness and doping concentrations as those of the substrate 110, buffer layer 120 and lower channel layer 131 in the SiC MESFET 100 shown in Fig. 1, respectively. The upper channel layer 332 has a thickness that ranges from about 0.15μm to about 0.20μm, and its doping concentration is the same as that of the upper channel layer 132 in the SiC MESFET 100 shown in Fig.l. The source contact region 342 and the drain contact region 341 are formed by ion implantation of nitrogen or phosphorus at an elevated temperature of between about 600°C and about 800°C, followed by annealing at a temperature of between about 1000°C and about 1700°C for several minutes (e.g., between 5 and 10 minutes) in argon. The source contact region 342 and the drain contact region 341 can have a carrier concentration of about 1.0 l0¹⁹cm^"3 or beyond. The recessed region 382 with a length of Vz L_g formed by RIE extends a distance of about 0.05μm into the upper channel layer 332. A source electrode 353 and a drain electrode 351 may be formed on the source contact region 342 and the drain contact region 341 respectively. The ohmic contacts 351 and 353 can be formed by depositing a double-metal layer of nickel and gold and then annealing at a temperature of between about 900°C and about 950°C for a few minutes in vacuum or nitrogen ambient. The gold is used to reduce the contact resistance with the interconnection. A gate electrode 352 is deposited on the n type channel layer 332 between the source electrode 353 and the drain electrode 351 to form Schottky contact. The buried gate contact 382 can be formed directly into the active channel layer 332 and the unburied parts 381 and 383 on the active channel layer 332 by depositing a double-metal layer of nickel and gold or a tri-metal layer of chromium (Cr), platinum (Pt) and gold and then annealing at a temperature of about between 300°C and 450°C for a few minutes in a nitrogen ambient. A dielectric layer 360 of silicon dioxide or silicon nitride is used to cover the exposed surface of the device. The lateral parameters such as the length of the gate 352, the length of the buried part of the gate 382, the lengths of the unburied part of the gate 381 and 383, the gate-source spacing between the source region 342 and the gate 352, the gate-drain spacing between the gate 352 and the drain region 341 are the same as those of the SiC MESFET 100 shown in Fig. 1.

Figure 4 shows the cross-sectional view of still another embodiment of a SiC MESFET 400 designed in accordance with the principles of the invention. The MESFET 400 is well isolated by the mesas 471 and 472 formed by etching into the substrate 410. A p type SiC buffer layer 420 is epitaxially grown on the semi-insulating SiC substrate 410. The lower channel layer 431 is grown on the buffer layer 420 and the upper channel layer 432 is laid on the lower channel layer 431. The substrate 410, buffer layer 420, lower channel layer 431 and upper channel layer 432 in the SiC MESFET 400 shown in Fig. 4 have the same thickness and doping concentrations as those of the substrate 310, buffer layer 320, lower channel layer 331 and upper channel layer 332 in the SiC MESFET 300 shown in Fig. 3, respectively. The source contact region 442 and the drain contact region 441 are formed by ion implantation of nitrogen or phosphorus at an elevated temperature of between about 600°C and about 800°C, followed by annealing at a temperature of between about 1000°C and about 1700°C for several minutes (e.g., between 5 and 10 minutes) in argon. The source contact region 442 and the drain contact region 441 can have a carrier concentration of about 1.0χl0¹⁹cm^"3 or beyond. A thermal oxide or any dielectric layer such as silicon dioxide or silicon nitride 460 is formed on the surface with a thickness that ranges from about 0.02μm to about O.lOμm. The recessed section 482 with a length of Vz L_g may be formed by etching to remove the dielectric layer, and then further etched by RIE that extends a distance of about 0.05 μm into the upper channel layer 432. A source electrode 453 and a drain electrode 451 are formed on the source contact region 442 and the drain contact region 441 respectively after opening the dielectric layer on the top. The ohmic contacts 451 and 453 can be formed by depositing a double-metal layer of nickel and gold and then annealing at a temperature of between about 900°C and about 950°C for a few minutes in vacuum or nitrogen ambient. The gold is used to reduce the contact resistance with the interconnection. A gate electrode 452 is deposited on the dielectric layer 460 between the source electrode 453 and the drain electrode 451 to form Schottky contact. The buried gate contact 482 can be formed directly in the active channel layer 432 and the unburied parts 481 and 483 on the dielectric layer 460 by depositing a double-metal layer of nickel and gold or a tri-metal layer of chromium (Cr), platinum (Pt) and gold and then annealing at a temperature of between about 300°C and about 450°C for a few minutes in a nitrogen ambient. A dielectric layer of silicon dioxide or silicon nitride is used to cover the exposed surface of the device. The lateral parameters such as the length of the gate 452, the length of the buried part of the gate 482, the lengths of the unburied part of the gate 481 and 483, the gate-source spacing between the source region 442 and the gate 452, the gate-drain spacing between the gate 452 and the drain region 441 are the same as those of the SiC MESFET 200 shown in Fig. 2.

Figure 5 shows a cross-sectional view of a conventional SiC MESFET 500 which has been mentioned in the background of the invention.

While the invention has been described in connection with various embodiments, it will be understood that the invention is capable of further modifications. This application is intended to cover any variations, uses or adaptation of the invention following, in general, the principles of the invention, and including such departures from the present disclosure as come within the known and customary practice within the art to which the invention pertains.

Claims

ClaimsWhat is claimed is:

1. A metal semiconductor field effect transistor (MESFET) comprising: a semi-insulating SiC substrate; a buffer layer of p type SiC on the substrate; a channel layer of n type SiC on the buffer layer, wherein said channel layer includes, a lower channel layer of SiC with higher carrier concentration on the buffer layer, and an upper channel layer of SiC with lower carrier concentration on the lower channel layer; a cap layer of highly doped n type SiC on the upper channel layer; a first recessed section that extends into the upper channel layer that is formed by etching off a portion of the cap layer; a second recessed section within said first recessed section that is formed by further etching into said upper channel layer; a drain and a source contacts formed on unetched portions of the cap layer; a gate contact formed over the second recessed region having a buried part that is closer to the source contact than to the drain contact, and wherein said buried part is buried within said second recessed section; and a dielectric layer formed on an exposed surface of the MESFET.

2. The MESFET of claim 1, wherein the buffer layer has a carrier concentration that ranges from about 1.0xl0¹⁵cm^"3 to about 3.0xl0¹⁶cm^"3 and a thickness ranging from about 0.4μm to about l.Oμm.

3. The MESFET of claim 1, wherein the dielectric layer is one of silicon dioxide and silicon nitride.

4. The MESFET of claim 1, wherein the lower channel layer has a carrier concentration that ranges from about 5χl0¹⁷cm^"3 to about 1.0xl0¹⁸cm^"3 and a thickness that ranges from about 0.05 μm to about O.lOμm.

5. The MESFET of claim 1 , wherein the upper channel layer has a carrier concentration that ranges from about 5xl0¹⁶cm^"3 to about 1.0xl0¹⁷cm^"3 and a thickness that ranges from about 0.20μm to about 0.25 μm.

6. The MESFET of claim 1 , wherein the cap layer has a carrier concentration of at least lxl0¹⁹cm^"3 and a thickness that ranges from about O.lOμm to about 0.20μm.

7. The MESFET of claim 1, wherein the first recessed section is formed through the cap layer and extends into the upper channel layer with a depth of about 0.05μm.

8. The MESFET of claim 7, wherein the second recessed section extends into the upper channel layer about 0.05μm more than said first recessed section.

9. The MESFET of claim 1 , wherein the buried part of said gate contact has a buried length equal to about one-half a total length of said gate contact (L_g), and wherein said buried part is buried into the upper channel layer with a depth of about 0.05μm.

10. The MESFET of claim 9, wherein said gate contact further includes an unburied part, and wherein said unburied part is formed within said first recessed section and directly on the upper channel layer.

11. The MESFET of claim 10, wherein the unburied part of the gate closer to the source contact has a length of from 0 to % L_g and the unburied part of the gate closer to the drain has a length of from Vz L_g to ^lA L_g.

12. A metal semiconductor field effect transistor (MESFET) comprising: a semi-insulating SiC substrate; a buffer layer of p type SiC on the substrate; a channel layer of n type SiC on the buffer layer, wherein the channel layer includes, a lower channel layer of SiC with higher carrier concentration on the buffer layer, and an upper channel layer of SiC with lower carrier concentration on the lower channel layer; a cap layer of highly doped n type SiC on the upper channel layer a first recessed section that extends into the upper channel layer and which is formed by etching off a portion of the cap layer; a first dielectric layer is formed on a surface of the MESFET; a second recessed section within said first recessed section that is formed by etching a portion of the first dielectric layer, and by further etching into said upper channel layer; a drain and a source contacts formed on unetched portions of the cap layer; a gate contact formed over the second recessed region having a buried part that is closer to the source contact than to the drain contact, and wherein said buried part is buried within said second recessed section; and a second dielectric layer formed on an exposed surface of the MESFET.

13. The MESFET of claim 12, wherein the buffer layer has a carrier concentration that rraannggeess ffrroomm aabboouutt 11..00xχll00^II55ccrm^"3 to about 3.0xl0¹⁶cm^"3 and a thickness ranging from about 0.4μm to about l.Oμm.

14. The MESFET of claim 12, wherein the second dielectric layer is made from one of silicon dioxide and silicon nitride.

15. The MESFET of claim 12, wherein the lower channel layer has a carrier concentration that ranges from about 5xl0¹⁷cm^"3 to about 1.0xl0¹⁸cm^"3 and a thickness that ranges from about 0.05μm to about O.lOμm.

16. The MESFET of claim 12, wherein the upper channel layer has a carrier concentration that ranges from about 5xl0¹⁶cm^"3 to about 1.0xl0¹⁷cm^"3 and a thickness that ranges from about 0.20μm to about 0.25μm.

17. The MESFET of claim 12, wherein the cap layer has a carrier concentration of at least lxl0¹⁹cm^"3 and a thickness that ranges from about O.lOμm to about 0.20μm.

18. The MESFET of claim 12, wherein a first recessed section is formed through the cap layer and extends into the upper channel layer with a depth of about 0.05μm.

19. The MESFET of claim 12, wherein the first dielectric layer is made from one of a thermal oxide, silicon dioxide and silicon nitride, and wherein the first dielectric layer has a thickness of from about 0.02μm to about O.lOμm.

20. The MESFET of claim 12, wherein a second recessed section is formed through the first dielectric layer and then extends into the upper channel layer about 0.05μm more than said first recessed section.

21. The MESFET of claim 12, wherein the buried part of the gate contact has a buried length of one half a total length of said gate contact (L_g), and wherein said buried part is buried into the upper channel layer with a depth of about 0.05μm.

22. The MESFET of claim 21, wherein said gate contact further includes an unburied part, and wherein said unburied part is formed within said first recessed section and directly on the first dielectric layer.

23. The MESFET of claim 22, wherein the unburied part of the gate closer to the source contact has a length of from 0 to ^lA L_g and the unburied part of the gate closer to the drain has a length of from ^lA L_g to Α L_g.

24. A metal semiconductor field effect transistor (MESFET) comprising: a semi-insulating SiC substrate; a buffer layer of p type SiC on the substrate; a channel layer of n type SiC on the buffer layer, wherein the channel layer includes, a lower channel layer of SiC with higher carrier concentration on the buffer layer, and an upper channel layer of SiC with lower carrier concentration on the lower channel layer; a recessed section formed by etching that extends into the upper channel layer; a source contact and a drain contact formed on the upper channel layer; a gate contact formed over the recessed section and on the upper channel layer between the source contact and the drain contact; two regions of SiC underneath and adjacent to the source and the drain contacts, respectively, wherein said two regions of SiC are spaced apart from the gate contact and have a carrier concentration that is greater than a carrier concentration in the channel layer; and a dielectric layer formed on an exposed surface of the device.

25. The MESFET of claim 24, wherein the buffer layer has a carrier concentration that ranges from about 1.0xl0¹⁵cm^"3 to about 3.0xl0¹⁶cm^"3 and a thickness that ranges from about 0.4μm to about l.Oμm.

26. The MESFET of claim 24, wherein the dielectric layer is made from one of a silicon dioxide and a silicon nitride.

27. The MESFET of claim 24, wherein the lower channel layer has a canier concentration that ranges from about 5xl0¹⁷cm^"3 to about 1.0xl0¹⁸cm^"3 and a thickness that ranges from about 0.05μm to about O.lOμm.

28. The MESFET of claim 24, wherein the upper channel layer has a carrier concentration that ranges from about 5xl0¹⁶cm^"3 to about 1.0xl0¹⁷cm^"3 and a thickness that ranges from about 0.20μm to about 0.25μm.

29. The MESFET of claim 24, wherein the two regions of SiC are formed by ion implantation and have a carrier concentration of at least about 1.0xl0¹⁹cm^"3.

30. The MESFET of claim 24, wherein the recessed section extends into the upper channel layer with a depth of about 0.05μm.

31. The MESFET of claim 24, wherein a buried part of the gate contact has a buried length of one-half a total length of said gate contact (L_g), and wherein said buried part is buried into the upper channel layer with a depth of about 0.05μm.

32. The MESFET of claim 31, wherein the gate contact further includes an unburied part that is formed directly on the upper channel layer.

33. The MESFET of claim 31, wherein the unburied part of the gate closer to the source has a length of from 0 to ^lA L_g and the unburied part of the gate closer to the drain has a length of from Vz L_g to Α L_g.

34. A metal semiconductor field effect transistor (MESFET) comprises: a semi-insulating SiC substrate; a buffer layer of p type SiC on the substrate; a channel layer of n type SiC on the buffer layer, wherein the channel layer includes, a lower channel layer of SiC with higher carrier concentration on the buffer layer, and an upper channel layer of SiC with lower carrier concentration on the lower channel layer; a first dielectric layer formed on a surface of the MESFET; a recessed section formed by etching through the first dielectric layer and extending into the upper channel layer; a source contact and a drain contact formed on the upper channel layer; a gate contact formed over the recessed section and on the upper channel layer between the source contact and the drain contact; two regions of SiC underneath and adjacent to the source and the drain contacts, respectively, said two regions of SiC being spaced apart from the gate contact and having a carrier concentration that is greater than a carrier concentration in the channel layer; a second dielectric layer formed on an exposed surface of the MESFET.

35. The MESFET of claim 34, wherein the buffer layer has a carrier concentration that ranges from about 1.0xl0¹⁵cm^"3 to about 3.0xl0¹⁶cm^"3 and a thickness that ranges from about 0.4μm to about l.Oμm.

36. The MESFET of claim 34, wherein the second dielectric layer is made from one of silicon dioxide and silicon nitride.

37. The MESFET of claim 34, wherein the lower channel layer has a carrier concentration that ranges from about 5xl0¹⁷cm^"3 to about 1.0xl0¹⁸cm^"3 and a thickness that ranges from about 0.05μm to about O.lOμm.

38. The MESFET of claim 34, wherein the upper channel layer has a carrier concentration that ranges from about 5xl0¹⁶cm^"3 to about 1.0χl0¹⁷cm^"3 a thickness that ranges from about 0.20μm to about 0.25μm.

39. The MESFET of claim 34, wherein the two regions of SiC are formed by ion implantation and have a carrier concentration of at least about 1.0χl0¹⁹cm^"3.

40. The MESFET of claim 34, wherein the first dielectric layer is made from one of a thermal oxide, silicon dioxide and silicon nitride, and wherein the first dielectric layer has a thickness of from about 0.02μm to about O.lOμm.

41. The MESFET of claim 34, wherein the recessed section is formed through the dielectric layer and then extends into the upper channel layer with a depth of about 0.05μm.

42. The MESFET of claim 34, wherein said contact gate has a buried part having a buried length that is one-half a total length of the gate contact (L_g), and wherein said buried part is buried into the upper channel layer with a depth of about 0.05 μm.

43. The MESFET of claim 42, wherein said gate contact further includes an unburied part that is formed directly on the first dielectric layer.

44. The MESFET of claim 43, wherein the unburied part of the gate closer to the source has a length of from 0 to ^lA L_g and the unburied part of the gate closer to the drain has a length of from Vz L_g to ^lA L_g.