WO2006005062A3 - Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices - Google Patents

Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices Download PDF

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Publication number
WO2006005062A3
WO2006005062A3 PCT/US2005/023755 US2005023755W WO2006005062A3 WO 2006005062 A3 WO2006005062 A3 WO 2006005062A3 US 2005023755 W US2005023755 W US 2005023755W WO 2006005062 A3 WO2006005062 A3 WO 2006005062A3
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WO
WIPO (PCT)
Prior art keywords
light emitting
emitting devices
chip
substrate
scale
Prior art date
Application number
PCT/US2005/023755
Other languages
French (fr)
Other versions
WO2006005062A2 (en
Inventor
James Ibbetson
Bernd Keller
Primit Parikh
Original Assignee
Cree Inc
James Ibbetson
Bernd Keller
Primit Parikh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cree Inc, James Ibbetson, Bernd Keller, Primit Parikh filed Critical Cree Inc
Priority to AT05769290T priority Critical patent/ATE524839T1/en
Priority to JP2007520428A priority patent/JP4996463B2/en
Priority to KR1020077002238A priority patent/KR101193740B1/en
Priority to EP05769290A priority patent/EP1774598B1/en
Publication of WO2006005062A2 publication Critical patent/WO2006005062A2/en
Publication of WO2006005062A3 publication Critical patent/WO2006005062A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

A packaged light emitting device includes a carrier substrate (20) having a top surface and a bottom surface, first and second conductive vias (22S, B) extending from the top surface of the substrate (20) to the bottom surface of the substrate, and a bond pad (24) on the top surface of the substrate in electrical contact with the first conductive via (22A). A diode (16) having first and second electrodes is mounted on the bond pad with the first electrode (26) is in electrical contact with the bond pad (24). A passivation layer (32) is formed on the diode (16), exposing the second electrode of the diode (16). A conductive trace (33) is formed on the top surface of the carrier substrate in electrical contact with the second conductive via (22B) and the second electrode. The conductive trace is on and extends across the passivation layer to contact the second electrode. Methods of packaging light emitting devices include providing an epiwafer including a growth substrate and an epitaxial structure on the growth substrate, bonding a carrier substrate to the epitaxial structure of the epiwafer, forming a plurality of conductive vias through the carrier substrate, defining a plurality of isolated diodes in the epitaxial structure, and electrically connecting at least one conductive via to respective ones of the plurality of isolated diodes.
PCT/US2005/023755 2004-06-30 2005-06-30 Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices WO2006005062A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AT05769290T ATE524839T1 (en) 2004-06-30 2005-06-30 METHOD FOR ENCAPSULATING A LIGHT-EMITTING COMPONENT AND ENCAPSULATED LIGHT-EMITTING COMPONENTS ON A CHIP SCALE
JP2007520428A JP4996463B2 (en) 2004-06-30 2005-06-30 Chip scale method for packaging light emitting device and light emitting device packaged on chip scale
KR1020077002238A KR101193740B1 (en) 2004-06-30 2005-06-30 Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices
EP05769290A EP1774598B1 (en) 2004-06-30 2005-06-30 Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58418704P 2004-06-30 2004-06-30
US60/584,187 2004-06-30

Publications (2)

Publication Number Publication Date
WO2006005062A2 WO2006005062A2 (en) 2006-01-12
WO2006005062A3 true WO2006005062A3 (en) 2006-07-13

Family

ID=35783407

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/023755 WO2006005062A2 (en) 2004-06-30 2005-06-30 Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices

Country Status (7)

Country Link
US (1) US7329905B2 (en)
EP (1) EP1774598B1 (en)
JP (1) JP4996463B2 (en)
KR (1) KR101193740B1 (en)
CN (1) CN101032034A (en)
AT (1) ATE524839T1 (en)
WO (1) WO2006005062A2 (en)

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CN101032034A (en) 2007-09-05
EP1774598A2 (en) 2007-04-18
WO2006005062A2 (en) 2006-01-12
JP4996463B2 (en) 2012-08-08
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US20060006404A1 (en) 2006-01-12
EP1774598B1 (en) 2011-09-14

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