WO2006011897A1 - Packaged microelectronic imagers and methods of packaging microelectronic imagers - Google Patents
Packaged microelectronic imagers and methods of packaging microelectronic imagers Download PDFInfo
- Publication number
- WO2006011897A1 WO2006011897A1 PCT/US2004/037415 US2004037415W WO2006011897A1 WO 2006011897 A1 WO2006011897 A1 WO 2006011897A1 US 2004037415 W US2004037415 W US 2004037415W WO 2006011897 A1 WO2006011897 A1 WO 2006011897A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- pad
- bond
- passage
- die
- Prior art date
Links
- 238000004377 microelectronic Methods 0.000 title claims abstract description 99
- 238000000034 method Methods 0.000 title claims abstract description 78
- 238000004806 packaging method and process Methods 0.000 title abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 113
- 238000003384 imaging method Methods 0.000 claims abstract description 91
- 239000000463 material Substances 0.000 claims abstract description 29
- 229910052802 copper Inorganic materials 0.000 claims description 15
- 239000000080 wetting agent Substances 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 11
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 238000004140 cleaning Methods 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 230000008878 coupling Effects 0.000 claims description 6
- 238000010168 coupling process Methods 0.000 claims description 6
- 238000005859 coupling reaction Methods 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 3
- 238000003698 laser cutting Methods 0.000 claims 2
- 229910052681 coesite Inorganic materials 0.000 claims 1
- 229910052906 cristobalite Inorganic materials 0.000 claims 1
- 239000000377 silicon dioxide Substances 0.000 claims 1
- 229910052682 stishovite Inorganic materials 0.000 claims 1
- 229910052905 tridymite Inorganic materials 0.000 claims 1
- 230000008569 process Effects 0.000 description 22
- 235000012431 wafers Nutrition 0.000 description 16
- 238000012360 testing method Methods 0.000 description 12
- 238000005530 etching Methods 0.000 description 9
- 230000008901 benefit Effects 0.000 description 7
- 239000002893 slag Substances 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 239000000523 sample Substances 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- DNIAPMSPPWPWGF-UHFFFAOYSA-N Propylene glycol Chemical compound CC(O)CO DNIAPMSPPWPWGF-UHFFFAOYSA-N 0.000 description 3
- 239000006227 byproduct Substances 0.000 description 3
- 239000012459 cleaning agent Substances 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 229920001690 polydopamine Polymers 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910020169 SiOa Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 238000001429 visible spectrum Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/02016—Circuit arrangements of general character for the devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01066—Dysprosium [Dy]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01077—Iridium [Ir]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Definitions
- Microelectronic imagers are used in digital cameras, wireless devices with picture capabilities, and many other applications.
- Cell phones and Personal Digital Assistants are used in digital cameras, wireless devices with picture capabilities, and many other applications.
- PDAs for example, are incorporating microelectronic imagers for capturing and sending pictures.
- the growth rate of microelectronic imagers has been steadily increasing as they become smaller and produce better images with higher pixel counts.
- Microelectronic imagers include image sensors that use Charged Coupled Device (CCD) systems, Complementary Metal-Oxide Semiconductor (CMOS) systems, or other systems.
- CCD image sensors have been widely used in digital cameras and other applications.
- CMOS image sensors are also quickly becoming very popular because they are expected to have low production costs, high yields, and small sizes.
- CMOS image sensors can provide these advantages because they are manufactured using technology and equipment developed for fabricating semiconductor devices.
- CMOS image sensors, as well as CCD image sensors are accordingly "packaged" to protect the delicate components and to provide external electrical contacts.
- Figure 1 is a schematic view of a conventional microelectronic imager 1 with a conventional package.
- the imager 1 includes a die 10, an interposer substrate 20 attached to the die 10, and a housing 30 attached to the interposer substrate 20.
- the housing 30 surrounds the periphery of the die 10 and has an opening 32.
- the imager 1 also includes a transparent cover 40 over the die 10.
- the ball- pads 24 are arranged in an array for surface mounting the imager 1 to a board or module of another device.
- the bond-pads 14 on the die 10 are electrically coupled to the bond-pads 22 on the interposer substrate 20 by wire-bonds 28 to provide electrical 5 pathways between the bond-pads 14 and the ball-pads 24.
- the imager 1 shown in Figure 1 also has an optics unit including a support 50 attached to the housing 30 and a barrel 60 adjustably attached to the support 50.
- the support 50 can include internal threads 52, and the barrel 60 can include external threads 62 engaged with the threads 52.
- the optics unit also includes a lens 70 carried
- the footprint of the imager in Figure 1 is the surface area of the bottom of the interposer substrate 20. This is typically much larger than the surface area of the /5 die 10 and can be a limiting factor in the design and marketability of picture cell phones or PDAs because these devices are continually shrinking to be more portable. Therefore, there is a need to provide microelectronic imagers with smaller footprints and lower profiles.
- Another problem with packaging conventional microelectronic imagers is the 0 manufacturing costs for packaging the dies.
- Forming the wire bonds 28, for example, in the imager 1 shown in Figure 1 can be complex and/or expensive because it requires individual wires between each set of bond-pads and ball-pads.
- Figure 1 is a cross-sectional view of a packaged microelectronic imager in accordance with the prior art.
- Figure 2 is a side cross-sectional view schematically illustrating a microelectronic 0 imaging die in accordance with an embodiment of the invention.
- Figures 3A-3J are schematic side cross-sectional views illustrating various stages in a method of forming an electrically conductive interconnect through a microelectronic
- Figures 4A-4F are schematic side cross-sectional views illustrating various stages in a method of forming an electrically conductive interconnect through a microelectronic imaging die for providing a backside array of ball-pads in accordance with another embodiment of the invention.
- Figures 5A and 5B are schematic side cross-sectional views illustrating various stages in a method of forming an electrically conductive interconnect through a microelectronic imaging die for providing a backside array of ball-pads in accordance with another embodiment of the invention.
- Figure 6 is a schematic side cross-sectional view of an assembly including a microelectronic imager workpiece having a plurality of imaging dies and an optics workpiece having a plurality of optics units in accordance with an embodiment of the invention.
- microelectronic imagers methods for packaging microelectronic imagers, and methods for forming electrically conductive interconnects in microelectronic imagers.
- One particular embodiment of the invention is directed toward a microelectronic imaging die comprising a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit.
- the imaging die further includes an electrical terminal (e.g., bond-pad) electrically coupled to the integrated circuit and an electrically conductive through-wafer interconnect extending through at least a portion of the substrate.
- One end of the interconnect contacts the bond-pad, and the other end of the interconnect can contact a ball-pad on the backside of the die.
- Another particular embodiment of the invention is directed toward a method for manufacturing a microelectronic imaging die.
- the method can include providing a microelectronic substrate having an integrated circuit and an image sensor electrically coupled to the integrated circuit, forming a bond-pad on the substrate, and electrically coupling the bond-pad to the integrated circuit.
- the method can further include forming a passage through the die and the bond-pad, and constructing an electrically conductive through-wafer interconnect in at least a portion of the passage so that the interconnect
- the interconnect can be constructed Dy depositing an electrically conductive fill material into at least a portion of the passage.
- One embodiment of a method for constructing the interconnect includes cleaning the passage through the die and applying a dielectric liner to at least a portion of the passage before depositing the electrically conductive fill material into the passage.
- the dielectric liner electrically insulates the other components in the substrate from the electrically conductive material filling the passage.
- This method can further include depositing a conductive layer into at least a portion of the passage, and depositing a wetting agent over at least a portion of the conductive layer.
- the electrically conductive fill material can then be deposited into the passage.
- microfeature workpiece includes substrates upon which and/or in which microelectronic devices, micromechanical devices, data storage elements, read/write components, and other features are fabricated.
- microfeature workpieces can include semiconductor wafers (e.g., silicon or gallium arsenide wafers), glass substrates, insulated substrates, and many other types of substrates.
- semiconductor wafers e.g., silicon or gallium arsenide wafers
- glass substrates e.g., glass substrates, insulated substrates, and many other types of substrates.
- the feature sizes in microfeature workpieces can be 0.11 ⁇ m or less, but the workpieces can have larger submicron and supra-micron features.
- FIG. 2 is a side cross-sectional view of a microelectronic imaging die 200 for use in a microelectronic imager in accordance with one embodiment of the invention.
- the microelectronic imaging die 200 includes a substrate 210 having a first side 241 , a second side 242 opposite the first side 241 , integrated circuitry (IC) 230 within the substrate 210, and an image sensor 212 electrically coupled to the IC 230.
- the image sensor 212 can be a CMOS device or a CCD for capturing pictures or other images in the visible spectrum. In other embodiments, the image sensor 212 can detect radiation in other spectrums (e.g., IR or UV ranges).
- the imaging die 200 further includes a plurality of external contacts 220 for carrying electrical signals.
- Each external contact 220 for example, can include a bond- pad 222, a ball-pad 224, and an electrically conductive through-wafer interconnect 226 electrically coupling the bond-pad 222 to the ball-pad 224.
- the external contacts 220 shown in Figure 2 accordingly provide an array of ball-pads 224 within the footprint of the imaging die 200.
- the ball-pads 224 can be connected to other external devices such that the imaging die 200 does not need an interposing substrate to be installed on a circuit board.
- the imaging die 200 which has a significantly smaller footprint and profile than the interposer substrate of the conventional device shown in Figure 1 , can define the final footprint of the packaged imager. Accordingly, the imaging die 200 can be used in smaller electronic devices. Furthermore, the imaging die 200 also eliminates having to wire-bond the bond-pads to external contacts. This is useful because wire-bonds tend to break and are difficult to fabricate on high-density arrays. Accordingly, the microelectronic imaging die 200 with the through-wafer interconnects 226 is more robust than dies that require wire-bonds.
- Figures 3A-5B illustrate various embodiments of methods for forming electrically conductive through-wafer interconnects in the imaging die 200. Although the following description illustrates forming one interconnect, it will be appreciated that a plurality of interconnects are constructed simultaneously through a plurality of imaging dies on a wafer.
- Figures 3A-3J schematically illustrate various stages in a method of forming the through-wafer interconnect 226 in the imaging die 200 in accordance with an embodiment of the invention.
- Figure 3A is a schematic side cross- sectional view of the area 3A shown on Figure 2.
- a first dielectric 5 layer 350 is applied to the first side 241 of the substrate 210, and a second dielectric layer 351 is applied over the first dielectric layer 350.
- a portion of the second dielectric layer 351 over the bond-pad 222 is removed by etching or another known process to expose the bond-pad 222.
- a first hole 360 is formed through the bond-pad 222.
- the first hole 360 can be formed by etching the center of
- a third dielectric layer 352 is applied over the imaging die 200 to cover the bond-pad 222 and fill the first hole 360.
- the first, second, and third dielectric layers 350, 351 , 352 are a polyimide material, but these
- the first dielectric layer 350 and/or one or more subsequent dielectric layers can be a low temperature chemical vapor deposition (low temperature CVD) material, such as tetraethylorthosilicate (TEOS), parylene, silicon nitride (Si 3 N 4 ), silicon oxide (SiOa), and/or other suitable materials.
- low temperature CVD low temperature chemical vapor deposition
- TEOS tetraethylorthosilicate
- parylene silicon nitride
- Si 3 N 4 silicon oxide
- SiOa silicon oxide
- the foregoing list of dielectric materials is not 0 exhaustive.
- the dielectric layers 350, 351 , 352 are not generally composed of the same materials as each other, but it is possible that two or more of these layers are composed of the same material.
- one or more of the layers described above with reference to Figures 3A and 3B, or described below with reference to subsequent figures, may be omitted.
- 5 Figures 3C-3J are schematic side cross-section
- Figure 3C further illustrates cutting a passage or through-hole 361 through the substrate 210.
- the through-hole 361 extends through the substrate 210 to the first hole
- the through-hole 361 and the first hole 360 together form passage 374 extending through the imaging die 200 in the embodiment shown in Figure 2.
- the through-hole 361 can be formed using a laser 363 (shown schematically) to cut through the die 200 from the second side 242 toward the first side 241.
- the laser 363 can conceivably cut from the first side 241 toward the second side 242.
- the laser 363 can be aligned with respect to the bond-pad 222 using scanning/alignment systems known in the art.
- the through-hole 361 can be formed by suitable etching processes if the wafer is not too thick. After forming the through-hole 361 , it is cleaned to remove ablated byproducts
- the through-hole 361 can be cleaned using a wet-etch process.
- the cross-sectional dimension of the through-hole 361 is less than the cross-sectional dimension of the first hole 360 in the bond-pad 222 so that the laser 363 does not impinge against the bond-pad 222. This avoids producing slag of one material in the first hole 360 through the bond-pad 222 and slag of a different material in the through-hole 361 through the substrate 210.
- This feature allows a single cleaning process/chemistry to clean the slag from the through-hole 361 without having to use a second cleaning process to clean residue from the first hole 360.
- cleaning agents that do not attack the metal of the bond-pad 222 can be used to clean slag from the through-hole 361.
- One such cleaning agent may include 6% tetramethylammonium hydroxide (TMAH): propylene glycol for removing laser ablated byproducts.
- TMAH tetramethylammonium hydroxide
- the through-hole 361 is not cleaned after formation. Referring to Figure 3D, a fourth dielectric layer 353 is applied to the imaging die
- the fourth dielectric layer 353 can be applied using CVD, PVD, ALD or other deposition processes. In the illustrated embodiment the fourth dielectric layer 353 is applied to the entire imaging die 200 so that it covers the exposed portions of the substrate 210, the bond-pad 222, and the third dielectric layer 352.
- the fourth dielectric layer 353 can be a low temperature CVD oxide, but in other embodiments the fourth dielectric layer 353 can be other suitable dielectric materials.
- the fourth dielectric layer 353 electrically insulates the components of the substrate 210 from an interconnect that is subsequently formed in the passage 374 as described in greater detail below.
- a first conductive layer 354 is deposited onto the imaging die 200.
- the first conductive layer 354 covers the fourth dielectric layer 353.
- the first conductive layer 354 is generally a metal layer, such as a TiN layer, but in other embodiments the first conductive layer 354 can be composed of TaN 1 W, WN, Ta, Ti, Al, Cu, Ag, Au, Ni, Co and/or other suitable materials known to those of skill in the art.
- the first conductive layer 354 When the first conductive layer 354 is composed of TiN, it can be formed using TiCUTiN and an atomic layer deposition (ALD) or chemical vapor deposition (CVD) process. As explained below, the first conductive layer 354 provides a material for plating another layer of metal onto only selected areas of the wafer (e.g., in the through-hole 361 ).
- ALD atomic layer deposition
- CVD chemical vapor deposition
- portions of the first conductive layer 354 are removed from the horizontal and diagonal surfaces of the imaging die 200.
- such portions of the first conductive layer 354 are removed from these surfaces by a suitable etching process, such as a "dry etch” or “spacer etch” that preferentially removes material at a higher etch rate from horizontal surfaces and surfaces having horizontal components relative to the direction of the etchant.
- a suitable etching process such as a "dry etch” or "spacer etch” that preferentially removes material at a higher etch rate from horizontal surfaces and surfaces having horizontal components relative to the direction of the etchant.
- different processes can be used to selectively remove non-vertical portions of the first conductive layer 354 so that the vertical portions of the first conductive layer 354 on the sidewalls in the holes 360 and 361 remain on the workpiece.
- portions of the third dielectric layer 352 and fourth dielectric layer 353 on horizontal and diagonal surfaces of the first side 241 of the imaging die 200 are removed.
- the portion of the fourth dielectric layer 353 on the second side 242 of the substrate 210 remains on the imaging die 200 in this embodiment.
- the third dielectric layer 352 and fourth dielectric layer 353 can be removed from the horizontal and diagonal surfaces of the imaging die 200 by a suitable etching process, such as a dry etch or spacer etch as described above.
- a second conductive layer 355 is applied to the remaining portions of the first conductive layer 354 in the holes 360 and 361.
- the second conductive layer 355 can act as a wetting agent to facilitate depositing metals into the passage 374.
- the second conductive layer 355 can be Ni that is deposited onto a first conductive layer 354 composed of TiN in an electroless plating operation. When the TiN is activated by an HFPd wet dip, it provides nucleation for the Ni during the plating process.
- the plating process may also be performed using an activationless Ni
- the passage 374 can be coated with Cu, Au, or other suitable materials using other methods, or one or more of the first and second conductive layers 354, 355 may be omitted.
- a conductive fill material 358 is deposited into the passage 374 to form an interconnect 377 extending through the imaging die 200.
- the fill material 358 can be solder, copper, or other electrically conductive materials.
- Various processes can be used to deposit the fill material 358 into the passage 374.
- the fill material 358 can be /0 deposited into the passage 374 using a solder wave process.
- the fill material 358 can be deposited by electroplating, stenciling, placing a pre-formed sphere of metal fill in the passage 374 and melting the sphere, or injecting a flowable material into the passage 374.
- the fill material 358 can be solder, copper, or other electrically conductive materials.
- the cap 359 electrically couples the interconnect 377 with the bond-pad 222.
- the cap 359 can be Ni electroplated onto the interconnect 377.
- the cap 359 can be a wetting agent and/or other material.
- the cap 359 can be a portion of the fill material itself, or the cap 359 can be omitted.
- a solder ball 370 is attached to the interconnect 377 at the second side 242 of the substrate 210 to provide an external connection to other electronic devices on the backside of the imaging die 200.
- the passage 374 extends through the entire imaging die 200.
- One advantage of this feature is that it makes the passage 374 easier to clean and fill than would otherwise be the case if the passage were "blind" (i.e., a passage that extends only 0 partially through the workpiece).
- a blind passage is difficult to fill with metallic materials using known physical vapor deposition (PVD), ALD, or plating processes.
- PVD physical vapor deposition
- ALD atomic layer deposition
- FIG. 4A-4F illustrate stages in a method of forming a through-wafer interconnect in an imaging die 200 in accordance with another embodiment of the invention.
- the initial stage of this method is at least generally similar to the steps described above with reference to Figure 3A, and thus Figure 4A shows the workpiece configuration illustrated in Figure 3A.
- the subsequent stages of this method differ from those described above with reference to Figures 3B-3F in that a third dielectric layer is not applied over the second dielectric layer 451 before cutting a through-hole 461 through the substrate 210.
- the through-hole 461 is formed through the substrate 210 without having a third dielectric layer over the second dielectric layer 451.
- the passage formed by the through-hole 461 and a first hole 460 through the bond-pad 222 is referred to as a via or passage 474 extending through the imaging die 200.
- the through-hole 461 can be formed using a laser 463 (shown schematically), etching, or other suitable processes as described above.
- Figure 4B illustrates additional stages of this method that are generally similar to the steps described above with reference to Figure 3D.
- a third dielectric layer 453 is deposited onto the imaging die 200 to cover the sidewall of the through-hole 461 within the substrate 210.
- the third dielectric layer 453 generally covers the bond- pad 222 and the second dielectric layer 451 in addition to the exposed portion of the substrate 210 in the through-hole 461.
- a first conductive layer 454 is deposited onto the imaging die 200.
- the first conductive layer 454 covers the entire third dielectric layer 453.
- the first conductive layer 454 can be a TiN layer, but the first conductive layer 454 can be a different material.
- a portion of the first conductive layer 454 is removed from the horizontal and diagonal surfaces of the imaging die 200.
- the first conductive layer 454 can be removed from these surfaces by a spacer etch or other process described above with respect to Figure 3E.
- the portions of the third dielectric layer 453 on the upper horizontal and diagonal surfaces of the imaging die 200 are then removed to leave portions of the third dielectric layer 453 in the passageway 474 and on the second side 242 of the substrate 210.
- a second conductive layer 455 is then deposited onto the first conductive layer 454.
- the second conductive layer 455 can be a wetting agent to
- the second conductive layer 455 can be generally similar to the second conductive layer 355 described above with respect to Figure 3H.
- a fill material 458 is deposited into the passageway 474 to construct a through-wafer interconnect 477 in a procedure generally similar to that described above with reference to Figures 3I-3J.
- Figures 5A and 5B illustrate stages in a method of forming an interconnect in an imaging die 200 in accordance with another embodiment of the invention.
- the first part of this method can be at least generally similar to the steps described above with reference to Figure 3A.
- a hole is not etched in the bond-pad 222.
- a through-hole 561 can be formed through the substrate 210 and the bond-pad 222.
- the through-hole 561 can be formed using a laser 563 (shown schematically), etching, or other suitable processes.
- a first type of slag can coat the portion of the sidewall in the substrate 210 and a second type of slag can coat the portion of the 0 sidewall in the bond-pad 222. As such, it may take two separate cleaning steps to clean the through-hole 561.
- the cleaning agents used to clean the through-hole 561 may be limited to those chemistries that do not attack or otherwise degrade the metal of the bond-pad 222 or the material of the substrate 210.
- the imaging die 200 can undergo additional packaging 5 steps that are at least generally similar to those described above with reference to Figures 3C-3J to construct a through-wafer interconnect as illustrated in Figure 3J.
- inventions described above with reference to Figures 3A-5B include three methods for forming and/or filling through-holes in microfeature workpieces that extend through bond-pads and/or associated substrates.
- other methods 0 can be used to form and/or fill such through-holes.
- the present invention is not limited to the particular methods for forming and/or filling the through-holes described above, but it also includes alternative methods for providing an electrically conductive material in a through-hole to form an array of ball-pads on the backside of the imager die.
- Figure 6 is a schematic cross-sectional view of an assembly 600 including a plurality of microelectronic imagers 690 that each include an imaging die 200 and an optics unit 640.
- the assembly 600 includes a microelectronic imager workpiece 602 having a first substrate 604 and a plurality of imaging dies 200 formed on the first substrate 604.
- the individual imaging dies 200 can be generally similar to the imaging die 200 described above with respect to Figure 2; like reference numbers accordingly refer to like components in Figures 2 and 6.
- the assembly 600 also includes an optics workpiece 630 that includes a second substrate 634 and a plurality of optics units 640 on the second substrate 634.
- Individual optic units 640 can include an optic member 650 on the second substrate 634.
- the optic member 650 can include lenses and/or filters for focusing and filtering the radiation passing through the optics unit 640.
- the assembly 600 further includes a plurality of stand-offs 660 configured to position individual optic units 640 with respect to individual image sensors 212.
- Suitable stand-offs are disclosed in U.S. Patent Application No. 10/723,363 (Perkins Coie Docket No. 108298746US00), entitled “Packaged Microelectronic Imagers and Methods of Packaging Microelectronic Imagers,” filed on November 26, 2003, which is incorporated by reference herein.
- the microelectronic imagers 690 can be assembled by seating the stand-offs 660 so that the optics units 640 are accurately aligned with the image sensors 212.
- the through-wafer interconnects 226 enable a plurality of microelectronic imagers to be fabricated at the wafer level using semiconductor fabrication techniques. Because the through-wafer interconnects 226 provide an array of ball-pads 224 on the backside of the imaging dies 200, it is not necessary to wire-bond the bond-pads 222 on the front side of the wafer to external devices. The bond-pads 222 can accordingly be covered at the wafer level.
- Another advantage of the assembly 600 of microelectronic imagers 690 is the ability to decrease the real estate that the imagers 690 occupy in a cell phone, PDA, or 5 other type of device. Because the imagers 690 do not require an interposer substrate to provide external electrical contacts in light of the through-wafer interconnects 226, the footprint of the imagers 690 can be the same as that of the die 200 instead of the interposer substrate. The area occupied by the imagers 690 is accordingly less than conventional imagers because the footprint of the individual imaging dies 200 is
- the dies 200 provide a backside array of ball-pads 224 that can be coupled directly to a module without an interposer substrate, the profile is lower and the time and costs associated with mounting the die to the interposer substrate are eliminated. This results in greater throughput, lower packaging costs, and smaller imagers.
- a further advantage of wafer-level imager packaging is that the microelectronic imagers 690 can be tested from the backside of the dies 200 at the wafer level before the individual imagers 690 are singulated.
- a test probe can contact the backside of the dies 200 to test the individual microelectronic imagers 690 because the through-wafer interconnects 226 provide backside electrical contacts. Accordingly, because the test 0 probe engages contacts on the backside of the imager workpiece 602, it will not damage the image sensors 212, the optics units 640, or associated circuitry on the front of the microelectronic imagers 690.
- the test probe does not obstruct the image sensors 212 during a backside test, which allows the test probe to test a larger number of dies at one time compared to processes that test imaging dies from the front 5 side.
- it is more efficient in terms of cost and time to test the microelectronic imagers 690 at the wafer level (i.e., before singulation) than to test each imager 690 from the front side of the dies 200.
- microelectronic imagers 690 can be singulated after assembling the optics units 640 to the dies 200.
- the attached optics units 640 protect the imager sensors 212 on the front side of the dies 200 from particles generated during the singulation process.
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007519188A JP4759677B2 (en) | 2004-06-29 | 2004-11-09 | Packaged microelectronic imager and method for packaging a microelectronic imager |
EP04822213A EP1763897B1 (en) | 2004-06-29 | 2004-11-09 | Packaged microelectronic imagers and methods of packaging microelectronic imagers |
KR1020077002140A KR100909773B1 (en) | 2004-06-29 | 2004-11-09 | How to package a packaged microelectronic imager and a microelectronic imager |
AT04822213T ATE441941T1 (en) | 2004-06-29 | 2004-11-09 | PACKAGED MICROELECTRONIC IMAGE SENSORS AND PACKAGING METHOD THEREOF |
CNA2004800435031A CN1977382A (en) | 2004-06-29 | 2004-11-09 | Packaged microelectronic imagers and methods of packaging microelectronic imagers |
DE602004023002T DE602004023002D1 (en) | 2004-06-29 | 2004-11-09 | ACKING PROCEDURE THEREOF |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/879,398 US7294897B2 (en) | 2004-06-29 | 2004-06-29 | Packaged microelectronic imagers and methods of packaging microelectronic imagers |
US10/879,398 | 2004-06-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2006011897A1 true WO2006011897A1 (en) | 2006-02-02 |
Family
ID=34959511
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2004/037415 WO2006011897A1 (en) | 2004-06-29 | 2004-11-09 | Packaged microelectronic imagers and methods of packaging microelectronic imagers |
Country Status (10)
Country | Link |
---|---|
US (3) | US7294897B2 (en) |
EP (2) | EP2093800B1 (en) |
JP (1) | JP4759677B2 (en) |
KR (1) | KR100909773B1 (en) |
CN (1) | CN1977382A (en) |
AT (2) | ATE515799T1 (en) |
DE (1) | DE602004023002D1 (en) |
SG (1) | SG153876A1 (en) |
TW (1) | TWI305388B (en) |
WO (1) | WO2006011897A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2269944A1 (en) | 2009-06-30 | 2011-01-05 | The Procter & Gamble Company | Liquid dosing apparatus |
Families Citing this family (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7091124B2 (en) | 2003-11-13 | 2006-08-15 | Micron Technology, Inc. | Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices |
US8084866B2 (en) | 2003-12-10 | 2011-12-27 | Micron Technology, Inc. | Microelectronic devices and methods for filling vias in microelectronic devices |
US7148525B2 (en) * | 2004-01-12 | 2006-12-12 | Micron Technology, Inc. | Using high-k dielectrics in isolation structures method, pixel and imager device |
US6943106B1 (en) * | 2004-02-20 | 2005-09-13 | Micron Technology, Inc. | Methods of fabricating interconnects for semiconductor components including plating solder-wetting material and solder filling |
US20050247894A1 (en) | 2004-05-05 | 2005-11-10 | Watkins Charles M | Systems and methods for forming apertures in microfeature workpieces |
US7199439B2 (en) * | 2004-06-14 | 2007-04-03 | Micron Technology, Inc. | Microelectronic imagers and methods of packaging microelectronic imagers |
US7232754B2 (en) * | 2004-06-29 | 2007-06-19 | Micron Technology, Inc. | Microelectronic devices and methods for forming interconnects in microelectronic devices |
US7416913B2 (en) | 2004-07-16 | 2008-08-26 | Micron Technology, Inc. | Methods of manufacturing microelectronic imaging units with discrete standoffs |
US7189954B2 (en) | 2004-07-19 | 2007-03-13 | Micron Technology, Inc. | Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers |
US7364934B2 (en) * | 2004-08-10 | 2008-04-29 | Micron Technology, Inc. | Microelectronic imaging units and methods of manufacturing microelectronic imaging units |
SG120200A1 (en) | 2004-08-27 | 2006-03-28 | Micron Technology Inc | Slanted vias for electrical circuits on circuit boards and other substrates |
US7300857B2 (en) * | 2004-09-02 | 2007-11-27 | Micron Technology, Inc. | Through-wafer interconnects for photoimager and memory wafers |
US7271482B2 (en) | 2004-12-30 | 2007-09-18 | Micron Technology, Inc. | Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods |
US7795134B2 (en) | 2005-06-28 | 2010-09-14 | Micron Technology, Inc. | Conductive interconnect structures and formation methods using supercritical fluids |
JP4533283B2 (en) * | 2005-08-29 | 2010-09-01 | 新光電気工業株式会社 | Manufacturing method of semiconductor device |
US7863187B2 (en) * | 2005-09-01 | 2011-01-04 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
US7262134B2 (en) | 2005-09-01 | 2007-08-28 | Micron Technology, Inc. | Microfeature workpieces and methods for forming interconnects in microfeature workpieces |
US7892972B2 (en) * | 2006-02-03 | 2011-02-22 | Micron Technology, Inc. | Methods for fabricating and filling conductive vias and conductive vias so formed |
CN101627474A (en) * | 2006-04-20 | 2010-01-13 | Nxp股份有限公司 | Thermal isolation of electronic devices in submount used for leds lighting applications |
US7749899B2 (en) | 2006-06-01 | 2010-07-06 | Micron Technology, Inc. | Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces |
US7629249B2 (en) * | 2006-08-28 | 2009-12-08 | Micron Technology, Inc. | Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods |
US7902643B2 (en) | 2006-08-31 | 2011-03-08 | Micron Technology, Inc. | Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods |
US7768040B2 (en) * | 2006-10-23 | 2010-08-03 | Micron Technology, Inc. | Imager device with electric connections to electrical device |
US7919410B2 (en) * | 2007-03-14 | 2011-04-05 | Aptina Imaging Corporation | Packaging methods for imager devices |
US8193092B2 (en) * | 2007-07-31 | 2012-06-05 | Micron Technology, Inc. | Semiconductor devices including a through-substrate conductive member with an exposed end and methods of manufacturing such semiconductor devices |
SG150410A1 (en) | 2007-08-31 | 2009-03-30 | Micron Technology Inc | Partitioned through-layer via and associated systems and methods |
US7884015B2 (en) | 2007-12-06 | 2011-02-08 | Micron Technology, Inc. | Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods |
US8084854B2 (en) * | 2007-12-28 | 2011-12-27 | Micron Technology, Inc. | Pass-through 3D interconnect for microelectronic dies and associated systems and methods |
JP2009224492A (en) * | 2008-03-14 | 2009-10-01 | Oki Semiconductor Co Ltd | Semiconductor device and method of manufacturing the same |
KR100956379B1 (en) * | 2008-04-24 | 2010-05-07 | 삼성전기주식회사 | Method for inspecting wafer level camera module |
US7968373B2 (en) * | 2008-05-02 | 2011-06-28 | Stats Chippac Ltd. | Integrated circuit package on package system |
US8253230B2 (en) | 2008-05-15 | 2012-08-28 | Micron Technology, Inc. | Disabling electrical connections using pass-through 3D interconnects and associated systems and methods |
US7919348B2 (en) * | 2008-06-13 | 2011-04-05 | Aptina Imaging Corporation | Methods for protecting imaging elements of photoimagers during back side processing |
KR101002680B1 (en) * | 2008-10-21 | 2010-12-21 | 삼성전기주식회사 | Semiconductor package and method of manufacturing the same |
KR20100052638A (en) * | 2008-11-11 | 2010-05-20 | 주식회사 동부하이텍 | Method for manufacturing of image sensor |
US7947601B2 (en) | 2009-03-24 | 2011-05-24 | Micron Technology, Inc. | Semiconductor devices and methods for forming patterned radiation blocking on a semiconductor device |
US8278769B2 (en) * | 2009-07-02 | 2012-10-02 | Avago Technologies Wireless Ip (Singapore) Pte. Ltd. | Compound semiconductor device and connectors |
US8304863B2 (en) | 2010-02-09 | 2012-11-06 | International Business Machines Corporation | Electromigration immune through-substrate vias |
FR2959866A1 (en) * | 2010-05-06 | 2011-11-11 | St Microelectronics Crolles 2 | Method for realizing electrically conducting through connection within semiconductor substrate of integrated circuit, involves forming protection mask that is extended on part of insulating region situated at exterior of opening |
JP2012004677A (en) * | 2010-06-14 | 2012-01-05 | Toshiba Corp | Camera module and manufacturing method for the same |
US9252172B2 (en) | 2011-05-31 | 2016-02-02 | Stats Chippac, Ltd. | Semiconductor device and method of forming EWLB semiconductor package with vertical interconnect structure and cavity region |
US8552518B2 (en) | 2011-06-09 | 2013-10-08 | Optiz, Inc. | 3D integrated microelectronic assembly with stress reducing interconnects |
US9553162B2 (en) | 2011-09-15 | 2017-01-24 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming semiconductor die with active region responsive to external stimulus |
US9564413B2 (en) | 2011-09-15 | 2017-02-07 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming semiconductor die with active region responsive to external stimulus |
FR3007403B1 (en) * | 2013-06-20 | 2016-08-05 | Commissariat Energie Atomique | METHOD FOR PRODUCING A MECHANICALLY AUTONOMOUS MICROELECTRONIC DEVICE |
CN104576664B (en) * | 2013-10-23 | 2018-04-20 | 豪威科技(上海)有限公司 | A kind of back-illuminated type cmos sensor and its manufacture method |
CN105845635B (en) * | 2015-01-16 | 2018-12-07 | 恒劲科技股份有限公司 | Electron package structure |
JP6808714B2 (en) * | 2015-08-03 | 2021-01-06 | フジフイルム エレクトロニック マテリアルズ ユー.エス.エー., インコーポレイテッド | Cleaning composition |
US10276402B2 (en) * | 2016-03-21 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and manufacturing process thereof |
CN207781947U (en) * | 2017-03-10 | 2018-08-28 | 唐虞企业股份有限公司 | Connector with a locking member |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5424573A (en) * | 1992-03-04 | 1995-06-13 | Hitachi, Ltd. | Semiconductor package having optical interconnection access |
EP1157967A2 (en) * | 2000-05-22 | 2001-11-28 | Lucent Technologies Inc. | Packaging micromechanical devices |
US20020006687A1 (en) * | 2000-05-23 | 2002-01-17 | Lam Ken M. | Integrated IC chip package for electronic image sensor die |
US6686588B1 (en) * | 2001-01-16 | 2004-02-03 | Amkor Technology, Inc. | Optical module with lens integral holder |
WO2004054001A2 (en) * | 2002-12-09 | 2004-06-24 | Quantum Semiconductor Llc | Cmos image sensor |
Family Cites Families (103)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6687A (en) * | 1849-09-04 | Bedstead-fastening | ||
DE1160831B (en) * | 1962-04-21 | 1964-01-09 | Knapsack Ag | Method and device for the production of titanium nitride |
US4534100A (en) * | 1982-06-28 | 1985-08-13 | The United States Of America As Represented By The Secretary Of The Air Force | Electrical method of making conductive paths in silicon |
JPS59101882A (en) | 1982-12-03 | 1984-06-12 | Nec Corp | Photo semiconductor device |
JPS59191388A (en) | 1983-04-14 | 1984-10-30 | Victor Co Of Japan Ltd | Semiconductor device |
DE3837063C1 (en) | 1988-10-31 | 1990-03-29 | Reimar Dr. 8000 Muenchen De Lenz | |
US4906314A (en) * | 1988-12-30 | 1990-03-06 | Micron Technology, Inc. | Process for simultaneously applying precut swatches of precured polyimide film to each semiconductor die on a wafer |
JP2828116B2 (en) * | 1990-05-30 | 1998-11-25 | オリンパス光学工業株式会社 | Solid-state imaging device |
US5130783A (en) * | 1991-03-04 | 1992-07-14 | Texas Instruments Incorporated | Flexible film semiconductor package |
US5760834A (en) * | 1992-09-30 | 1998-06-02 | Lsi Logic | Electronic camera with binary lens element array |
JP2833941B2 (en) * | 1992-10-09 | 1998-12-09 | 三菱電機株式会社 | Solid-state imaging device and method of manufacturing the same |
JP3161142B2 (en) * | 1993-03-26 | 2001-04-25 | ソニー株式会社 | Semiconductor device |
JP2950714B2 (en) * | 1993-09-28 | 1999-09-20 | シャープ株式会社 | Solid-state imaging device and method of manufacturing the same |
US5435887A (en) * | 1993-11-03 | 1995-07-25 | Massachusetts Institute Of Technology | Methods for the fabrication of microstructure arrays |
JP3253439B2 (en) * | 1993-12-24 | 2002-02-04 | シャープ株式会社 | Manufacturing method of liquid crystal display element |
US5536455A (en) * | 1994-01-03 | 1996-07-16 | Omron Corporation | Method of manufacturing lens array |
KR0147401B1 (en) * | 1994-02-23 | 1998-08-01 | 구본준 | Solid image sensor and the fabrication method thereof |
JPH07263607A (en) | 1994-03-17 | 1995-10-13 | Sumitomo Kinzoku Ceramics:Kk | Semiconductor package with j-lead and bending method of lead frame |
JP2872051B2 (en) * | 1994-10-04 | 1999-03-17 | カーネル技研株式会社 | Underwater glasses |
JP3239640B2 (en) * | 1994-10-04 | 2001-12-17 | ソニー株式会社 | Semiconductor device manufacturing method and semiconductor device |
US5605783A (en) * | 1995-01-06 | 1997-02-25 | Eastman Kodak Company | Pattern transfer techniques for fabrication of lenslet arrays for solid state imagers |
US5861654A (en) * | 1995-11-28 | 1999-01-19 | Eastman Kodak Company | Image sensor assembly |
US5693967A (en) * | 1995-08-10 | 1997-12-02 | Lg Semicon Co., Ltd. | Charge coupled device with microlens |
JP3263705B2 (en) * | 1995-09-21 | 2002-03-11 | 三菱電機株式会社 | Printed wiring board and flat panel display driving circuit printed wiring board and flat panel display device |
US6013948A (en) * | 1995-11-27 | 2000-01-11 | Micron Technology, Inc. | Stackable chip scale semiconductor package with mating contacts on opposed surfaces |
US5776824A (en) * | 1995-12-22 | 1998-07-07 | Micron Technology, Inc. | Method for producing laminated film/metal structures for known good die ("KG") applications |
JPH09186286A (en) * | 1996-01-05 | 1997-07-15 | Matsushita Electron Corp | Lead frame and mounting method for semiconductor chip |
GB2310952B (en) * | 1996-03-05 | 1998-08-19 | Mitsubishi Electric Corp | Infrared detector |
US6795120B2 (en) * | 1996-05-17 | 2004-09-21 | Sony Corporation | Solid-state imaging apparatus and camera using the same |
NL1003315C2 (en) * | 1996-06-11 | 1997-12-17 | Europ Semiconductor Assembly E | Method for encapsulating an integrated semiconductor circuit. |
US5857963A (en) * | 1996-07-17 | 1999-01-12 | Welch Allyn, Inc. | Tab imager assembly for use in an endoscope |
US6096155A (en) * | 1996-09-27 | 2000-08-01 | Digital Optics Corporation | Method of dicing wafer level integrated multiple optical elements |
JP2924854B2 (en) * | 1997-05-20 | 1999-07-26 | 日本電気株式会社 | Semiconductor device and manufacturing method thereof |
US5821532A (en) * | 1997-06-16 | 1998-10-13 | Eastman Kodak Company | Imager package substrate |
US5811799A (en) * | 1997-07-31 | 1998-09-22 | Wu; Liang-Chung | Image sensor package having a wall with a sealed cover |
JPH1168074A (en) * | 1997-08-13 | 1999-03-09 | Sony Corp | Solid state image sensor |
US5962810A (en) * | 1997-09-09 | 1999-10-05 | Amkor Technology, Inc. | Integrated circuit package employing a transparent encapsulant |
JPH11132857A (en) * | 1997-10-28 | 1999-05-21 | Matsushita Electric Works Ltd | Infrared detector |
US6114240A (en) * | 1997-12-18 | 2000-09-05 | Micron Technology, Inc. | Method for fabricating semiconductor components using focused laser beam |
JPH11326603A (en) * | 1998-05-19 | 1999-11-26 | Seiko Epson Corp | Microlens array and its production thereof, and display |
EP0962978A1 (en) * | 1998-06-04 | 1999-12-08 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of manufacturing same |
US6080291A (en) * | 1998-07-10 | 2000-06-27 | Semitool, Inc. | Apparatus for electrochemically processing a workpiece including an electrical contact assembly having a seal member |
IL126165A0 (en) * | 1998-09-10 | 1999-05-09 | Scitex Corp Ltd | Apparatus for the orthogonal movement of a ccd sensor |
US6566745B1 (en) * | 1999-03-29 | 2003-05-20 | Imec Vzw | Image sensor ball grid array package and the fabrication thereof |
US6274927B1 (en) * | 1999-06-03 | 2001-08-14 | Amkor Technology, Inc. | Plastic package for an optical integrated circuit device and method of making |
US6376868B1 (en) * | 1999-06-15 | 2002-04-23 | Micron Technology, Inc. | Multi-layered gate for a CMOS imager |
JP2001077496A (en) | 1999-09-06 | 2001-03-23 | Ngk Insulators Ltd | Substrate for printed circuit and its manufacture |
DE19952363A1 (en) * | 1999-10-30 | 2001-05-03 | Bosch Gmbh Robert | Optoelectronic receiver |
US6483101B1 (en) * | 1999-12-08 | 2002-11-19 | Amkor Technology, Inc. | Molded image sensor package having lens holder |
US6266197B1 (en) * | 1999-12-08 | 2001-07-24 | Amkor Technology, Inc. | Molded window array for image sensor packages |
JP3736607B2 (en) * | 2000-01-21 | 2006-01-18 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus |
US6351027B1 (en) * | 2000-02-29 | 2002-02-26 | Agilent Technologies, Inc. | Chip-mounted enclosure |
US6285064B1 (en) * | 2000-03-28 | 2001-09-04 | Omnivision Technologies, Inc. | Chip scale packaging technique for optical image sensing integrated circuits |
US6441481B1 (en) * | 2000-04-10 | 2002-08-27 | Analog Devices, Inc. | Hermetically sealed microstructure package |
US6503780B1 (en) * | 2000-07-05 | 2003-01-07 | Amkor Technology, Inc. | Wafer scale image sensor package fabrication method |
US6407381B1 (en) * | 2000-07-05 | 2002-06-18 | Amkor Technology, Inc. | Wafer scale image sensor package |
JP2002094082A (en) * | 2000-07-11 | 2002-03-29 | Seiko Epson Corp | Optical element and its manufacturing method and electronic equipment |
JP3725012B2 (en) * | 2000-08-17 | 2005-12-07 | シャープ株式会社 | Manufacturing method of lens-integrated solid-state imaging device |
TW528889B (en) * | 2000-11-14 | 2003-04-21 | Toshiba Corp | Image pickup apparatus, manufacturing method thereof, and portable electric apparatus |
US6909554B2 (en) * | 2000-12-27 | 2005-06-21 | Finisar Corporation | Wafer integration of micro-optics |
US20020089025A1 (en) * | 2001-01-05 | 2002-07-11 | Li-Kun Chou | Package structure for image IC |
US20020096729A1 (en) * | 2001-01-24 | 2002-07-25 | Tu Hsiu Wen | Stacked package structure of image sensor |
KR100396551B1 (en) * | 2001-02-03 | 2003-09-03 | 삼성전자주식회사 | Wafer level hermetic sealing method |
US6534863B2 (en) * | 2001-02-09 | 2003-03-18 | International Business Machines Corporation | Common ball-limiting metallurgy for I/O sites |
JP3821652B2 (en) * | 2001-02-26 | 2006-09-13 | 三菱電機株式会社 | Imaging device |
US20040012698A1 (en) * | 2001-03-05 | 2004-01-22 | Yasuo Suda | Image pickup model and image pickup device |
US6828663B2 (en) * | 2001-03-07 | 2004-12-07 | Teledyne Technologies Incorporated | Method of packaging a device with a lead frame, and an apparatus formed therefrom |
FR2822326B1 (en) | 2001-03-16 | 2003-07-04 | Atmel Grenoble Sa | LOW COST ELECTRONIC CAMERA IN INTEGRATED CIRCUIT TECHNOLOGY |
US6635941B2 (en) * | 2001-03-21 | 2003-10-21 | Canon Kabushiki Kaisha | Structure of semiconductor device with improved reliability |
JP2002299595A (en) * | 2001-04-03 | 2002-10-11 | Matsushita Electric Ind Co Ltd | Solid state imaging unit and its manufacturing method |
US7057273B2 (en) | 2001-05-15 | 2006-06-06 | Gem Services, Inc. | Surface mount package |
FR2824953B1 (en) | 2001-05-18 | 2004-07-16 | St Microelectronics Sa | OPTICAL SEMICONDUCTOR PACKAGE WITH INCORPORATED LENS AND SHIELDING |
JP4053257B2 (en) * | 2001-06-14 | 2008-02-27 | 新光電気工業株式会社 | Manufacturing method of semiconductor device |
US6734419B1 (en) * | 2001-06-28 | 2004-05-11 | Amkor Technology, Inc. | Method for forming an image sensor package with vision die in lens housing |
KR100427356B1 (en) * | 2001-08-14 | 2004-04-13 | 삼성전기주식회사 | Sub chip on board for optical mouse |
KR100431260B1 (en) | 2001-08-29 | 2004-05-12 | 삼성전기주식회사 | Image module |
US6504196B1 (en) | 2001-08-30 | 2003-01-07 | Micron Technology, Inc. | CMOS imager and method of formation |
US6603183B1 (en) * | 2001-09-04 | 2003-08-05 | Amkor Technology, Inc. | Quick sealing glass-lidded package |
US6759266B1 (en) * | 2001-09-04 | 2004-07-06 | Amkor Technology, Inc. | Quick sealing glass-lidded package fabrication method |
US6778046B2 (en) * | 2001-09-17 | 2004-08-17 | Magfusion Inc. | Latching micro magnetic relay packages and methods of packaging |
US6774486B2 (en) * | 2001-10-10 | 2004-08-10 | Micron Technology, Inc. | Circuit boards containing vias and methods for producing same |
WO2003041174A1 (en) * | 2001-11-05 | 2003-05-15 | Mitsumasa Koyanagi | Solid-state image sensor and its production method |
FR2835654B1 (en) | 2002-02-06 | 2004-07-09 | St Microelectronics Sa | OPTICAL SEMICONDUCTOR PACKAGE WITH COUPLED LENS HOLDER |
TWI229435B (en) * | 2002-06-18 | 2005-03-11 | Sanyo Electric Co | Manufacture of semiconductor device |
US20040038442A1 (en) * | 2002-08-26 | 2004-02-26 | Kinsman Larry D. | Optically interactive device packages and methods of assembly |
US6885107B2 (en) * | 2002-08-29 | 2005-04-26 | Micron Technology, Inc. | Flip-chip image sensor packages and methods of fabrication |
US6808960B2 (en) * | 2002-10-25 | 2004-10-26 | Omni Vision International Holding Ltd | Method for making and packaging image sensor die using protective coating |
JP2004165191A (en) * | 2002-11-08 | 2004-06-10 | Oki Electric Ind Co Ltd | Semiconductor device, method of manufacturing semiconductor device, and camera system |
US6813154B2 (en) * | 2002-12-10 | 2004-11-02 | Motorola, Inc. | Reversible heat sink packaging assembly for an integrated circuit |
SG137651A1 (en) * | 2003-03-14 | 2007-12-28 | Micron Technology Inc | Microelectronic devices and methods for packaging microelectronic devices |
JP3800335B2 (en) * | 2003-04-16 | 2006-07-26 | セイコーエプソン株式会社 | Optical device, optical module, semiconductor device, and electronic apparatus |
US7312101B2 (en) * | 2003-04-22 | 2007-12-25 | Micron Technology, Inc. | Packaged microelectronic devices and methods for packaging microelectronic devices |
SG143932A1 (en) * | 2003-05-30 | 2008-07-29 | Micron Technology Inc | Packaged microelectronic devices and methods of packaging microelectronic devices |
US6934065B2 (en) * | 2003-09-18 | 2005-08-23 | Micron Technology, Inc. | Microelectronic devices and methods for packaging microelectronic devices |
US7091124B2 (en) * | 2003-11-13 | 2006-08-15 | Micron Technology, Inc. | Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices |
US8084866B2 (en) * | 2003-12-10 | 2011-12-27 | Micron Technology, Inc. | Microelectronic devices and methods for filling vias in microelectronic devices |
US7583862B2 (en) * | 2003-11-26 | 2009-09-01 | Aptina Imaging Corporation | Packaged microelectronic imagers and methods of packaging microelectronic imagers |
JP3990347B2 (en) * | 2003-12-04 | 2007-10-10 | ローム株式会社 | Semiconductor chip, manufacturing method thereof, and semiconductor device |
JP4179174B2 (en) * | 2004-01-27 | 2008-11-12 | カシオ計算機株式会社 | Imaging device, manufacturing method thereof, and mounting structure thereof |
US7632713B2 (en) * | 2004-04-27 | 2009-12-15 | Aptina Imaging Corporation | Methods of packaging microelectronic imaging devices |
US7253957B2 (en) * | 2004-05-13 | 2007-08-07 | Micron Technology, Inc. | Integrated optics units and methods of manufacturing integrated optics units for use with microelectronic imagers |
US20050275750A1 (en) * | 2004-06-09 | 2005-12-15 | Salman Akram | Wafer-level packaged microelectronic imagers and processes for wafer-level packaging |
US7199439B2 (en) * | 2004-06-14 | 2007-04-03 | Micron Technology, Inc. | Microelectronic imagers and methods of packaging microelectronic imagers |
-
2004
- 2004-06-29 US US10/879,398 patent/US7294897B2/en not_active Expired - Fee Related
- 2004-11-09 JP JP2007519188A patent/JP4759677B2/en not_active Expired - Fee Related
- 2004-11-09 KR KR1020077002140A patent/KR100909773B1/en not_active IP Right Cessation
- 2004-11-09 CN CNA2004800435031A patent/CN1977382A/en active Pending
- 2004-11-09 DE DE602004023002T patent/DE602004023002D1/en active Active
- 2004-11-09 WO PCT/US2004/037415 patent/WO2006011897A1/en active Application Filing
- 2004-11-09 EP EP09007845A patent/EP2093800B1/en not_active Not-in-force
- 2004-11-09 SG SG200904440-5A patent/SG153876A1/en unknown
- 2004-11-09 AT AT09007845T patent/ATE515799T1/en not_active IP Right Cessation
- 2004-11-09 EP EP04822213A patent/EP1763897B1/en not_active Not-in-force
- 2004-11-09 AT AT04822213T patent/ATE441941T1/en not_active IP Right Cessation
- 2004-11-23 TW TW093136006A patent/TWI305388B/en not_active IP Right Cessation
-
2007
- 2007-09-27 US US11/863,087 patent/US7858429B2/en not_active Expired - Fee Related
-
2010
- 2010-12-23 US US12/977,686 patent/US8053857B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5424573A (en) * | 1992-03-04 | 1995-06-13 | Hitachi, Ltd. | Semiconductor package having optical interconnection access |
EP1157967A2 (en) * | 2000-05-22 | 2001-11-28 | Lucent Technologies Inc. | Packaging micromechanical devices |
US20020006687A1 (en) * | 2000-05-23 | 2002-01-17 | Lam Ken M. | Integrated IC chip package for electronic image sensor die |
US6686588B1 (en) * | 2001-01-16 | 2004-02-03 | Amkor Technology, Inc. | Optical module with lens integral holder |
WO2004054001A2 (en) * | 2002-12-09 | 2004-06-24 | Quantum Semiconductor Llc | Cmos image sensor |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2269944A1 (en) | 2009-06-30 | 2011-01-05 | The Procter & Gamble Company | Liquid dosing apparatus |
WO2011002758A1 (en) | 2009-06-30 | 2011-01-06 | The Procter & Gamble Company | Liquid dosing apparatus |
Also Published As
Publication number | Publication date |
---|---|
JP4759677B2 (en) | 2011-08-31 |
JP2008505481A (en) | 2008-02-21 |
EP1763897B1 (en) | 2009-09-02 |
US20110089539A1 (en) | 2011-04-21 |
TW200601466A (en) | 2006-01-01 |
EP1763897A1 (en) | 2007-03-21 |
TWI305388B (en) | 2009-01-11 |
DE602004023002D1 (en) | 2009-10-15 |
US20080020505A1 (en) | 2008-01-24 |
EP2093800A3 (en) | 2010-03-31 |
US7294897B2 (en) | 2007-11-13 |
EP2093800B1 (en) | 2011-07-06 |
US8053857B2 (en) | 2011-11-08 |
US7858429B2 (en) | 2010-12-28 |
CN1977382A (en) | 2007-06-06 |
ATE441941T1 (en) | 2009-09-15 |
SG153876A1 (en) | 2009-07-29 |
KR20070041728A (en) | 2007-04-19 |
US20050285154A1 (en) | 2005-12-29 |
KR100909773B1 (en) | 2009-07-29 |
ATE515799T1 (en) | 2011-07-15 |
EP2093800A2 (en) | 2009-08-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP2093800B1 (en) | Packaged microelectronic imagers and methods of packaging microelectronic imagers | |
US7498647B2 (en) | Packaged microelectronic imagers and methods of packaging microelectronic imagers | |
US7419841B2 (en) | Microelectronic imagers and methods of packaging microelectronic imagers | |
US8816463B2 (en) | Wafer-level packaged microelectronic imagers having interconnects formed through terminals | |
US11075146B2 (en) | Microfeature workpieces having alloyed conductive structures, and associated methods | |
KR101460141B1 (en) | Chips having rear contacts connected by through vias to front contacts | |
US9373653B2 (en) | Stepped package for image sensor | |
US8247907B2 (en) | Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods | |
EP2087516B1 (en) | Wafer-level fabrication of lidded chips with electrodeposited dielectric coating | |
KR100840502B1 (en) | Semiconductor device and manufacturing mathod thereof | |
US20070049016A1 (en) | Microfeature workpieces and methods for forming interconnects in microfeature workpieces | |
US20080138973A1 (en) | Microelectronic devices and methods for forming interconnects in microelectronic devices |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2007519188 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 200480043503.1 Country of ref document: CN |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWW | Wipo information: withdrawn in national office |
Country of ref document: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2004822213 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020077002140 Country of ref document: KR |
|
WWP | Wipo information: published in national office |
Ref document number: 2004822213 Country of ref document: EP |