WO2006034670A1

WO2006034670A1 - Semiconductor module with stacked semiconductor components and electrical connecting elements between the stacked semiconductor components

Info

Publication number: WO2006034670A1
Application number: PCT/DE2005/001600
Authority: WO
Inventors: Jochen Thomas; Wolfgang Hetzel
Original assignee: Infineon Technologies Ag
Priority date: 2004-09-14
Filing date: 2005-09-13
Publication date: 2006-04-06
Also published as: DE102004044882B3

Abstract

The invention relates to a semiconductor module (3) with stacked semiconductor components (7, 8) and electrical connecting elements (31) between the stacked semiconductor components (7, 8), these stacked semiconductor components (7, 8) having wiring structures (25) on their undersides (41). Outer edge connections (28) are placed on at least one of their housing outer edge sides (26, 27). These outer edge connections (28) are connected via wiring structures (25) to inner connections (29) of the semiconductor components (7, 8). The semiconductor module (3) has, on at least one outer side (30), a grid of electrical connecting elements (31) that is vertically oriented with regard to the wiring structures (25), these electrical connecting elements being integrally and electrically connected to the outer edge connections (28).

Description

Semiconductor module with stacked semiconductor devices and electrical interconnects between the stacked semiconductor devices

The invention relates to a semiconductor module with stacked semiconductor devices and electrical connection elements between the stacked semiconductor devices. The semiconductor components to be stacked on one another have wiring structures on their undersides which are to be connected to one another. Such substrate-based housings are also called BGA housings (ball grid array housings) and, owing to their good electrical properties, combined with a low form factor and comparatively low manufacturing costs, have meanwhile found wide application. Increasingly, BGA packages are also used for memory semiconductor components. In some cases, there are modern memory architectures, such as the DDR2 semiconductor components (double data rate 2 semiconductor components), which can only be realized with BGA packages, because they meet the necessary electrical requirements, by doubling the data rate of 200 to reach 400 megabits per second.

Stacking of semiconductor devices into semiconductor modules is becoming increasingly interesting in order to achieve a high stack density, with two trends having emerged, namely stacking of multiple internal semiconductor chips within a package, also called "stacked FBGA" (fine pitch ball grid array) , and on the other hand stacking two or more individual housings on each other. These solutions have different disadvantages, with the internal semiconductor chip stack posing test problems, since the individual semiconductor devices Chips after their final assembly are no longer testable, and stacking of individual housings incur high costs due to the different measures that must be taken to connect the finished semiconductor devices with each other.

The previously known approaches to the stacking of two or more individual housings have the following disadvantages. In a first solution, thin individual substrates with special peripheral arrangements of spherical contacts are stacked one above the other. This requires expensive materials and special handling in the production necessary. The test of the individual elements is also mechanically demanding, since no standard solder ball contacts with constant surface increase are possible.

Another approach provides for a rewiring foil which leads from additional solder balls to the upper stacked semiconductor device, for which, however, an expensive lower alkaline semiconductor device has to be produced. A threefold "reflow" provided in this structure results in additional manufacturing problems. Another problem solution provides that an upper semiconductor device carries a separate small circuit board which is connected via solder contacts to the main circuit board of the semiconductor module. This results in difficulties in the surface mounting of

Solder contacts. In addition, there is a high overall height and an additional area increase, which increases the space requirement of the semiconductor module of stacked semiconductor components.

Another solution to the stacking problem is known from the publication DE 101 38 278. For stacking Halbleitererbau¬ share conventional semiconductor devices with BGH or LBGA housing (large ball grid array) with additional flexible provided with wiring foils. These additional rewiring foils are larger than the semiconductor devices to be stacked and protrude beyond the edge of the semiconductor devices so as to bend toward a semiconductor device of a semiconductor device stack for a semiconductor module disposed thereunder and over the flexible film to the underlying semiconductor device can be electrically connected.

A semiconductor module with semiconductor components stacked in this way has the disadvantage that the semiconductor components can not be stacked with the least possible space requirement, and sometimes the bent rewiring foil requires a bending radius which can not be undershot without micro-cracks in the rewiring foil Risk rewiring lines.

The object of the invention is to specify a semiconductor module with semiconductor components, wherein the semiconductor components are stacked on one another and have wiring structures on their undersides. In addition, the semiconductor module should also be available for stacking semiconductor components with internal chip stacks. Furthermore, it is an object of the invention that this semiconductor module can be combined with differently constructed base components and with differently structured outer semiconductor components. It is another object of the invention to provide a semiconductor module with stacked semiconductor chips, with which a stacking is not limited to we¬ nige predetermined pattern of semiconductor devices, but in which the arrangement and assignment of verbin¬ denden external contacts can be varied as desired. Furthermore, it is the object of the invention to minimize the space requirement and the space requirement of a semiconductor module, in particular the To reduce the size of a memory module of DRAM semiconductor devices and / or microprocessors.

This object is achieved with the subject of the independent claims. Advantageous developments of the invention will become apparent from the dependent claims.

According to the invention, a semiconductor module with semiconductor components is created, wherein the semiconductor components are stacked on one another. The undersides of the semiconductor components have rewiring structures and have outer edge terminals on at least one outer edge of the housing. These outer peripheral connections are electrically connected via the redistribution structures to internal connections of the semiconductor components. On at least one outer side, the semiconductor module has a grid of electrical connecting elements oriented vertically to the wiring structures of the semiconductor components. These electrical connection elements are materially connected and electrically connected to the outer edge connections.

This semiconductor module has the advantage that the three-dimensional wiring by the horizontally arranged wiring structures of each semiconductor component and by additional outer edge terminals, which are aligned when stacking the main conductor components, does not require any additional space for connecting these edge terminals verti¬ cal direction is required. In addition, thin connecting wires or connecting webs extend as connecting elements in order to connect the outer edge terminals of the semiconductor components to one another in a straight line. Since these connection elements are arranged on the outside of the semiconductor module, in the case of malfunctions, the semiconductor module can be decomposed and defective semiconductor components can be replaced accordingly. The individual testing of the semiconductor components prior to assembly of the semiconductor module is also possible without restriction. All thermal cycling tests, as well as vibration testing at a variety of loads, are possible in the assembly of semiconductor modules in each of the single semiconductor devices to be stacked.

The attachment of vertical connecting elements to the vorgese¬ Henen outer edge connections is not a problem and can be realized with little manufacturing effort. Also, a laying of internal connections of the semiconductor components to the edge sides of the semiconductor components is, unless they are already present in the semiconductor components anyway, not a cost-intensive action. Thus, in the simplest way, a semiconductor module with any storage capacity can be produced cost-effectively by stacking DRAMs. However, it is also equally possible to pack memory elements with logic components by incorporating additional integrated logic circuits, such as microprocessors, in the semiconductor module as a stackable semiconductor component.

In a first embodiment of the invention, the electrical connection elements are separated through contacts on an outer edge of a wiring substrate of one of the stacked semiconductor components. Since basically every semiconductor component in BGA technology or FBGA technology has such a wiring substrate on its underside, it is possible with the narrowest available and feasible connection grid on the circumference of the wiring substrate, which is sawn out of a utility, to provide a maximum number of vias on the traces of the benefit. When dividing the benefit into individual wiring substrates for the semiconductor devices, then arises a variety of Outer edge connections in the form of halved through-contacts. These outer edge terminals in the form of split through contacts may be connected to internal terminals which simultaneously connect an internal stack of semiconductor chips to the outer edge terminals.

Thus, even with this first embodiment of the invention, a maximum increase of the storage capacity can be provided. For example, a first semiconductor chip with its rear side can be fi xed onto the wiring substrate and its active upper side can be connected to a wiring structure of the wiring via bonding connections ¬ substrate the outer edge connections are achieved. Since logic semiconductor chips have their contact surfaces in the edge region, the central region of the logic chip can be used to adhere an insulating spacer plate and to accommodate a memory chip with a central bonding channel on this spacer plate. The upper side of the stacked semiconductor chip with a central bonding channel can in turn have a rewiring structure in order to in turn lead the electrical connections from the electrodes in the central bonding channel to internal connections in the edge region of the stacked semiconductor chip. From these internal connections in the edge region of the stacked semiconductor chip, bond wires can again lead to corresponding contact pads on the wiring substrate, which in turn has a wiring structure which is connected to the outer edge terminals of the semiconductor module.

In a further preferred embodiment of the invention, the housing outer edge of the stacked semiconductor devices has grooves formed vertically to the wiring structures. These molded grooves have the outer grooves of the individual semiconductor components, so that a vertical Verbin¬ tion between the semiconductor devices can be made in a confined space by arranging wire ridges in the shaped grooves. The number of stacked Halbleiterbau- parts is arbitrary, but preferably two

Semiconductor components with internal chip stacks connected with this Tech¬ technology via outer edge connections and corresponding cable webs.

In a further embodiment of the invention, a plurality of connecting elements are held in position by means of a leadframe, wherein the leadframe has a grid of wire webs between transverse webs. In this semiconductor module, all connection elements in the form of conductor bars are initially short-circuited via the transverse webs, which may be advantageous for the transport and for the transfer of the modules. Only shortly before the use of the semiconductor modules, the transverse webs are removed so that the line webs now connect the individual stacked semiconductor components vertically with one another.

As already mentioned, preferably the stacked semiconductor components also have internal semiconductor chip stacks which are electrically connected to the connecting elements of the semiconductor module via a common wiring structure of the stacked semiconductor component and via the outer edge terminals of the stacked semiconductor component. With this structure, the storage capacity of stacked Halbleiterbau¬ parts can be advantageously further increased.

The internal chip stack preferably has semiconductor chips which have contact surfaces on their active upper side in a central region. These contact areas in the central Raler region can be arranged in two rows and are electrically connected via conductor tracks with Innenanschlussflachen on edge regions of the semiconductor chip. In contrast to memory components with a central bonding channel in a wiring foil or in a wiring substrate, these semiconductor chips have neither a wiring foil nor a wiring substrate, but rather conductor tracks formed by a structured metal coating on the active top side of the semiconductor chips become. The contact surfaces arranged in the center can thus be accessed from the edge of the semiconductor chips via the inner contact surfaces arranged in the edge region and the conductor tracks of the metal coating. The inner connection surfaces can be used as bonding surfaces for the chip stack.

In a further embodiment of the invention, the semiconductor module has external contacts on its underside. These are electrically connected via a wiring substrate and via outer edge connections of the wiring substrate to the conductor webs of the semiconductor terminal arranged vertically to the wiring substrate. Thus, it is possible to connect the semiconductor module on a higher-level circuit board with a large number of external contacts located on the underside and at the same time make available the circuit capacitance of the stacked semiconductor components at the external contacts arranged on the underside by the vertically aligned line segments put.

In a further preferred embodiment of the invention, the semiconductor module has as an external contact on the underside of the wiring substrate uniformly distributed solder balls arranged. With these solder balls is a simple Ober¬ surface mounting of the semiconductor module on a parent Circuit substrate possible by a short-term soldering process is performed.

The storage capacity of the individual stacked DRAMs may preferably be in the gigabere range. Such DRAMs have the advantage that they are embedded in flat, large-area Kunststoffgehäu¬ sen, so that correspondingly large edge sides allow attachment of a plurality of edge contact terminals and thus the attachment of a plurality of vertically aligned th webs.

In a further preferred embodiment, it is provided that the semiconductor module has a stacked semiconductor component with a wiring substrate, which in turn has solder balls as internal connection contacts. With these solder balls, however, the overall height of the semiconductor module is increased, so that solutions without solder balls on the wiring substrates of the stacked semiconductor components are preferred.

In a further preferred embodiment, the wiring structure may be accommodated on a wiring film, in particular if the semiconductor module has a stacked component memory component with a central bonding channel. Extremely densely packed semiconductor modules are possible through the wiring film if the wiring film is designed such that it makes outer edge connections available which can be contacted via vertical conductor webs.

A method for producing a semiconductor module with

Semiconductor components that are stacked on top of one another and have wiring structures on their undersides are characterized by the following method steps: First, individual semiconductor devices with outer edge connections are produced on at least one of their outer sides. Subsequently, the semiconductor devices are stacked to align the outer edge terminals in the vertical direction. Finally, the stacked outer edge terminals are electrically connected by applying connecting elements to the outer edge terminals.

In these connection steps, the lower semiconductor component can already have solder balls distributed on the underside as external contacts on external contact surfaces of a wiring substrate. The conductor tracks additionally to be led from the outer contact surfaces of each semiconductor component to the outer edge in order to realize outer edge connections can be taken into account already during the production of the layout for the wiring structure of the wiring substrate. In addition, vias can already be provided on the edge sides during the production of the wiring substrate with the aid of a benefit, which are cut in half when the benefit is separated and thus form first outer edge connections or vertical connection elements for an internal semiconductor chip stack.

In addition, at least on a housing outer edge side of the semiconductor components to be stacked vertically to the

Wiring structures and in the positions of the Außenrandan¬ connections grooves are formed for receiving cable webs. This molding can preferably be carried out in the injection molding process by inserting line webs into the injection mold, so that grooves are present during molding at predetermined positions in the edge sides of the semiconductor component, into which conductor webs of the semiconductor module can then be introduced. The connection of outer edge connections arranged one above the other by application of cable webs to the outer edge connections can be effected by means of laser welding technology or by means of soldering or by adhesive bonding with a conductive adhesive. The cohesive compounds have proven themselves in semiconductor technology and form a reliable process basis for the production of semiconductor modules.

In summary, by providing a simple leadframe having flat leads for mounting leadbars, a cost effective solution to the stacking problem is provided. For this purpose, the leadframe is not provided horizontally but vertically and connects specially modified substrate connections in the form of outer edge connections one above the other. Da¬ in the laser welding is advantageously used, especially since this method is already successful in stacking other Halbleiter¬ components.

The modification of the required wiring substrate is relatively small. Provided external contact pads of each semiconductor device, on which solder balls are otherwise provided, additional connecting leads are led to the edge region, which is already provided in the case of a large number of semiconductor components without a bonding channel. In casings with a bonding channel, these lines can be added to the edge regions without difficulties. At the housing edge, the additional conductor tracks of the wiring structure lead into corresponding plated-through holes through the wiring substrate and can additionally be improved by gilding their surface properties. When singulating the individual housings from an intended common substrate, such as a benefit, for a plurality of semiconductor components, the contact holes in the edge area are sawed through in the middle such that the inner radius is exposed. Advantageously, a singulation separates two housings, so that the exposed halved through contacts can serve as outer edge connections and as vertical connection elements for internal semiconductor chip stacks.

In a further embodiment of the invention, in an injection molding tool or "mold tool" corresponding cable webs are located at the positions above the outer edge connections, so that these webs ensure that no molding compound settles there. As a result of the groove-shaped recesses formed during the molding, the shape of the outer edge connections for the connection of a corresponding vertically equipped flat conductor frame is lengthened, which is advantageous for the attachment of vertical conductor webs.

Semiconductor components prepared in this way can now be assembled to form a semiconductor module for stacking two or more substrate-based packages. The decisive factor is that the edge side contacts to be connected are located one above the other at the same edge positions. The stacking partners themselves can have two or more similar components with the same chips or memory chips, or they can have two or more similar components with different semiconductor chips, for example in a multichip package, or in a "staked the FBGA". Finally, it is possible for various semiconductor components, such as logic semiconductor components and memory semiconductor components, or any other semiconductor components to be used. The combination of these semiconductor devices are stacked together.

The individual stacking partners can themselves again be equipped with solder balls and thus tested with a standard process. On the other hand, it is also possible to apply corresponding needle contacts during testing via the outer contact surfaces on which such external contacts of semiconductor components are arranged and thus also to test semiconductor components without such solder balls in a simple manner before a semiconductor module is assembled.

To produce the stacked connection, the individual partners are aligned so that the cavities or through contacts (either consisting only of through contacts or having vertical recesses or grooves having extended contact holes) are arranged one above the other. Furthermore, a preformed leadframe is placed over all contacts and by laser welding the individual connections are closed with the outer edge contact connections and by Laser¬ corresponding crossbars or Befestigungs¬ rails of the leadframe for the cable webs are abge¬ separated. After all contacts have been connected, the stacked semiconductor module can be tested again and then used.

In summary, the following advantages result:

1. a cost-effective stacking technology; 2. Utilization of substrate-based packages, such as FBGA packages for stacking technology; 3. an increase in electrical performance; 4. a reduction in the vertical size extent of a semiconductor module;

5. a pre-testing of the individual semiconductor components to be stacked so that a reduced rejection of the semiconductor modules occurs;

6. a high variety of stacking possibilities by Einzel¬ chip housing, multi-chip housing and combinations dersel¬ ben.

With this technology, it is possible to double or quadruple the storage density compared to standard storage densities. In the case of, for example, 120 necessary vertical connections, there are, for example, 30 vias per edge side of the semiconductor components; with a connection raster of 0.65 mm, a minimum length of 20 mm is required to accommodate such a number of line ridges on the edge sides. The memory chips which are of interest for such stacking in a semiconductor module are the chips having a high memory density, for example from 1 gigabit to 2 gigabit, since these semiconductor chips already have an edge length of greater than 18 mm. Thus, the connection grid is also sufficient to provide sufficient outer edge contact connections.

The invention will now be explained in more detail with reference to the accompanying figures.

Figure 1 shows a schematic cross section through a

Semiconductor module of a first embodiment of the invention; Figure 2 shows a schematic cross section through a

Semiconductor module of a second embodiment of the invention;

FIG. 3 shows a schematic plan view of a vertically aligned leadframe with electrical connecting elements;

FIG. 4 shows a schematic cross section through a semiconductor module of a third embodiment of FIG

Invention;

Figure 5 shows a schematic cross section through a

Semiconductor module of a fourth embodiment of the invention;

Figure 6 shows a schematic cross section through a

Semiconductor module of a fifth embodiment of the invention.

FIG. 1 shows a schematic cross section through a semiconductor module 1 of a first embodiment of the invention. This semiconductor module 1 has an internal Halbleiterchip¬ stack 40 of the semiconductor chips 13 and 14. Between the semiconductor chips 13 and 14, a spacer isolieren¬ de layer 52 is arranged, since the semiconductor chips 13 and 14 have identical outer dimensions. Both semiconductor chips 13 and 14 have central and double row arranged contact surfaces 54 on the active upper side of the semiconductor chips 13 and 14. Of the contact surfaces 54 in the central region 44 lead tracks 48 of a wiring structure, which is formed by a structured metal coating on the active Ober¬ sides of the semiconductor chips 13 and 14, to indoor Connections 29 in the edge regions of the semiconductor chips 13 and 14, from which the internal connections 29 are connected via bonding connections 49 with a wiring structure 25 on a wiring substrate 34.

The wiring substrate 34 has external contacts 42 on its underside 41, which are arranged on external contact surfaces 50. The outer contact surfaces 50 are electrically connected via lines of the underside 41 and through contacts 51 to the wiring structure 25. At the outer edge 33 of the wiring substrate 34 through-cut contacts 32 are arranged, which in turn are electrically connected to both the bonding connections 49 or with the external contacts 42. At least via these separated through contacts 32, which are also called hollow contacts, three contact planes are joined together at the outer edge 33 of the wiring substrate 34, namely the contact plane of the external contacts 42 and the contact plane of the internal connections 29 of the two semiconductor chips 13 and 14. Furthermore, the contacts of the three contact planes can additionally be connected together via the through contacts 51.

The sectional drawings A, B, C and D, which are identified in Figure 1 with Figure IA, Figure IB, Figure IC and Figure ID, the different structure of the outer edge 33 in the region of the wiring substrate 34 and the structure of the outer surface 30 in the region Plastic housing 47 clearly. In this first embodiment of the invention, only the hollow contacts or through contacts 32 have a recess or grooves in the edge region, while the outside 30 of the semiconductor module 1, as shown in FIGS. 1B and 1C, is completely smooth. To improve the resistance to corrosion and oxidation, the through contacts 32 made of a copper alloy may be coated with a gold layer in the outer edge 33 of the wiring substrate 34. The advantage of these outer edge connections 28 of this first embodiment of the invention is that a large number of vias 32 can be provided in the edge area of the semiconductor component 6 so that a test is possible via these outer edge terminals 28 from separated through contacts 32 without the solder balls 43 must be charged. Even with a surface mounting of this semiconductor module 1 on a higher-level circuit board, it is still possible to access the outer edge terminals 28 on the housing outer edge sides 26 and 27, which is advantageous when testing the component.

FIG. 2 shows a schematic cross section through a semiconductor module 2 of a second embodiment of the invention. Components with the same functions as in FIG. 1 are identified by the same reference symbols and are not discussed separately. This semiconductor module 2 also has an internal

Semiconductor chip stack 40 with memory chips of a few gigabits. The difference between the embodiment according to FIG. 1 and the embodiment according to FIG. 2 can be seen on the sectional drawings FIG. 2A, FIG. 2B, FIG. 2C and FIG. 2D. In this embodiment of the invention, grooves or recesses are provided both in the area of the wiring substrate 34 and in the area of the plastic housing 47, as shown in FIGS. 2B and 2C. These recesses are filled up with line bars 36 as vertical connecting elements 31, via which a further semiconductor component with an internal semiconductor chip stack 40, as shown for example in FIG. 1, can be coupled to the present semiconductor module 1. As a result of the conductor webs 36 aligned vertically with respect to the wiring structure 25, it is possible to establish a connection between semiconductor components to be stacked in the smallest possible space. For this purpose, the recesses or grooves 35 in the plastic housing 47 can be produced by inserting corresponding guide webs 36 into an injection mold or an embossing mold, so that when the mold is removed, these conductor webs 36 either cast in the same way or subsequently into the resulting grooves 35 be inserted. The electrical connection of the line webs 36 with the outer edge terminals 28 in the form of split Durch¬ contacts 32 can be achieved by laser welding. This is the most reliable cohesive method with which the cable webs 36 can be connected to the separated vias 32 of the wiring substrate 34. In general, it is also possible to solder these conductor webs 36 to the separated through contacts 32 or to electrically connect them with a conductive adhesive.

FIG. 3 shows a schematic plan view of a vertically aligned leadframe 37 with electrical connection elements 31. In order to simultaneously apply a plurality of connection elements 31 to the housing outer edge sides of a semiconductor module in the grooves provided, the electrical connection elements 31 are in the form of line webs 36 a lead frame 37 is held in a grid shape. The leadframe 37 has transverse webs 39, which hold the Lei¬ tion webs 36 in position. The grid 38 can first be placed completely on the housing outer edge sides of a semiconductor module with stacked semiconductor components and then connected to the intended outer edge connections. The short circuit that arises through the transverse webs 39, after attaching the frame and Contact the outer edge contacts 32 are removed by laser separation of the supernatant 46 of the grid 38.

FIG. 4 shows a schematic cross section through a semiconductor module 3 of a third embodiment of the invention. The lower semiconductor component 7 corresponds to the semiconductor components 6, which are shown in FIGS. 1 and 2, and has an internal semiconductor chip stack 40 with the semiconductor chips 15 and 16. The stacked semiconductor device 8 with its internal semiconductor chip stack 40 of the semiconductor chips 17 and 18 is indirectly bonded to the upper side of the lower semiconductor device 8 and has no solder balls or solder balls, especially since the two stacked semiconductor chips 17 and 18 via their inner terminals 29 and the wiring structure 25th are connected to corresponding outer edge terminals 28 so that solder balls 43 on the outer contact surfaces 50 of the sta¬ pelten semiconductor device 8 are superfluous. The electrical connection to the upper and lower semiconductor device takes place in this case by connecting elements 31, which are formed as a flat conductor. By eliminating solder balls between the two semiconductor components 7 and 8, the entire semiconductor module 3 is reduced in height h.

FIG. 5 shows a schematic cross section through a semiconductor module 4 of a fourth embodiment of the invention.

Components having the same functions as in the previous figures are identified by the same reference numerals and will not be discussed separately.

This fourth embodiment of the invention largely corresponds to the third embodiment of the invention according to FIG. 4, but the overall height h of the semiconductor module 4 is greater because solder balls 43 of the stacked semiconductor component 9 were maintained. With the internal semiconductor chip stack 40 from the semiconductor chips 19 and 20, the stacked semiconductor component 9 is constructed in the same way as the embodiment according to FIG. 2. The base semiconductor component 10 also has an internal semiconductor chip stack 40 with the semiconductor chips 21 and 22 and corresponds in its construction the semiconductor device 6 shown in FIG. The advantage of this semiconductor module is that no modifications and changes have to be made to the semiconductor components 9 and 10 to be stacked, so that similar semiconductor components 9 and 10 are stacked on top of each other via the conductor bars 36 on the outside 30 of the semiconductor module 4 ¬ can be tied. This brings advantages in testing the semiconductor devices 9.

FIG. 6 shows a schematic cross section through a semiconductor module 5 of a fifth embodiment of the invention, in which case two semiconductor components 11 and 12 are stacked on one another, which have semiconductor chips 23 and 24 with a central bonding channel 44. In the central bonding channel 44, contact surfaces 54 are arranged in two rows, which are connected via bonding wires 49 to conductor tracks 48 on a wiring foil 45. On the wiring film 45, external contacts 42 in the form of solder balls 43 are arranged in the case of the lower semiconductor device 11. In contrast, the upper stacked semiconductor component 12 has no solder balls 43.

The contact surfaces 54 arranged in two rows are here connected by way of bonding wires 49 to a wiring structure 25 of a central bonding channel 55, which are connected directly to outer edge terminals 28 and are connected via the connecting elements 31 in the form of conductor webs 36 to the outer edge of the housing. Pages 26 and 27 are connected to the external contacts 42 of the lower Halb¬ ladder component 11 of the semiconductor module 5. Between the semiconductor components 11 and 12, an adhesive compound 53 is arranged, with which the stacked semiconductor component 12 is fixed on the base semiconductor component 11. The difference between the semiconductor module 5 and the preceding embodiments of the invention lies in the fact that the central bonding channels 55 of the stacked semiconductor components 11 and 12 are aligned in the direction of the external contacts 42 of the semiconductor module 5 and therefore on a self-supporting wiring substrate can be dispensed with semiconductor chips, zu¬ times no internal semiconductor chip stack is provided in this embodiment of the invention.

Claims

claims

1. Semiconductor module with semiconductor components (6-12), wherein the semiconductor components (6-12) are stacked on one another and on their underside wiring structures (25) and on at least one Gehäuseaußen¬ edge side (26, 27) have outer edge terminals (28), wherein the outer edge terminals (28) are electrically connected to inner terminals (29) of the semiconductor components (6-12) via the wiring structures (25), and wherein the semiconductor module (1-5) adjoins at least one outer side (30) Lattice (38), which is aligned vertically with respect to the wiring structures (25), has electrical connection elements (31) which are connected to the outer edge connections (28) in a materially bonded and electrically connected manner.

2. The semiconductor module according to claim 1, characterized in that the electrical connection elements (31) have cut through contacts (32) on an outer edge (33) of a wiring substrate (34) of the stacked semiconductor components (6 - 10).

3. Semiconductor module according to claim 1 or claim 2, characterized in that the housing outer edge sides (26, 27) of the stacked semiconductor components (6-12) vertical to the Verdrah¬ processing structures (25) molded grooves (35), in which line webs (36 ) are arranged as electrical connection elements (31) and are electrically connected to the outer edge terminals (28).

4. Semiconductor module according to one of the preceding claims, characterized in that a plurality of connecting elements (31) by means of a Flach¬ ladder frame (37) are held in position and a grid (38) of wire webs (36) between transverse webs (39).

5. Semiconductor module according to one of the preceding claims, characterized in that the stacked semiconductor components (6 - 10) internal

Semiconductor chip stacks (40) which have a common wiring structure (25) of the stacked semiconductor component (6-12) and the outer edge terminals (28) of the stacked semiconductor component (6-12) with the connection elements (31) of the semiconductor module (40). 1 - 5) are electrically connected.

6. Semiconductor module according to one of the preceding claims, characterized in that the semiconductor module (1 - 5) on its underside (41) has external contacts (42) via a wiring substrate (34) and via outer edge terminals (28) of Ver¬ Wiring substrate (34) with the vertical to the wiring substrate (34) arranged wire webs (36) of the semiconductor module (1-5) electrically connected hen hen.

7. The semiconductor module as claimed in claim 5, characterized in that the internal chip stack (40) has semiconductor chips (13, 14) which have contact surfaces (54) on their active upper side in a central region (44) which are connected via conductor tracks (48 ) with inner connection surfaces (29) on edge regions of the semiconductor chips (13, 14) are in Ver¬ binding, wherein the conductor tracks (48) of a structured metal coating on the active Ober¬ sides of the semiconductor chips (13, 14) are formed.

8. The semiconductor module according to one of claims 5 to 7, characterized in that the internal semiconductor chip stack (40) has memory components, preferably DRAMs, with memory capacities in the gigabit range.

9. Semiconductor module according to one of claims 5 to 7, characterized in that the internal semiconductor chip stack (40) at least one logic chip preferably has a microprocessor.

10. Semiconductor module according to one of the preceding claims, characterized in that a stacked semiconductor component (6 - 10) with a wiring substrate (34) having solder balls (43) as external contacts (42) for the semiconductor module (1 - 5), vor¬ is seen.

11. The semiconductor module according to one of the preceding claims, characterized in that the semiconductor module (1-5) has a memory component with a central bonding channel (55) and wiring foil (45), which has a wiring structure (25), wel¬ che with the External edge connections (28) is electrically connected.

12. A method for producing a semiconductor module (1-5) with semiconductor components (β-12), wherein the semiconductor components (6 - 12) are stacked on top of one another and have wiring structures (25) on their undersides, the method comprising the following method steps: - producing individual semiconductor components (6 - 12) with outer edge connections (28) on at least one outer side ( 30);

Stacking the semiconductor components (6 - 12) while aligning the outer edge terminals (28) in the vertical direction one above the other;

Connecting superposed Außenrandan¬ connections (28) by applying Verbindungsele¬ elements (31) on the outer edge terminals (28).

13. The method according to claim 12, characterized in that in at least one of the housing outer edge sides (26, 27) of the semiconductor components to be stacked (6-12) vertical to the wiring structures (34) and in the positions of the outer edge terminals (28) grooves (35). for receiving wire webs (36) are formed.

14. The method according to claim 12 or claim 13, characterized in that first a flat conductor frame (37) with parallel ange¬ arranged wire webs (36) is made, which are held in position via transverse webs (39), wherein the distances of the wire webs (36 ) corresponds to the spacings of the outer edge terminals (28) of the semiconductor components (6 - 12) and the length of the line webs (36) is greater than the total height (h) of the semiconductor module (1-5), so that when joining Cable webs (36) with the Au¬ ßenrandanschlüssen (28) the transverse webs (39) over the Semiconductor module (1-5) protrude and the supernatants (46) are removed with the transverse webs (39).

15. The method according to any one of claims 12 to 15, characterized in that the connecting superposed Außenrandan- connections (28) by applying wire webs (36) on the outer edge terminals (28) by means of Laserschweiß¬ technology takes place.

16. The method according to any one of claims 12 to 14, characterized in that the connecting superposed Außenrandan¬ connections (28) by applying line webs (36) on the outer edge terminals (28) by means of soldering Lei¬ tion webs (36) on the outer edge terminals (28) follows.

17. The method according to any one of claims 12 to 14, characterized in that the connecting superposed Außenrandan¬ connections (28) by applying line webs (36) on the outer edge terminals (28) by means of adhesive technology with a conductive adhesive.

18. The method according to any one of claims 13 to 17, characterized in that the molding of grooves (35) for receiving Leitungs¬ webs (36) in at least one of the Gehäuseaußenrandsei- th (26, 27) of the semiconductor components to be stacked (6 12) by inserting wire webs (36) into an injection mold before injection molding the plastic Housing (47) of the semiconductor components to be stacked (6-12) takes place.