WO2006039183A3 - Expansion of compute engine code space by sharing adjacent control stores using interleaved program addresses - Google Patents

Expansion of compute engine code space by sharing adjacent control stores using interleaved program addresses Download PDF

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Publication number
WO2006039183A3
WO2006039183A3 PCT/US2005/034010 US2005034010W WO2006039183A3 WO 2006039183 A3 WO2006039183 A3 WO 2006039183A3 US 2005034010 W US2005034010 W US 2005034010W WO 2006039183 A3 WO2006039183 A3 WO 2006039183A3
Authority
WO
WIPO (PCT)
Prior art keywords
control stores
stores
instructions
thread
expansion
Prior art date
Application number
PCT/US2005/034010
Other languages
French (fr)
Other versions
WO2006039183A2 (en
Inventor
Gilbert Wolrich
Mark Rosenbluth
Matthew Adiletta
Hugh Wilkinson
Jose Niell
Rajagopal Narayanan
Sanjeev Jain
Original Assignee
Intel Corp
Gilbert Wolrich
Mark Rosenbluth
Matthew Adiletta
Hugh Wilkinson
Jose Niell
Rajagopal Narayanan
Sanjeev Jain
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Gilbert Wolrich, Mark Rosenbluth, Matthew Adiletta, Hugh Wilkinson, Jose Niell, Rajagopal Narayanan, Sanjeev Jain filed Critical Intel Corp
Priority to EP05799874A priority Critical patent/EP1807755A2/en
Publication of WO2006039183A2 publication Critical patent/WO2006039183A2/en
Publication of WO2006039183A3 publication Critical patent/WO2006039183A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Abstract

Method and apparatus to support expansion of compute engine code space by sharing adjacent control stores using interleaved addressing schemes. Instructions corresponding to an original instruction thread are partitioned into multiple interleaved sequences that are stored in respective control stores. During thread execution, instructions are retrieved from the control stores in a repeated order based on the interleaving scheme. For example, in one embodiment two compute engines share two control stores. Thus, instructions for a given thread are sequentially loaded from the control stores in an alternating manner. In another embodiment, four control stores are shared by four compute engines. In this case, the instructions in a thread are interleave using four stores, and each store is accessed every fourth instruction in the code sequence. Schemes are also provided for handling branching operations to maintain synchronized access to the control stores.
PCT/US2005/034010 2004-09-30 2005-09-21 Expansion of compute engine code space by sharing adjacent control stores using interleaved program addresses WO2006039183A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP05799874A EP1807755A2 (en) 2004-09-30 2005-09-21 Expansion of compute engine code space by sharing adjacent control stores using interleaved program addresses

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/955,643 2004-09-30
US10/955,643 US20060095730A1 (en) 2004-09-30 2004-09-30 Expansion of compute engine code space by sharing adjacent control stores using interleaved program addresses

Publications (2)

Publication Number Publication Date
WO2006039183A2 WO2006039183A2 (en) 2006-04-13
WO2006039183A3 true WO2006039183A3 (en) 2006-11-16

Family

ID=35995093

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/034010 WO2006039183A2 (en) 2004-09-30 2005-09-21 Expansion of compute engine code space by sharing adjacent control stores using interleaved program addresses

Country Status (4)

Country Link
US (1) US20060095730A1 (en)
EP (1) EP1807755A2 (en)
CN (1) CN100388211C (en)
WO (1) WO2006039183A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7707266B2 (en) * 2004-11-23 2010-04-27 Intel Corporation Scalable, high-performance, global interconnect scheme for multi-threaded, multiprocessing system-on-a-chip network processor unit
CN102957493B (en) * 2011-08-18 2016-06-08 上海华为技术有限公司 The processing method of interior interleaving address, recurrence Sequences processing method and relevant apparatus thereof
US10120683B2 (en) * 2016-04-27 2018-11-06 International Business Machines Corporation Supporting even instruction tag (‘ITAG’) requirements in a multi-slice processor using null internal operations (IOPs)
US9996351B2 (en) 2016-05-26 2018-06-12 International Business Machines Corporation Power management of branch predictors in a computer processor
CN111831405A (en) * 2019-04-18 2020-10-27 阿里巴巴集团控股有限公司 Data processing method, logic chip and equipment thereof
CN112053712A (en) * 2019-06-06 2020-12-08 意法半导体国际有限公司 In-memory compute array with integrated bias elements

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4156925A (en) * 1976-04-30 1979-05-29 International Business Machines Corporation Overlapped and interleaved control store with address modifiers
US4823252A (en) * 1986-03-28 1989-04-18 Tandem Computers Incorporated Overlapped control store
EP0328989A1 (en) * 1988-02-18 1989-08-23 Siemens Aktiengesellschaft Circuit to adapt a slow memory to a fast processor
US5815723A (en) * 1990-11-13 1998-09-29 International Business Machines Corporation Picket autonomy on a SIMD machine

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4754396A (en) * 1986-03-28 1988-06-28 Tandem Computers Incorporated Overlapped control store
US4890225A (en) * 1988-04-01 1989-12-26 Digital Equipment Corporation Method and apparatus for branching on the previous state in an interleaved computer program
US6567839B1 (en) * 1997-10-23 2003-05-20 International Business Machines Corporation Thread switch control in a multithreaded processor system
US6427196B1 (en) * 1999-08-31 2002-07-30 Intel Corporation SRAM controller for parallel processor architecture including address and command queue and arbiter
US6606704B1 (en) * 1999-08-31 2003-08-12 Intel Corporation Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4156925A (en) * 1976-04-30 1979-05-29 International Business Machines Corporation Overlapped and interleaved control store with address modifiers
US4823252A (en) * 1986-03-28 1989-04-18 Tandem Computers Incorporated Overlapped control store
EP0328989A1 (en) * 1988-02-18 1989-08-23 Siemens Aktiengesellschaft Circuit to adapt a slow memory to a fast processor
US5815723A (en) * 1990-11-13 1998-09-29 International Business Machines Corporation Picket autonomy on a SIMD machine

Also Published As

Publication number Publication date
US20060095730A1 (en) 2006-05-04
EP1807755A2 (en) 2007-07-18
CN1760835A (en) 2006-04-19
CN100388211C (en) 2008-05-14
WO2006039183A2 (en) 2006-04-13

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