WO2006041520A3 - De-coupled memory access system and method - Google Patents

De-coupled memory access system and method Download PDF

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Publication number
WO2006041520A3
WO2006041520A3 PCT/US2005/010616 US2005010616W WO2006041520A3 WO 2006041520 A3 WO2006041520 A3 WO 2006041520A3 US 2005010616 W US2005010616 W US 2005010616W WO 2006041520 A3 WO2006041520 A3 WO 2006041520A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory access
read
write
coupled
access system
Prior art date
Application number
PCT/US2005/010616
Other languages
French (fr)
Other versions
WO2006041520A2 (en
Inventor
Paul W Hollis
George M Lattimore
Matthew B Rutledge
Original Assignee
Analog Devices Inc
Paul W Hollis
George M Lattimore
Matthew B Rutledge
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc, Paul W Hollis, George M Lattimore, Matthew B Rutledge filed Critical Analog Devices Inc
Priority to EP05731247.2A priority Critical patent/EP1807766B1/en
Priority to CN2005800396440A priority patent/CN101124553B/en
Publication of WO2006041520A2 publication Critical patent/WO2006041520A2/en
Publication of WO2006041520A3 publication Critical patent/WO2006041520A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/229—Timing of a write operation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

A de-coupled memory access system (50) including a memory access control circuit (52) configured to generate first and second independent, de-coupled time references. The memory access control circuit (52) includes a read initiate circuit (54) responsive to the first time reference (58) and a read signal for generating a read-enable signal (66), and a write initiate circuit (58) responsive to the second time reference (60) and a write signal for generating a write enable signal (70) independent of the read enable signal for providing independent, de-coupled write access to a memory array (80).
PCT/US2005/010616 2004-09-30 2005-03-31 De-coupled memory access system and method WO2006041520A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP05731247.2A EP1807766B1 (en) 2004-09-30 2005-03-31 De-coupled memory access system and method
CN2005800396440A CN101124553B (en) 2004-09-30 2005-03-31 De-coupled memory access system and method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/955,609 US7466607B2 (en) 2004-09-30 2004-09-30 Memory access system and method using de-coupled read and write circuits
US10/955,609 2004-09-30

Publications (2)

Publication Number Publication Date
WO2006041520A2 WO2006041520A2 (en) 2006-04-20
WO2006041520A3 true WO2006041520A3 (en) 2007-05-10

Family

ID=36100576

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/010616 WO2006041520A2 (en) 2004-09-30 2005-03-31 De-coupled memory access system and method

Country Status (6)

Country Link
US (1) US7466607B2 (en)
EP (1) EP1807766B1 (en)
KR (1) KR100956470B1 (en)
CN (1) CN101124553B (en)
TW (1) TWI270892B (en)
WO (1) WO2006041520A2 (en)

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US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8225239B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining and utilizing sub-resolution features in linear topology
US7932545B2 (en) 2006-03-09 2011-04-26 Tela Innovations, Inc. Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7943967B2 (en) 2006-03-09 2011-05-17 Tela Innovations, Inc. Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments
US8247846B2 (en) 2006-03-09 2012-08-21 Tela Innovations, Inc. Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US8225261B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining contact grid in dynamic array architecture
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8245180B2 (en) 2006-03-09 2012-08-14 Tela Innovations, Inc. Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US7586800B1 (en) * 2006-08-08 2009-09-08 Tela Innovations, Inc. Memory timing apparatus and associated methods
US7512909B2 (en) * 2006-08-31 2009-03-31 Micron Technology, Inc. Read strobe feedback in a memory system
US7979829B2 (en) 2007-02-20 2011-07-12 Tela Innovations, Inc. Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods
US8286107B2 (en) 2007-02-20 2012-10-09 Tela Innovations, Inc. Methods and systems for process compensation technique acceleration
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US7888705B2 (en) 2007-08-02 2011-02-15 Tela Innovations, Inc. Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
SG10201608214SA (en) 2008-07-16 2016-11-29 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
KR102112024B1 (en) * 2014-04-14 2020-05-19 삼성전자주식회사 Method for forming strobe signal in data storage system and therefore device
US10255880B1 (en) 2015-09-14 2019-04-09 F.lux Software LLC Coordinated adjustment of display brightness
US10163474B2 (en) 2016-09-22 2018-12-25 Qualcomm Incorporated Apparatus and method of clock shaping for memory
WO2019217966A1 (en) 2018-05-11 2019-11-14 F.lux Software LLC Coordinated lighting adjustment for groups
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US20030172241A1 (en) * 2002-03-07 2003-09-11 Hiroshi Shirota High speed, low current consumption FIFO circuit
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See also references of EP1807766A4 *

Also Published As

Publication number Publication date
EP1807766A4 (en) 2009-07-22
CN101124553B (en) 2012-04-25
US20060069894A1 (en) 2006-03-30
EP1807766A2 (en) 2007-07-18
US7466607B2 (en) 2008-12-16
KR20070069157A (en) 2007-07-02
KR100956470B1 (en) 2010-05-07
WO2006041520A2 (en) 2006-04-20
EP1807766B1 (en) 2014-06-04
TW200611276A (en) 2006-04-01
TWI270892B (en) 2007-01-11
CN101124553A (en) 2008-02-13

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