WO2006060116A3 - Multi-bit nanocrystal memory - Google Patents

Multi-bit nanocrystal memory Download PDF

Info

Publication number
WO2006060116A3
WO2006060116A3 PCT/US2005/040151 US2005040151W WO2006060116A3 WO 2006060116 A3 WO2006060116 A3 WO 2006060116A3 US 2005040151 W US2005040151 W US 2005040151W WO 2006060116 A3 WO2006060116 A3 WO 2006060116A3
Authority
WO
WIPO (PCT)
Prior art keywords
trench
nanocrystal
gate structure
bit
trenches
Prior art date
Application number
PCT/US2005/040151
Other languages
French (fr)
Other versions
WO2006060116A2 (en
Inventor
Bohumil Lojek
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to EP05817129A priority Critical patent/EP1820213A4/en
Publication of WO2006060116A2 publication Critical patent/WO2006060116A2/en
Publication of WO2006060116A3 publication Critical patent/WO2006060116A3/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/02—Structural aspects of erasable programmable read-only memories
    • G11C2216/06—Floating gate cells in which the floating gate consists of multiple isolated silicon islands, e.g. nanocrystals

Abstract

An improved memory cell having a nanocrystal gate structure (Fig. 20) is formed by using a plurality of trenches (52, 57) in the manufacturing process. The nanocrystal gate structure (20) is comprised of a tunnel oxide layer (21), a nanocrystal layer (22), and a control oxide layer (23) over a substrate (10). A first trench (52) is formed and doped areas (54, 55) are formed in the substrate near the bottom of the first trench. After at least one doped area is formed, a portion of the nanocrystal structure (20) is removed. The first trench (31) is filled and a second trench (57) is formed that is positioned in close proximity to the location of the first trench. A second portion of the nanocrystal gate structure (20) is then removed near the bottom of the second trench. Using a plurality of trenches, the process reduces the size of the nanocrystal gate structure, thus improving the performance of the memory cell.
PCT/US2005/040151 2004-12-02 2005-11-07 Multi-bit nanocrystal memory WO2006060116A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP05817129A EP1820213A4 (en) 2004-12-02 2005-11-07 Multi-bit nanocrystal memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/001,936 US7170128B2 (en) 2004-12-02 2004-12-02 Multi-bit nanocrystal memory
US11/001,936 2004-12-02

Publications (2)

Publication Number Publication Date
WO2006060116A2 WO2006060116A2 (en) 2006-06-08
WO2006060116A3 true WO2006060116A3 (en) 2007-03-08

Family

ID=36565492

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/040151 WO2006060116A2 (en) 2004-12-02 2005-11-07 Multi-bit nanocrystal memory

Country Status (5)

Country Link
US (2) US7170128B2 (en)
EP (1) EP1820213A4 (en)
CN (1) CN101194355A (en)
TW (1) TW200629484A (en)
WO (1) WO2006060116A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7170128B2 (en) * 2004-12-02 2007-01-30 Atmel Corporation Multi-bit nanocrystal memory
US20090039417A1 (en) * 2005-02-17 2009-02-12 National University Of Singapore Nonvolatile Flash Memory Device and Method for Producing Dielectric Oxide Nanodots on Silicon Dioxide
US8129242B2 (en) * 2006-05-12 2012-03-06 Macronix International Co., Ltd. Method of manufacturing a memory device
TW200812074A (en) * 2006-07-04 2008-03-01 Nxp Bv Non-volatile memory and-array
US7687360B2 (en) * 2006-12-22 2010-03-30 Spansion Llc Method of forming spaced-apart charge trapping stacks
US8486782B2 (en) * 2006-12-22 2013-07-16 Spansion Llc Flash memory devices and methods for fabricating the same
US7927987B2 (en) * 2007-03-27 2011-04-19 Texas Instruments Incorporated Method of reducing channeling of ion implants using a sacrificial scattering layer
WO2008147710A1 (en) * 2007-05-23 2008-12-04 Nanosys, Inc. Gate electrode for a nonvolatile memory cell
US7846793B2 (en) * 2007-10-03 2010-12-07 Applied Materials, Inc. Plasma surface treatment for SI and metal nanocrystal nucleation
CN102446726B (en) * 2010-10-13 2013-10-09 中芯国际集成电路制造(上海)有限公司 Method for forming metal gate
TWI594420B (en) * 2015-01-13 2017-08-01 Xinnova Tech Ltd Non-volatile memory components and methods of making the same
US10319675B2 (en) 2016-01-13 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor embedded with nanocrystals

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6913984B2 (en) * 2002-12-23 2005-07-05 Samsung Electronics Co., Ltd. Method of manufacturing memory with nano dots
US6949788B2 (en) * 1999-12-17 2005-09-27 Sony Corporation Nonvolatile semiconductor memory device and method for operating the same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4648937A (en) * 1985-10-30 1987-03-10 International Business Machines Corporation Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer
US5278439A (en) 1991-08-29 1994-01-11 Ma Yueh Y Self-aligned dual-bit split gate (DSG) flash EEPROM cell
US5541130A (en) 1995-06-07 1996-07-30 International Business Machines Corporation Process for making and programming a flash memory array
US6225201B1 (en) * 1998-03-09 2001-05-01 Advanced Micro Devices, Inc. Ultra short transistor channel length dictated by the width of a sidewall spacer
KR100271211B1 (en) 1998-07-15 2000-12-01 윤덕용 Method for fabricating a non-volatile memory device using nano-crystal dots
US6248633B1 (en) 1999-10-25 2001-06-19 Halo Lsi Design & Device Technology, Inc. Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory
US6744082B1 (en) * 2000-05-30 2004-06-01 Micron Technology, Inc. Static pass transistor logic with transistors with multiple vertical gates
KR100476924B1 (en) * 2002-06-14 2005-03-17 삼성전자주식회사 Method Of Forming Fine Pattern Of Semiconductor Device
US7259984B2 (en) 2002-11-26 2007-08-21 Cornell Research Foundation, Inc. Multibit metal nanocrystal memories and fabrication
US6816414B1 (en) * 2003-07-31 2004-11-09 Freescale Semiconductor, Inc. Nonvolatile memory and method of making same
US7170128B2 (en) * 2004-12-02 2007-01-30 Atmel Corporation Multi-bit nanocrystal memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6949788B2 (en) * 1999-12-17 2005-09-27 Sony Corporation Nonvolatile semiconductor memory device and method for operating the same
US6913984B2 (en) * 2002-12-23 2005-07-05 Samsung Electronics Co., Ltd. Method of manufacturing memory with nano dots

Also Published As

Publication number Publication date
US7170128B2 (en) 2007-01-30
TW200629484A (en) 2006-08-16
US20060121673A1 (en) 2006-06-08
US20070111442A1 (en) 2007-05-17
CN101194355A (en) 2008-06-04
EP1820213A2 (en) 2007-08-22
EP1820213A4 (en) 2008-09-17
WO2006060116A2 (en) 2006-06-08

Similar Documents

Publication Publication Date Title
WO2006060116A3 (en) Multi-bit nanocrystal memory
SG144931A1 (en) Method for forming high-k charge storage device
TW200627631A (en) Non-volatile memory and manufacturing method and operating method thereof
TW200629574A (en) Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
TW200721492A (en) Non-volatile memory and manufacturing method and operation method thereof
TW200701236A (en) Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
TW200701440A (en) Non-volatile memory and manufacturing method and operating method thereof
TW200701442A (en) Method of forming gloating-gate tip for split-gate flosh memory
WO2004057661A3 (en) Non-volatile memory cell and method of fabrication
EP1179839A3 (en) Process for manufacturing a non-volatile memory cell
WO2009032530A3 (en) Thickened sidewall dielectric for memory cell
TW200620482A (en) Memory cell with reduced DIBL and VSS resistance
WO2003067639A3 (en) Method for producing a memory cell
TW200514256A (en) Non-volatile memory device and method of manufacturing the same
TWI257150B (en) Non-volatile memory and fabricating method and operating method thereof
CN101325157A (en) Memory construction and preparation method thereof
TW200629479A (en) Semiconductor device having step gates and method for fabricating the same
TW200419783A (en) Flash memory with selective gate within a substrate and method of fabricating the same
EP1139426A3 (en) Nonvolatile semiconductor memory and method of manufacturing the same
TW200727496A (en) Non-volatile floating gate memory cells and fabrication methods thereof
TW200713513A (en) Memory structure with high coupling ratio and forming method thereof
TW200713518A (en) Non-volatile memory and the fabricating method thereof
TW200633140A (en) Method of fabricating a non-volatile memory
CN109273449B (en) Memory and manufacturing method thereof
TW200607080A (en) Flash memory cell and fabricating method thereof

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200580041548.X

Country of ref document: CN

AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KN KP KR KZ LC LK LR LS LT LU LV LY MA MD MG MK MN MW MX MZ NA NG NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU LV MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
WWE Wipo information: entry into national phase

Ref document number: 2005817129

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE

WWP Wipo information: published in national office

Ref document number: 2005817129

Country of ref document: EP