WO2006060575A3 - Method for forming self-aligned dual salicide in cmos technologies - Google Patents

Method for forming self-aligned dual salicide in cmos technologies Download PDF

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Publication number
WO2006060575A3
WO2006060575A3 PCT/US2005/043474 US2005043474W WO2006060575A3 WO 2006060575 A3 WO2006060575 A3 WO 2006060575A3 US 2005043474 W US2005043474 W US 2005043474W WO 2006060575 A3 WO2006060575 A3 WO 2006060575A3
Authority
WO
WIPO (PCT)
Prior art keywords
type semiconductor
semiconductor device
forming self
cmos technologies
aligned dual
Prior art date
Application number
PCT/US2005/043474
Other languages
French (fr)
Other versions
WO2006060575A2 (en
Inventor
Cyril Cabral Jr
Chester T Dziobkowski
John J Ellis-Monaghan
Sunfei Fang
Christian Lavoie
Zhijiong Luo
James S Nakos
An L Steegen
Clement H Wann
Original Assignee
Ibm
Cyril Cabral Jr
Chester T Dziobkowski
John J Ellis-Monaghan
Sunfei Fang
Christian Lavoie
Zhijiong Luo
James S Nakos
An L Steegen
Clement H Wann
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm, Cyril Cabral Jr, Chester T Dziobkowski, John J Ellis-Monaghan, Sunfei Fang, Christian Lavoie, Zhijiong Luo, James S Nakos, An L Steegen, Clement H Wann filed Critical Ibm
Priority to KR1020077012730A priority Critical patent/KR101055708B1/en
Priority to CN2005800413925A priority patent/CN101069281B/en
Priority to EP05852638A priority patent/EP1825508A4/en
Priority to JP2007544510A priority patent/JP5102628B2/en
Publication of WO2006060575A2 publication Critical patent/WO2006060575A2/en
Publication of WO2006060575A3 publication Critical patent/WO2006060575A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors

Abstract

A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.
PCT/US2005/043474 2004-12-02 2005-12-01 Method for forming self-aligned dual salicide in cmos technologies WO2006060575A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020077012730A KR101055708B1 (en) 2004-12-02 2005-12-01 How to Form Dual Salicide in CMOS Technology
CN2005800413925A CN101069281B (en) 2004-12-02 2005-12-01 Method for forming self-aligned dual salicide in CMOS technologies
EP05852638A EP1825508A4 (en) 2004-12-02 2005-12-01 Method for forming self-aligned dual salicide in cmos technologies
JP2007544510A JP5102628B2 (en) 2004-12-02 2005-12-01 Method for forming self-aligned dual salicide in CMOS technology

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/904,884 US7064025B1 (en) 2004-12-02 2004-12-02 Method for forming self-aligned dual salicide in CMOS technologies
US10/904,884 2004-12-02

Publications (2)

Publication Number Publication Date
WO2006060575A2 WO2006060575A2 (en) 2006-06-08
WO2006060575A3 true WO2006060575A3 (en) 2007-04-26

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/043474 WO2006060575A2 (en) 2004-12-02 2005-12-01 Method for forming self-aligned dual salicide in cmos technologies

Country Status (7)

Country Link
US (3) US7064025B1 (en)
EP (1) EP1825508A4 (en)
JP (1) JP5102628B2 (en)
KR (1) KR101055708B1 (en)
CN (1) CN101069281B (en)
TW (1) TWI371084B (en)
WO (1) WO2006060575A2 (en)

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US7569446B2 (en) * 2007-06-12 2009-08-04 International Business Machines Corporation Semiconductor structure and method of manufacture
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US20100019327A1 (en) * 2008-07-22 2010-01-28 Eun Jong Shin Semiconductor Device and Method of Fabricating the Same
US8021971B2 (en) * 2009-11-04 2011-09-20 International Business Machines Corporation Structure and method to form a thermally stable silicide in narrow dimension gate stacks
CN103456691B (en) * 2012-05-29 2015-07-29 中芯国际集成电路制造(上海)有限公司 The manufacture method of CMOS
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Also Published As

Publication number Publication date
US7067368B1 (en) 2006-06-27
EP1825508A4 (en) 2009-06-24
KR101055708B1 (en) 2011-08-11
US7064025B1 (en) 2006-06-20
US20060121664A1 (en) 2006-06-08
US7112481B2 (en) 2006-09-26
US20060121662A1 (en) 2006-06-08
TW200625540A (en) 2006-07-16
JP2008522444A (en) 2008-06-26
CN101069281A (en) 2007-11-07
TWI371084B (en) 2012-08-21
EP1825508A2 (en) 2007-08-29
JP5102628B2 (en) 2012-12-19
US20060121665A1 (en) 2006-06-08
CN101069281B (en) 2012-05-30
KR20070085805A (en) 2007-08-27
WO2006060575A2 (en) 2006-06-08

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