WO2006065523A3 - Apparatus and method for memory operations using address-dependent conditions - Google Patents

Apparatus and method for memory operations using address-dependent conditions Download PDF

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Publication number
WO2006065523A3
WO2006065523A3 PCT/US2005/043074 US2005043074W WO2006065523A3 WO 2006065523 A3 WO2006065523 A3 WO 2006065523A3 US 2005043074 W US2005043074 W US 2005043074W WO 2006065523 A3 WO2006065523 A3 WO 2006065523A3
Authority
WO
WIPO (PCT)
Prior art keywords
address
memory cell
memory operations
bit
lines
Prior art date
Application number
PCT/US2005/043074
Other languages
French (fr)
Other versions
WO2006065523A2 (en
Inventor
Kenneth K So
Luca G Fasoli
Roy E Scheuerlein
Original Assignee
Matrix Semiconductor Inc
Kenneth K So
Luca G Fasoli
Roy E Scheuerlein
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matrix Semiconductor Inc, Kenneth K So, Luca G Fasoli, Roy E Scheuerlein filed Critical Matrix Semiconductor Inc
Priority to AT05852375T priority Critical patent/ATE496372T1/en
Priority to KR1020077013751A priority patent/KR101100805B1/en
Priority to JP2007546708A priority patent/JP5285277B2/en
Priority to CN200580042742XA priority patent/CN101208751B/en
Priority to EP05852375A priority patent/EP1825475B1/en
Priority to DE602005026052T priority patent/DE602005026052D1/en
Publication of WO2006065523A2 publication Critical patent/WO2006065523A2/en
Publication of WO2006065523A3 publication Critical patent/WO2006065523A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1677—Verifying circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Abstract

An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative to select a writing and/or reading condition to apply to a memory cell based on the memory cell’s location with respect to one or both of a word line driver and a bit line driver. The apparatus can also comprise circuitry that is operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to a word line and/or bit line driver.
PCT/US2005/043074 2004-12-17 2005-11-29 Apparatus and method for memory operations using address-dependent conditions WO2006065523A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
AT05852375T ATE496372T1 (en) 2004-12-17 2005-11-29 APPARATUS AND METHOD FOR STORAGE OPERATIONS USING ADDRESS DEPENDENT CONDITIONS
KR1020077013751A KR101100805B1 (en) 2004-12-17 2005-11-29 Apparatus and method for memory operations using address-dependent conditions
JP2007546708A JP5285277B2 (en) 2004-12-17 2005-11-29 Apparatus and method for memory operation using address dependent conditions
CN200580042742XA CN101208751B (en) 2004-12-17 2005-11-29 Apparatus and method for memory operations using address-dependent conditions
EP05852375A EP1825475B1 (en) 2004-12-17 2005-11-29 Apparatus and method for memory operations using address-dependent conditions
DE602005026052T DE602005026052D1 (en) 2004-12-17 2005-11-29 DEVICE AND METHOD FOR MEMORY OPERATIONS USING ADDRESS-RELATED CONDITIONS

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/015,440 2004-12-17
US11/015,440 US7218570B2 (en) 2004-12-17 2004-12-17 Apparatus and method for memory operations using address-dependent conditions

Publications (2)

Publication Number Publication Date
WO2006065523A2 WO2006065523A2 (en) 2006-06-22
WO2006065523A3 true WO2006065523A3 (en) 2006-10-05

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/043074 WO2006065523A2 (en) 2004-12-17 2005-11-29 Apparatus and method for memory operations using address-dependent conditions

Country Status (8)

Country Link
US (1) US7218570B2 (en)
EP (1) EP1825475B1 (en)
JP (1) JP5285277B2 (en)
KR (1) KR101100805B1 (en)
CN (1) CN101208751B (en)
AT (1) ATE496372T1 (en)
DE (1) DE602005026052D1 (en)
WO (1) WO2006065523A2 (en)

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Also Published As

Publication number Publication date
EP1825475A4 (en) 2009-01-07
CN101208751A (en) 2008-06-25
ATE496372T1 (en) 2011-02-15
KR20070104526A (en) 2007-10-26
US7218570B2 (en) 2007-05-15
US20060133125A1 (en) 2006-06-22
JP5285277B2 (en) 2013-09-11
EP1825475A2 (en) 2007-08-29
CN101208751B (en) 2010-09-15
DE602005026052D1 (en) 2011-03-03
WO2006065523A2 (en) 2006-06-22
EP1825475B1 (en) 2011-01-19
JP2008524772A (en) 2008-07-10
KR101100805B1 (en) 2012-01-02

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