WO2006072598A8 - Verfahren und vorrichtung zum testen von halbleiterwafern mittels einer temperierbaren aufspanneinrichtung - Google Patents

Verfahren und vorrichtung zum testen von halbleiterwafern mittels einer temperierbaren aufspanneinrichtung

Info

Publication number
WO2006072598A8
WO2006072598A8 PCT/EP2006/000142 EP2006000142W WO2006072598A8 WO 2006072598 A8 WO2006072598 A8 WO 2006072598A8 EP 2006000142 W EP2006000142 W EP 2006000142W WO 2006072598 A8 WO2006072598 A8 WO 2006072598A8
Authority
WO
WIPO (PCT)
Prior art keywords
output
temperature
test
semiconductor wafer
regulated
Prior art date
Application number
PCT/EP2006/000142
Other languages
English (en)
French (fr)
Other versions
WO2006072598A1 (de
Inventor
Erich Reitinger
Original Assignee
Erich Reitinger
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=36274039&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2006072598(A8) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Erich Reitinger filed Critical Erich Reitinger
Priority to ES06700504T priority Critical patent/ES2821736T3/es
Priority to EP06700504.1A priority patent/EP1844342B1/de
Priority to CN2006800019567A priority patent/CN101137911B/zh
Priority to KR1020077017504A priority patent/KR101185536B1/ko
Priority to JP2007549867A priority patent/JP4825812B2/ja
Publication of WO2006072598A1 publication Critical patent/WO2006072598A1/de
Publication of WO2006072598A8 publication Critical patent/WO2006072598A8/de

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2855Environmental, reliability or burn-in testing
    • G01R31/2872Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2874Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to temperature
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping

Abstract

Die vorliegende Erfindung schafft ein Verfahren zum Testen von Halbleiterwafern (5) mittels einer temperierbaren Aufspanneinrichtung (1) mit den Schritten: Temperieren der Aufspanneinrichtung (1) mittels einer elektrischen Heizeinrichtung (HE) mit einer vorgegebenen Heizleistung (PW) und einer Kühleinrichtung (11a, 11b, 11c), durch die zur Kühlung ein Fluid (F) geleitet wird, mit einer vorgegebenen Kühlleistung (PK) auf eine vorbestimmte Messtemperatur, wobei die Heizleistung (PW) wesentlich grösser als eine vorgegebene Testleistung (PT) ist; Auflegen der Rückseite (R) eines Halbleiterwafers (5) auf eine Auflageseite (AF) der temperierbaren Aufspanneinrichtung (1); Aufsetzen einer Sondenkarte (7', 7'a) auf die Vorderseite (O) des Halbleiterwafers (5); Testen des Halbleiterwafers (5) durch Einprägen der Testleistung (PT) von einer Testvorrichtung (TV) in einen Chipbereich (CH) der Vorderseite (O) des Halbleiterwafers (5) mittels Sonden (91, 92) der aufgesetzten Sondenkarte (7', 7'a); Erfassen einer die Testleistung (PT) widerspiegelnden Temperaturerhöhung des Fluids (F) beim Testen; und Reduzieren der Heizleistung (PW) während des Testens bei im wesentlichen konstanter Kühlleistung (PK) unter Berücksichtigung der beim Testen erfassten Temperaturerhöhung des Fluids (F). Die Erfindung schafft auch eine entsprechende Vorrichtung.
PCT/EP2006/000142 2005-01-10 2006-01-10 Verfahren und vorrichtung zum testen von halbleiterwafern mittels einer temperierbaren aufspanneinrichtung WO2006072598A1 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
ES06700504T ES2821736T3 (es) 2005-01-10 2006-01-10 Procedimiento y dispositivo para la realización del test de obleas de semiconductor por medio de un dispositivo de fijación atemperable
EP06700504.1A EP1844342B1 (de) 2005-01-10 2006-01-10 Verfahren und vorrichtung zum testen von halbleiterwafern mittels einer temperierbaren aufspanneinrichtung
CN2006800019567A CN101137911B (zh) 2005-01-10 2006-01-10 使用温度可调的卡盘设备来测试半导体晶片的方法和装置
KR1020077017504A KR101185536B1 (ko) 2005-01-10 2006-01-10 온도가 조절될 수 있는 척 장치를 이용한 반도체 웨이퍼테스트 장치 및 방법
JP2007549867A JP4825812B2 (ja) 2005-01-10 2006-01-10 温度を調整可能なチャック装置を用いた半導体ウエハ検査方法および装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005001163A DE102005001163B3 (de) 2005-01-10 2005-01-10 Verfahren und Vorrichtung zum Testen von Halbleiterwafern mittels einer temperierbaren Aufspanneinrichtung
DE102005001163.2 2005-01-10

Publications (2)

Publication Number Publication Date
WO2006072598A1 WO2006072598A1 (de) 2006-07-13
WO2006072598A8 true WO2006072598A8 (de) 2007-09-07

Family

ID=36274039

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2006/000142 WO2006072598A1 (de) 2005-01-10 2006-01-10 Verfahren und vorrichtung zum testen von halbleiterwafern mittels einer temperierbaren aufspanneinrichtung

Country Status (10)

Country Link
US (1) US7271604B2 (de)
EP (1) EP1844342B1 (de)
JP (1) JP4825812B2 (de)
KR (1) KR101185536B1 (de)
CN (1) CN101137911B (de)
DE (1) DE102005001163B3 (de)
ES (1) ES2821736T3 (de)
RU (1) RU2407023C2 (de)
TW (1) TWI371590B (de)
WO (1) WO2006072598A1 (de)

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Also Published As

Publication number Publication date
EP1844342B1 (de) 2020-07-01
KR101185536B1 (ko) 2012-09-24
US7271604B2 (en) 2007-09-18
TW200628818A (en) 2006-08-16
JP4825812B2 (ja) 2011-11-30
CN101137911A (zh) 2008-03-05
RU2007125378A (ru) 2009-02-20
ES2821736T3 (es) 2021-04-27
KR20070110840A (ko) 2007-11-20
WO2006072598A1 (de) 2006-07-13
TWI371590B (en) 2012-09-01
US20060158207A1 (en) 2006-07-20
CN101137911B (zh) 2011-06-08
EP1844342A1 (de) 2007-10-17
DE102005001163B3 (de) 2006-05-18
JP2008527701A (ja) 2008-07-24
RU2407023C2 (ru) 2010-12-20

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