WO2006080999A2 - Non-volatile nanocrystal memory and method therefor - Google Patents
Non-volatile nanocrystal memory and method therefor Download PDFInfo
- Publication number
- WO2006080999A2 WO2006080999A2 PCT/US2005/045207 US2005045207W WO2006080999A2 WO 2006080999 A2 WO2006080999 A2 WO 2006080999A2 US 2005045207 W US2005045207 W US 2005045207W WO 2006080999 A2 WO2006080999 A2 WO 2006080999A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- insulating layer
- forming
- nanocrystals
- nitrogen content
- layer
- Prior art date
Links
- 239000002159 nanocrystal Substances 0.000 title claims abstract description 46
- 230000015654 memory Effects 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 title claims description 29
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 110
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 55
- 239000004065 semiconductor Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 15
- 238000000137 annealing Methods 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 2
- 230000007423 decrease Effects 0.000 claims 2
- 229910052732 germanium Inorganic materials 0.000 claims 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 2
- 229910052735 hafnium Inorganic materials 0.000 claims 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims 2
- 229910052746 lanthanum Inorganic materials 0.000 claims 2
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims 2
- 229910052751 metal Inorganic materials 0.000 claims 2
- 239000002184 metal Substances 0.000 claims 2
- 230000003647 oxidation Effects 0.000 claims 2
- 238000007254 oxidation reaction Methods 0.000 claims 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 230000005524 hole trap Effects 0.000 abstract description 5
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 230000008901 benefit Effects 0.000 description 7
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 6
- 238000012545 processing Methods 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 239000007943 implant Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000036039 immunity Effects 0.000 description 3
- 239000001272 nitrous oxide Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000280 densification Methods 0.000 description 2
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010893 electron trap Methods 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42348—Gate electrodes for transistors with charge trapping gate insulator with trapping site formed by at least two separated sites, e.g. multi-particles trapping site
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
Definitions
- the present invention relates to non-volatile memories having nanocrystals for storage, and more particularly to the insulation of and over such nanocrystals.
- Nanocrystal memories have been found to be advantageous over floating gate memories due to increased immunity to charge leakage through gate dielectric defects.
- One issue in nanocrystal memories is the potential for electron trapping in the dielectric stack under the control gate. This problem occurs during hot carrier injection of electrons into the nanocrystals. A fraction of the electrons not trapped by the nanocrystals can be trapped in the dielectric stack, which leads to a shift in the threshold voltage. These electrons trapped in the dielectric stack are not electrically erasable so they accumulate with repeated program and erase cycles. Thus the shift in threshold voltage continues to grow with the repeated program erase operations and requires circuit designs that attempt to mitigate this effect. In addition to this, dielectric trapped charge can lead to degradation in reliability due to internal electric fields working concomitantly with external bias.
- electrons trapped in the portion of the dielectric stack between the control gate and the nanocrystals can degrade data retention of nanocrystals programmed with electrons by accelerating tunneling loss through the portion of the dielectric stack between the nanocrystals and the substrate.
- FIG. 1 is a cross section of a device structure at a stage in processing according to an embodiment of the invention
- FIG. 2 is a cross section of the device structure of FIG. 1 at a subsequent stage in processing
- FIG. 3 is a cross section of the device structure of FIG. 2 at a subsequent stage in processing
- HG. 4 is a cross section of the device structure of HG. 3 at a subsequent stage in processing
- FTG. 5 is a cross section of the structure of FIG. 4 at a subsequent stage in processing.
- a nanocrystal non- volatile memory has a dielectric between the control gate and the nanocrystals that has a nitrogen content sufficient to reduce the locations in the dielectric where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals where the concentration of electron/hole traps tend to be the highest and is reduced toward the control gate where the concentration of electron/hole traps is lower. This has been found to have the beneficial effect of reducing the number of locations where charge can be trapped. This is better understood with reference to the drawings and the following description. Shown in FIG.
- a semiconductor device 10 comprising a substrate 12, a gate dielectric 14 over substrate 12, a plurality of nanocrystals 16 over the gate dielectric 14.
- Substrate 12 is preferably a bulk silicon substrate but could be an SOI substrate also and could be a different semiconductor material than silicon.
- Gate dielectric layer 14 is preferably a grown oxide that is 50 to 100 Angstroms in thickness and has a graded nitrogen content which is highest farthest from nanocrystals 16 and closest to substrate 12.
- Nanocrystals 16 in this example are made of silicon and have a density of between five times ten to the eleventh (5ell) and 1.2el2 per centimeter squared. Nanocrystals 16 vary in size between about 3 to 10 nanometers. Nanocrystals 16 are preferably deposited by chemical deposition, but other processes may also be used. Other processes for forming nanocrystals include recrystallization of a thin amorphous layer of silicon and the deposition of prefabricated nanocrystals. Subsequent to nanocrystal formation, nanocrystals 16 may be passivated by oxidizing them using nitrous oxide.
- semiconductor device 10 after forming a , nitride-doped oxide layer 18 over and around nanocrystals 16. It is preferably about 3 to five nanometers in thickness and forms a first portion of a dielectric between the nanocrystals and a control gate that is not yet formed.
- the nitrogen content in layer 18 is graded. The highest nitrogen content is closest to the nanocrystals and begins at about 5-10 atomic percent. The nitrogen content is reduced away from nanocrystals 16 to eventually less than about 2 atomic percent.
- This grading is preferably achieved by reacting small amounts of ammonia .with oxide forming gases such as dichlorosilane and nitrous oxide and gradually decreasing the flow rate of the ammonia.
- An alternative is to implant nitrogen into an oxide layer in a series of implant steps.
- the heaviest dose implant is with the highest energy and the lightest dose implant is with the lowest energy.
- This implantation is preferably performed in a remote plasma environment to prevent damage to layer 18.
- the nitrogen in the oxide layer during subsequent annealing steps saturates dangling bonds in the originally formed oxide layer.
- silicon-hydrogen bonds that have weak immunity to hot electrons are converted to more robust silicon-nitrogen bonds. Since the highest concentration of such bond defects is at the interface between dielectric layers, in this case between layers 14 and 18, and between the nanocrystals 16 and dielectric layer 18, a higher concentration of nitrogen is needed in these interface regions. Further away from the interface, the bond defects are fewer and require less nitrogen.
- Dielectric layer 20 is preferably silicon oxide and deposited by reacting a silicon- containing precursor such as silane or dichlorosilane with an oxidizer such as oxygen or nitrous oxide in a chemical vapor deposition chamber at between about 500 and 900 degrees Celsius. Layer 20 is typically between four and ten nanometers in thickness.
- semiconductor device 10 after performing remote plasma nitridation of layer 20 to form a nitrided layer 22.
- the nitrogen content in nitrided layer 22 is preferably less than about 2 atomic percent. Since achieving such small nitrogen content is difficult by CVD, remote plasma deposition is the preferred approach. The energy of the remote plasma can be reduced over time in conjunction with a reduction in the flow of the nitrogen-containing species in order to achieve a graded nitrogen concentration in nitrided layer 22. The higher nitrogen concentration in such case is at the interface of layers 18 and 22 and the lower concentration is at the top surface of layer 22. Implanting nitrogen is also an alternative but remote plasma is preferable due to there being less damage at and near the surface of layer 20 compared to implanting. This remote plasma deposition, with enough energy, can also be utilized to introduce additional nitrogen into layer 18. Additionally, oxygen can be implanted into layer 20 to aid in densification.
- annealing steps are performed, preferably at about greater than 700 degrees Celsius or higher.
- a first of these annealing steps is done in an inert ambient such as nitrogen or argon at about greater than 800 degrees Celsius. This step facilitates nitrogen bonding and expels free hydrogen from layers 18 and 22.
- a second of these annealing steps is in a dilute oxidizing ambient and is for removing non-stoichiometric defects that may still be present.
- a third of these annealing steps is performed close to or about the glass transition temperature, which is about 950 degrees Celsius. The high degree of atomic motion during this reflow condition facilitates the structure to relax the stress of layers 18 and 22.
- the second and third annealing steps may be able to be combined into a single annealing step.
- the annealing temperature preferably does not exceed 1100 degrees Celsius.
- FIG. 5 Shown in FIG. 5 is semiconductor device 10 after performing known steps to form an NVM device comprising a control gate 26, a sidewall spacer 28 around control gate 26, a source/drain region 30 on one side of control gate 26 and in substrate 12, and a source/drain region 32 on the other side of control gate 26 and in substrate 12.
- the resulting semiconductor device 10 of FlG. 5 is a transistor useful as the NVM device and for forming arrays of such devices.
- Layers 18 and 22 with their nitrogen content as described reduces threshold shift due to electron/hole trapping.
- Another benefit of the described approach is that layers 18 and 22 have increased density. Unlike thermally grown oxide such as layer 14, deposited oxides are less dense and stoichiometrically imperfect.
Abstract
A nanocrystal non-volatile memory (NVM) (10) has a dielectric (22) between the control gate (26) and the nanocrystals (16) that has a nitrogen content sufficient to reduce the locations in the dielectric (22) where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals (16) where the concentration of electron/hole traps tend to be the highest and is reduced toward the control gate (26) where the concentration of electron/hole traps is lower. This has been found to have the beneficial effect of reducing the number of locations where charge can be trapped.
Description
NON- VOLATILE NANOCRYSTAL MEMORY AND METHOD THEREFOR
Field of the Invention The present invention relates to non-volatile memories having nanocrystals for storage, and more particularly to the insulation of and over such nanocrystals.
Related Art
Nanocrystal memories have been found to be advantageous over floating gate memories due to increased immunity to charge leakage through gate dielectric defects. One issue in nanocrystal memories is the potential for electron trapping in the dielectric stack under the control gate. This problem occurs during hot carrier injection of electrons into the nanocrystals. A fraction of the electrons not trapped by the nanocrystals can be trapped in the dielectric stack, which leads to a shift in the threshold voltage. These electrons trapped in the dielectric stack are not electrically erasable so they accumulate with repeated program and erase cycles. Thus the shift in threshold voltage continues to grow with the repeated program erase operations and requires circuit designs that attempt to mitigate this effect. In addition to this, dielectric trapped charge can lead to degradation in reliability due to internal electric fields working concomitantly with external bias. For example, electrons trapped in the portion of the dielectric stack between the control gate and the nanocrystals can degrade data retention of nanocrystals programmed with electrons by accelerating tunneling loss through the portion of the dielectric stack between the nanocrystals and the substrate.
Thus, there is a need for a method and structure that alleviates and/or reduces one or more of these problems.
Brief Description of the Drawings
The present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:
FIG. 1 is a cross section of a device structure at a stage in processing according to an embodiment of the invention;
FIG. 2 is a cross section of the device structure of FIG. 1 at a subsequent stage in processing;
FIG. 3 is a cross section of the device structure of FIG. 2 at a subsequent stage in processing;
HG. 4 is a cross section of the device structure of HG. 3 at a subsequent stage in processing; and
FTG. 5 is a cross section of the structure of FIG. 4 at a subsequent stage in processing; and
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
Detailed Description of the Drawings
In one aspect, a nanocrystal non- volatile memory (NVM) has a dielectric between the control gate and the nanocrystals that has a nitrogen content sufficient to reduce the locations in the dielectric where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals where the concentration of electron/hole traps tend to be the highest and is reduced toward the control gate where the concentration of electron/hole traps is lower. This has been found to have the beneficial effect of reducing the number of locations where charge can be trapped. This is better understood with reference to the drawings and the following description. Shown in FIG. 1 is a semiconductor device 10 comprising a substrate 12, a gate dielectric 14 over substrate 12, a plurality of nanocrystals 16 over the gate dielectric 14. Substrate 12 is preferably a bulk silicon substrate but could be an SOI substrate also and could be a different semiconductor material than silicon. Gate dielectric layer 14 is preferably a grown oxide that is 50 to 100 Angstroms in thickness and has a graded nitrogen content which is highest farthest from nanocrystals 16 and closest to substrate 12.
Nanocrystals 16 in this example are made of silicon and have a density of between five times ten to the eleventh (5ell) and 1.2el2 per centimeter squared. Nanocrystals 16 vary in size between about 3 to 10 nanometers. Nanocrystals 16 are preferably deposited by chemical deposition, but other processes may also be used. Other processes for forming nanocrystals include recrystallization of a thin amorphous layer of silicon and the deposition of prefabricated nanocrystals. Subsequent to nanocrystal formation, nanocrystals 16 may be passivated by oxidizing them using nitrous oxide.
Shown in FIG. 2 is semiconductor device 10 after forming a, nitride-doped oxide layer 18 over and around nanocrystals 16. It is preferably about 3 to five nanometers in thickness and forms a first portion of a dielectric between the nanocrystals and a control gate that is not yet formed. The nitrogen content in layer 18 is graded. The highest nitrogen content is closest to the nanocrystals and begins at about 5-10 atomic percent. The nitrogen content is reduced away from nanocrystals 16 to eventually less than about 2 atomic percent. This grading is preferably achieved by reacting small amounts of ammonia .with oxide forming gases such as dichlorosilane and nitrous oxide and gradually decreasing the flow rate of the ammonia. An alternative is to implant nitrogen into an oxide layer in a series of implant steps. The heaviest dose implant is with the highest energy and the lightest dose implant is with the lowest energy. This implantation is preferably performed in a remote plasma environment to prevent damage to layer 18. The nitrogen in the oxide layer during
subsequent annealing steps saturates dangling bonds in the originally formed oxide layer. In particular silicon-hydrogen bonds that have weak immunity to hot electrons are converted to more robust silicon-nitrogen bonds. Since the highest concentration of such bond defects is at the interface between dielectric layers, in this case between layers 14 and 18, and between the nanocrystals 16 and dielectric layer 18, a higher concentration of nitrogen is needed in these interface regions. Further away from the interface, the bond defects are fewer and require less nitrogen. Excessive nitrogen in these areas is deleterious to the memory device by acting as electron/hole traps. Additionally, oxygen can be implanted into layer 18 to aid in densification. Shown in FIG. 3 is semiconductor device 10 after forming a dielectric layer 20 over layer 18. Dielectric layer 20 is preferably silicon oxide and deposited by reacting a silicon- containing precursor such as silane or dichlorosilane with an oxidizer such as oxygen or nitrous oxide in a chemical vapor deposition chamber at between about 500 and 900 degrees Celsius. Layer 20 is typically between four and ten nanometers in thickness. Shown in FIG. 4 is semiconductor device 10 after performing remote plasma nitridation of layer 20 to form a nitrided layer 22. The nitrogen content in nitrided layer 22 is preferably less than about 2 atomic percent. Since achieving such small nitrogen content is difficult by CVD, remote plasma deposition is the preferred approach. The energy of the remote plasma can be reduced over time in conjunction with a reduction in the flow of the nitrogen-containing species in order to achieve a graded nitrogen concentration in nitrided layer 22. The higher nitrogen concentration in such case is at the interface of layers 18 and 22 and the lower concentration is at the top surface of layer 22. Implanting nitrogen is also an alternative but remote plasma is preferable due to there being less damage at and near the surface of layer 20 compared to implanting. This remote plasma deposition, with enough energy, can also be utilized to introduce additional nitrogen into layer 18. Additionally, oxygen can be implanted into layer 20 to aid in densification.
After performing the nitridation, annealing steps are performed, preferably at about greater than 700 degrees Celsius or higher. A first of these annealing steps is done in an inert ambient such as nitrogen or argon at about greater than 800 degrees Celsius. This step facilitates nitrogen bonding and expels free hydrogen from layers 18 and 22. A second of these annealing steps is in a dilute oxidizing ambient and is for removing non-stoichiometric defects that may still be present. A third of these annealing steps is performed close to or about the glass transition temperature, which is about 950 degrees Celsius. The high degree of atomic motion during this reflow condition facilitates the structure to relax the stress of
layers 18 and 22. The second and third annealing steps may be able to be combined into a single annealing step. The annealing temperature preferably does not exceed 1100 degrees Celsius.
Shown in FIG. 5 is semiconductor device 10 after performing known steps to form an NVM device comprising a control gate 26, a sidewall spacer 28 around control gate 26, a source/drain region 30 on one side of control gate 26 and in substrate 12, and a source/drain region 32 on the other side of control gate 26 and in substrate 12. The resulting semiconductor device 10 of FlG. 5 is a transistor useful as the NVM device and for forming arrays of such devices. Layers 18 and 22 with their nitrogen content as described reduces threshold shift due to electron/hole trapping. Another benefit of the described approach is that layers 18 and 22 have increased density. Unlike thermally grown oxide such as layer 14, deposited oxides are less dense and stoichiometrically imperfect. This is typically seen in the significantly faster etch rates of deposited oxides compared to grown oxides. Annealing alone has little impact on increasing the density. The presence of atomic nitrogen and oxygen obtained by remote plasma implantation facilitates unsaturated bond completion due to higher reactivity and leads to a denser oxide and the consequent improvement in electrical characteristics such as breakdown field and hot carrier immunity.
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, the gate dielectric layer 14 was described as grown oxide but could instead be a deposited high k dielectric. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Claims
CLAIMS What is claimed is: 1. A method for forming a semiconductor device comprising: providing a semiconductor substrate; forming a first insulating layer over a surface of the semiconductor substrate; forming a layer of nanocrystals over a surface of the first insulating layer; and forming a second insulating layer having a graded nitrogen content over the layer of nanocrystals.
2. The method of claim 1, further comprising forming a third insulating layer over the second insulating layer, wherein the third insulating layer has a relatively lower nitrogen content than the second insulating layer.
3. The method of claim 2, wherein forming the third insulating layer comprises forming the third insulating layer to have a nitrogen content that less than the lowest nitrogen content of the graded nitrogen content of the second insulating layer.
4. The method of claim 2, further comprising annealing the semiconductor device in an ambient comprising oxygen at a temperature of 700 to 1100 degrees Celsius.
5. The method of claim 2, wherein forming the third insulating layer further comprises uses plasma nitridation to modulate the nitrogen content of the third insulating layer.
6. The method of claim 5, wherein using plasma nitridation comprises reducing a plasma energy of the plasma nitridation source over time to form the graded nitrogen content.
7. The method of claim 5, wherein using plasma nitridation comprises reducing a flow of the nitrogen source over time to form the graded nitrogen content.
8. The method of claim 1, wherein forming the second insulating layer comprising forming the second insulating layer using silicon-oxynitride.
9. The method of claim 1, wherein forming the second insulating layer comprises forming the second insulating layer having a peak nitrogen content of about two atomic percent to about ten atomic percent.
10. The method of claim 1, wherein forming the second insulating layer further comprises using plasma nitridation to modulate the nitrogen content of the second insulating layer.
11. The method of claim 10, wherein using plasma nitridation comprises reducing a plasma energy of the plasma nitridation source over time to form the graded nitrogen content.
12. The method of claim 10, wherein using plasma nitridation comprises reducing a flow of the nitrogen source over time to form the graded nitrogen content.
13. The method of claim 1, wherein forming the second insulating layer further comprises using chemical vapor deposition by flowing gases comprising silicon, an oxidation source, and a nitrogen source.
14. The method of claim 13, wherein forming the second insulating layer further comprises reducing a flow of the nitrogen source over time to form the graded nitrogen content.
15. The method of claim 1, wherein forming the first insulating layer comprises forming the first insulating layer having a nitrogen content that decreases as distance from the semiconductor substrate increases.
16. The method of claim 1, wherein forming the second insulating layer comprises having relatively more nitrogen at an interface with the layer of nanocrystals and relatively less nitrogen as distance from the layer of nanocrystals increases.
17. The method of claim 1, wherein the nanocrystals of the layer of nanocrystals comprises at least one of silicon, germanium, or a metal.
18. The method of claim 1, further comprising coating the nanocrystals with a material comprising nitrogen.
19. The method of claim 1, wherein forming the first insulating layer comprises forming the first insulating layer from an oxide comprising at least one of silicon, hafnium, lanthanum, and aluminum.
20. The method of claim 1 , wherein forming the second insulating layer further comprises using plasma oxidation to improve the stoichiometry of the second insulating layer.
21. A semiconductor device comprising: a semiconductor substrate; a first insulating layer formed over a surface of the semiconductor substrate; a layer of nanocrystals formed over a surface of the first insulating layer; and a second insulating layer having a graded nitrogen content formed over the layer of nanocrystals.
22. The semiconductor device of claim 21 , further comprising a third insulating layer formed over the second insulating layer, wherein the third insulating layer has a relatively lower nitrogen content than the second insulating layer.
23. The semiconductor device of claim 22, wherein the third insulating layer has a nitrogen content that is less than the lowest nitrogen content of the graded nitrogen content of the second insulating layer.
24. The semiconductor device of claim 21, wherein the second insulating layer comprises silicon-oxynitride.
25. The semiconductor device of claim 21, wherein the second insulating layer has a peak nitrogen content of about two atomic percent to about ten atomic percent.
26. The semiconductor device of claim 21, wherein the first insulating layer has a nitrogen content that decreases as distance from the semiconductor substrate increases.
27. The semiconductor device of claim 21 , wherein the second insulating layer comprises having relatively more nitrogen at an interface with the layer of nanocrystals and relatively less nitrogen as distance from the layer of nanocrystals increases.
28. The semiconductor device of claim 21, wherein the nanocrystals of the layer of nanocrystals comprises at least one of silicon, germanium, or a metal.
29. The semiconductor device of claim 21, further comprising the nanocrystals being coated with a layer comprising nitrogen.
30. The semiconductor device of claim 21, wherein the first insulating layer is formed from an oxide comprising at least one of silicon, hafnium, lanthanum, and aluminum.
31. The semiconductor device of claim 21 , wherein the semiconductor device is a nonvolatile memory cell that stores charge in the layer of nanocrystals.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP05854006A EP1844492B1 (en) | 2005-01-26 | 2005-12-14 | Non-volatile nanocrystal memory and method therefor |
JP2007552129A JP4980931B2 (en) | 2005-01-26 | 2005-12-14 | Nonvolatile nanocrystal memory and method thereof |
AT05854006T ATE473515T1 (en) | 2005-01-26 | 2005-12-14 | NON-VOLATILE NANOCRYSTAL MEMORY AND METHOD THEREOF |
DE602005022229T DE602005022229D1 (en) | 2005-01-26 | 2005-12-14 | NON-VOLATILE NANOCRYSTAL STORAGE AND METHOD THEREFOR |
KR1020077017264A KR101219067B1 (en) | 2005-01-26 | 2005-12-14 | Non-volatile nanocrystal memory and method therefor |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/043,826 | 2005-01-26 | ||
US11/043,826 US7361567B2 (en) | 2005-01-26 | 2005-01-26 | Non-volatile nanocrystal memory and method therefor |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2006080999A2 true WO2006080999A2 (en) | 2006-08-03 |
WO2006080999A3 WO2006080999A3 (en) | 2009-04-23 |
Family
ID=36697390
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2005/045207 WO2006080999A2 (en) | 2005-01-26 | 2005-12-14 | Non-volatile nanocrystal memory and method therefor |
Country Status (9)
Country | Link |
---|---|
US (1) | US7361567B2 (en) |
EP (1) | EP1844492B1 (en) |
JP (1) | JP4980931B2 (en) |
KR (1) | KR101219067B1 (en) |
CN (1) | CN101438392A (en) |
AT (1) | ATE473515T1 (en) |
DE (1) | DE602005022229D1 (en) |
TW (1) | TWI407492B (en) |
WO (1) | WO2006080999A2 (en) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100673205B1 (en) * | 2004-11-24 | 2007-01-22 | 주식회사 하이닉스반도체 | Method of manufacturing in flash memory device |
US20060166435A1 (en) * | 2005-01-21 | 2006-07-27 | Teo Lee W | Synthesis of GE nanocrystal memory cell and using a block layer to control oxidation kinetics |
US7338894B2 (en) * | 2005-01-26 | 2008-03-04 | Freescale Semiconductor, Inc. | Semiconductor device having nitridated oxide layer and method therefor |
JP2007036025A (en) * | 2005-07-28 | 2007-02-08 | Nec Electronics Corp | Nonvolatile memory semiconductor device and its manufacturing method |
US7525149B2 (en) * | 2005-08-24 | 2009-04-28 | Micron Technology, Inc. | Combined volatile and non-volatile memory device with graded composition insulator stack |
TWI289336B (en) * | 2005-11-07 | 2007-11-01 | Ind Tech Res Inst | Nanocrystal memory component, manufacturing method thereof and memory comprising the same |
US7767588B2 (en) * | 2006-02-28 | 2010-08-03 | Freescale Semiconductor, Inc. | Method for forming a deposited oxide layer |
US7773493B2 (en) * | 2006-09-29 | 2010-08-10 | Intel Corporation | Probe-based storage device |
US20080150009A1 (en) * | 2006-12-20 | 2008-06-26 | Nanosys, Inc. | Electron Blocking Layers for Electronic Devices |
US8686490B2 (en) * | 2006-12-20 | 2014-04-01 | Sandisk Corporation | Electron blocking layers for electronic devices |
US7847341B2 (en) | 2006-12-20 | 2010-12-07 | Nanosys, Inc. | Electron blocking layers for electronic devices |
US20080150004A1 (en) * | 2006-12-20 | 2008-06-26 | Nanosys, Inc. | Electron Blocking Layers for Electronic Devices |
US7846793B2 (en) * | 2007-10-03 | 2010-12-07 | Applied Materials, Inc. | Plasma surface treatment for SI and metal nanocrystal nucleation |
US7799634B2 (en) * | 2008-12-19 | 2010-09-21 | Freescale Semiconductor, Inc. | Method of forming nanocrystals |
US7871886B2 (en) * | 2008-12-19 | 2011-01-18 | Freescale Semiconductor, Inc. | Nanocrystal memory with differential energy bands and method of formation |
US8021970B2 (en) * | 2009-03-20 | 2011-09-20 | Freescale Semiconductor, Inc. | Method of annealing a dielectric layer |
JP6125846B2 (en) * | 2012-03-22 | 2017-05-10 | 株式会社日立国際電気 | Semiconductor device manufacturing method, substrate processing method, substrate processing apparatus, and program |
CN102709330B (en) * | 2012-05-22 | 2016-04-27 | 上海华力微电子有限公司 | A kind of BE-SONOS structure device and formation method with low operating voltage |
CN102709315A (en) * | 2012-05-22 | 2012-10-03 | 上海华力微电子有限公司 | BE-SONOS (Band-gap Engineering SONOS (Silicon Oxide Nitride Oxide Semiconductor)) structure device with tapered energy band |
US8994006B2 (en) * | 2012-10-02 | 2015-03-31 | International Business Machines Corporation | Non-volatile memory device employing semiconductor nanoparticles |
US8895397B1 (en) | 2013-10-15 | 2014-11-25 | Globalfoundries Singapore Pte. Ltd. | Methods for forming thin film storage memory cells |
US9171858B2 (en) | 2013-12-30 | 2015-10-27 | Globalfoundries Singapore Pte. Ltd. | Multi-level memory cells and methods for forming multi-level memory cells |
US9953841B2 (en) * | 2015-05-08 | 2018-04-24 | Macronix International Co., Ltd. | Semiconductor device and method of fabricating the same |
DE102020100099A1 (en) | 2019-09-30 | 2021-04-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | GATE STRUCTURES IN SEMICONDUCTOR DEVICES |
US11756832B2 (en) * | 2019-09-30 | 2023-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate structures in semiconductor devices |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6320784B1 (en) * | 2000-03-14 | 2001-11-20 | Motorola, Inc. | Memory cell and method for programming thereof |
US6413819B1 (en) * | 2000-06-16 | 2002-07-02 | Motorola, Inc. | Memory device and method for using prefabricated isolated storage elements |
WO2001099167A2 (en) * | 2000-06-16 | 2001-12-27 | Motorola, Inc. | Memory device including nanoclusters and method for manufacture |
US6297095B1 (en) * | 2000-06-16 | 2001-10-02 | Motorola, Inc. | Memory device that includes passivated nanoclusters and method for manufacture |
TW525263B (en) * | 2000-09-28 | 2003-03-21 | Chartered Semiconductor Mfg | Formation of interfacial oxide layer at the Si3N4/Si interface by H2/O2 annealing |
US6444545B1 (en) * | 2000-12-19 | 2002-09-03 | Motorola, Inc. | Device structure for storing charge and method therefore |
JP2002261175A (en) * | 2000-12-28 | 2002-09-13 | Sony Corp | Nonvolatile semiconductor memory and its manufacturing method |
JP2002231834A (en) | 2001-02-02 | 2002-08-16 | Ricoh Co Ltd | Semiconductor memory |
US6713127B2 (en) * | 2001-12-28 | 2004-03-30 | Applied Materials, Inc. | Methods for silicon oxide and oxynitride deposition using single wafer low pressure CVD |
TW569377B (en) * | 2002-03-20 | 2004-01-01 | Taiwan Semiconductor Mfg | Improvement method for thickness uniformity of super-thin nitridation gate dielectric |
JP2004207613A (en) * | 2002-12-26 | 2004-07-22 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
US7338894B2 (en) * | 2005-01-26 | 2008-03-04 | Freescale Semiconductor, Inc. | Semiconductor device having nitridated oxide layer and method therefor |
-
2005
- 2005-01-26 US US11/043,826 patent/US7361567B2/en not_active Expired - Fee Related
- 2005-12-14 DE DE602005022229T patent/DE602005022229D1/en active Active
- 2005-12-14 KR KR1020077017264A patent/KR101219067B1/en not_active IP Right Cessation
- 2005-12-14 CN CNA2005800409629A patent/CN101438392A/en active Pending
- 2005-12-14 WO PCT/US2005/045207 patent/WO2006080999A2/en active Application Filing
- 2005-12-14 AT AT05854006T patent/ATE473515T1/en not_active IP Right Cessation
- 2005-12-14 JP JP2007552129A patent/JP4980931B2/en not_active Expired - Fee Related
- 2005-12-14 EP EP05854006A patent/EP1844492B1/en not_active Not-in-force
-
2006
- 2006-01-04 TW TW095100396A patent/TWI407492B/en active
Non-Patent Citations (1)
Title |
---|
See references of EP1844492A4 * |
Also Published As
Publication number | Publication date |
---|---|
ATE473515T1 (en) | 2010-07-15 |
KR101219067B1 (en) | 2013-01-18 |
US7361567B2 (en) | 2008-04-22 |
TWI407492B (en) | 2013-09-01 |
EP1844492B1 (en) | 2010-07-07 |
US20060166452A1 (en) | 2006-07-27 |
KR20070099625A (en) | 2007-10-09 |
JP4980931B2 (en) | 2012-07-18 |
DE602005022229D1 (en) | 2010-08-19 |
EP1844492A4 (en) | 2009-10-21 |
EP1844492A2 (en) | 2007-10-17 |
TW200629383A (en) | 2006-08-16 |
WO2006080999A3 (en) | 2009-04-23 |
JP2008532260A (en) | 2008-08-14 |
CN101438392A (en) | 2009-05-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7361567B2 (en) | Non-volatile nanocrystal memory and method therefor | |
US6949433B1 (en) | Method of formation of semiconductor resistant to hot carrier injection stress | |
US20220173216A1 (en) | Sonos stack with split nitride memory layer | |
US6740605B1 (en) | Process for reducing hydrogen contamination in dielectric materials in memory devices | |
KR100894098B1 (en) | Nonvolatile memory device having fast erase speed and improoved retention charactericstics, and method of fabricating the same | |
US6642573B1 (en) | Use of high-K dielectric material in modified ONO structure for semiconductor devices | |
US8614124B2 (en) | SONOS ONO stack scaling | |
US8643124B2 (en) | Oxide-nitride-oxide stack having multiple oxynitride layers | |
US6803275B1 (en) | ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices | |
US20070066083A1 (en) | Method of forming a silicon-rich nanocrystalline structure by an atomic layer deposition process and method of manufacturing a non-volatile semiconductor device using the same | |
US6958511B1 (en) | Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen | |
JP4617574B2 (en) | Nonvolatile semiconductor memory device and manufacturing method thereof | |
US20090124096A1 (en) | Method of fabricating flash memory device | |
US6955965B1 (en) | Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device | |
US6765254B1 (en) | Structure and method for preventing UV radiation damage and increasing data retention in memory cells | |
US7163860B1 (en) | Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device | |
US20090032861A1 (en) | Nonvolatile memories with charge trapping layers containing silicon nitride with germanium or phosphorus | |
US20070202645A1 (en) | Method for forming a deposited oxide layer | |
JP2002261175A (en) | Nonvolatile semiconductor memory and its manufacturing method | |
JP4358504B2 (en) | Method for manufacturing nonvolatile semiconductor memory device | |
US6992370B1 (en) | Memory cell structure having nitride layer with reduced charge loss and method for fabricating same | |
KR100791333B1 (en) | Method for fabricating nonvolatible memory device and nonvolatible memory device fabricated thereby | |
KR20080010514A (en) | Method of forming a dielectric layer structure and method of forming a non-volatile memory device using the same | |
US20130256779A1 (en) | Method of manufacturing semiconductor device and semiconductor device | |
KR20070109633A (en) | Method for fabricating non-volatile memory device and non-volatile memory device fabricated thereby |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200580040962.9 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 2005854006 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2007552129 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020077017264 Country of ref document: KR |
|
WWP | Wipo information: published in national office |
Ref document number: 2005854006 Country of ref document: EP |