WO2006081096A8 - Digital transmit phase trimming - Google Patents
Digital transmit phase trimmingInfo
- Publication number
- WO2006081096A8 WO2006081096A8 PCT/US2006/001592 US2006001592W WO2006081096A8 WO 2006081096 A8 WO2006081096 A8 WO 2006081096A8 US 2006001592 W US2006001592 W US 2006001592W WO 2006081096 A8 WO2006081096 A8 WO 2006081096A8
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- accordance
- signal
- digital transmit
- transmit phase
- signals
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0033—Correction by delay
- H04L7/0037—Delay of clock signal
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
Abstract
A circuit has a phase adjustment circuit to generate an adjusted clock signal by adjusting a first clock signal in accordance with a control signal. A multiplexer receives input data signals on a plurality of first data lines and outputs onto at least one second data line output data signals in accordance with a plurality of second clock signals. A timing measurement circuit determines at least one timing parameter of at least one output data signal on at least the one second data line and generates the control signal in accordance with a deviation of at least the one timing parameter from a desired value.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP06718643A EP1844553B1 (en) | 2005-01-27 | 2006-01-13 | Digital transmit phase trimming |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/046,451 | 2005-01-27 | ||
US11/046,451 US7627069B2 (en) | 2005-01-27 | 2005-01-27 | Digital transmit phase trimming |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2006081096A2 WO2006081096A2 (en) | 2006-08-03 |
WO2006081096A3 WO2006081096A3 (en) | 2007-04-19 |
WO2006081096A8 true WO2006081096A8 (en) | 2007-08-30 |
Family
ID=36696758
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2006/001592 WO2006081096A2 (en) | 2005-01-27 | 2006-01-13 | Digital transmit phase trimming |
Country Status (3)
Country | Link |
---|---|
US (2) | US7627069B2 (en) |
EP (1) | EP1844553B1 (en) |
WO (1) | WO2006081096A2 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007027833A2 (en) * | 2005-09-02 | 2007-03-08 | Cypress Semiconductor Corp. | Circuit, system, and method for multiplexing signals with reduced jitter |
US9209912B2 (en) * | 2009-11-18 | 2015-12-08 | Silicon Laboratories Inc. | Circuit devices and methods for re-clocking an input signal |
US9929972B2 (en) * | 2011-12-16 | 2018-03-27 | Qualcomm Incorporated | System and method of sending data via a plurality of data lines on a bus |
US9495271B2 (en) * | 2014-01-29 | 2016-11-15 | Freescale Semiconductor, Inc. | Statistical power indication monitor for purpose of measuring power consumption |
US9857865B2 (en) * | 2015-12-10 | 2018-01-02 | Aspeed Technology Inc. | Balancing of servers based on sampled utilization ratio and corresponding power consumption |
US10027280B1 (en) * | 2017-07-18 | 2018-07-17 | Novatek Microelectronics Corp. | Inductor-less local oscillator generation apparatus |
US20230208423A1 (en) * | 2021-12-24 | 2023-06-29 | Samsung Electronics Co., Ltd. | Systems and methods for quarter rate serialization |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3654394A (en) | 1969-07-08 | 1972-04-04 | Gordon Eng Co | Field effect transistor switch, particularly for multiplexing |
US6570944B2 (en) * | 2001-06-25 | 2003-05-27 | Rambus Inc. | Apparatus for data recovery in a synchronous chip-to-chip system |
US4390988A (en) | 1981-07-14 | 1983-06-28 | Rockwell International Corporation | Efficient means for implementing many-to-one multiplexing logic in CMOS/SOS |
US5075566A (en) | 1990-12-14 | 1991-12-24 | International Business Machines Corporation | Bipolar emitter-coupled logic multiplexer |
US5406198A (en) * | 1992-06-05 | 1995-04-11 | Hitachi, Ltd. | Digital circuitry apparatus |
US5714904A (en) | 1994-06-06 | 1998-02-03 | Sun Microsystems, Inc. | High speed serial link for fully duplexed data communication |
JPH0845188A (en) * | 1994-07-29 | 1996-02-16 | Sony Corp | Recording method and its recording device and reproducing device |
US5850422A (en) * | 1995-07-21 | 1998-12-15 | Symbios, Inc. | Apparatus and method for recovering a clock signal which is embedded in an incoming data stream |
JPH09247116A (en) | 1996-03-08 | 1997-09-19 | Fujitsu Ltd | Serial-parallel converting circuit and synchronization circuit of the same |
US6674772B1 (en) | 1999-10-28 | 2004-01-06 | Velio Communicaitons, Inc. | Data communications circuit with multi-stage multiplexing |
US20020097682A1 (en) * | 2000-06-02 | 2002-07-25 | Enam Syed K. | Low frequency loop-back in a high speed optical transceiver |
US6917660B2 (en) * | 2001-06-04 | 2005-07-12 | Intel Corporation | Adaptive de-skew clock generation |
US7443941B2 (en) | 2003-01-22 | 2008-10-28 | Rambus Inc. | Method and system for phase offset cancellation in systems using multi-phase clocks |
US6677793B1 (en) | 2003-02-03 | 2004-01-13 | Lsi Logic Corporation | Automatic delay matching circuit for data serializer |
US7149269B2 (en) * | 2003-02-27 | 2006-12-12 | International Business Machines Corporation | Receiver for clock and data recovery and method for calibrating sampling phases in a receiver for clock and data recovery |
US7230460B1 (en) * | 2003-03-04 | 2007-06-12 | Lsi Corporation | Digital visual interface |
US20050108600A1 (en) * | 2003-11-19 | 2005-05-19 | Infineon Technologies Ag | Process and device for testing a serializer circuit arrangement and process and device for testing a deserializer circuit arrangement |
US7038510B2 (en) * | 2004-07-02 | 2006-05-02 | Broadcom Corporation | Phase adjustment method and circuit for DLL-based serial data link transceivers |
US7397876B2 (en) * | 2004-08-11 | 2008-07-08 | International Business Machines Corporation | Methods and arrangements for link power reduction |
-
2005
- 2005-01-27 US US11/046,451 patent/US7627069B2/en active Active
-
2006
- 2006-01-13 EP EP06718643A patent/EP1844553B1/en active Active
- 2006-01-13 WO PCT/US2006/001592 patent/WO2006081096A2/en active Application Filing
-
2009
- 2009-12-01 US US12/628,982 patent/US7924963B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP1844553B1 (en) | 2012-10-31 |
US20100074385A1 (en) | 2010-03-25 |
US7924963B2 (en) | 2011-04-12 |
EP1844553A2 (en) | 2007-10-17 |
WO2006081096A2 (en) | 2006-08-03 |
US20060165205A1 (en) | 2006-07-27 |
WO2006081096A3 (en) | 2007-04-19 |
US7627069B2 (en) | 2009-12-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
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