WO2006083693A2 - Etchant treatment processes for substrate surfaces and chamber surfaces - Google Patents

Etchant treatment processes for substrate surfaces and chamber surfaces Download PDF

Info

Publication number
WO2006083693A2
WO2006083693A2 PCT/US2006/002841 US2006002841W WO2006083693A2 WO 2006083693 A2 WO2006083693 A2 WO 2006083693A2 US 2006002841 W US2006002841 W US 2006002841W WO 2006083693 A2 WO2006083693 A2 WO 2006083693A2
Authority
WO
WIPO (PCT)
Prior art keywords
silicon
gas
substrate
chamber
etching
Prior art date
Application number
PCT/US2006/002841
Other languages
French (fr)
Other versions
WO2006083693A3 (en
WO2006083693B1 (en
Inventor
Arkadii V. Samoilov
Ali Zojaji
Original Assignee
Applied Materials, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/047,323 external-priority patent/US7235492B2/en
Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Priority to EP06719625A priority Critical patent/EP1848550A4/en
Priority to JP2007553243A priority patent/JP5329094B2/en
Priority to CN200680010817.0A priority patent/CN101155648B/en
Publication of WO2006083693A2 publication Critical patent/WO2006083693A2/en
Publication of WO2006083693A3 publication Critical patent/WO2006083693A3/en
Publication of WO2006083693B1 publication Critical patent/WO2006083693B1/en

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B08—CLEANING
    • B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B7/00—Cleaning by methods not provided for in a single other subclass or a single group in this subclass
    • B08B7/0035—Cleaning by methods not provided for in a single other subclass or a single group in this subclass by radiant energy, e.g. UV, laser, light beam or the like
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B08—CLEANING
    • B08B—CLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
    • B08B6/00—Cleaning by electrostatic means
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F1/00—Electrolytic cleaning, degreasing, pickling or descaling
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25F—PROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00—Electrolytic etching or polishing
    • C25F3/16—Polishing
    • C25F3/30—Polishing of semiconducting materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02046—Dry cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H01L21/02661—In-situ cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Definitions

  • Embodiments of the invention generally relate to the field of electronic manufacturing processes and devices, more particular, to methods of etching and depositing silicon-containing materials while forming electronic devices.
  • Electronic devices such as semiconductor devices are fabricated by an assortment of steps including the deposition and removal of silicon-containing materials.
  • the deposition and. removal steps as well as other process steps may cause the substrate surface containing a silicon-containing material to become rough and/or bare contaminants.
  • particulates and other contaminants accumulate on the interior surfaces within a process chamber during the deposition and removal steps. The particulates may eventually further contaminate the substrate surface. Rough or contaminated substrate surfaces generally lead to poor quality interfaces which provide poor device performance and reliability.
  • Etching processes have been developed to combat contaminants and roughness on substrate surfaces.
  • the traditional etching processes have some draw backs.
  • etchants such as hydrogen chloride (HCI)
  • HCI hydrogen chloride
  • etching processes are often conducted at temperatures of 1 ,000 0 C or higher.
  • Such high temperatures are not desirable during a fabrication process due to thermal budget considerations, possible uncontrolled nitridation reactions or over- etching to the substrate surface and loss of economically efficiencies.
  • Etching processes with such extreme conditions may damage interior surfaces within the chamber, such as thermal quartz liners.
  • Chlorine (Cl 2 ) has been used to remove silicon-containing materials during etch processes at lower temperatures than processes that utilize hydrogen chloride etchants.
  • chlorine reacts very quickly with silicon-containing materials and thus the etch rate is not easily controllable. Therefore, silicon-containing materials are usually over etched by processes using chlorine gas.
  • etching processes generally are conducted in an etching chamber or a thermal processing chamber. Once the etching of the silicon- containing material is complete, the substrate is transferred into a secondary chamber for a subsequent deposition process. Often, the substrate is exposed to the ambient environment between the etching process and the deposition process. The ambient environment may introduce water and/or oxygen to the substrate surface forming an oxide layer.
  • a substrate Prior to the etching process or the deposition process, a substrate is usually exposed to a pre-treatment process including a wet clean process (e.g., a HF-last process), a plasma clean or an acid wash process.
  • a pre-treatment process including a wet clean process (e.g., a HF-last process), a plasma clean or an acid wash process.
  • the substrate may have to reside outside the process chamber or controlled environment for a period of time called the queue time (Q-time).
  • the substrate is exposed to ambient environmental conditions that include oxygen and water at atmospheric pressure and room temperature.
  • the ambient exposure forms an oxide layer on the substrate surface, such as silicon oxide.
  • longer Q-times form thicker oxide layers and therefore more extreme etching processes must be conducted at higher temperatures and pressures to maintain throughput.
  • a method for finishing or treating a silicon-containing surface which includes smoothing the surface and removing contaminants contained on the surface.
  • a substrate is placed into a process chamber and heated to a temperature within a range from about 500 0 C to about 700 0 C.
  • the substrate is exposed to an etching gas containing an etchant, a silicon source and a carrier gas.
  • Chlorine gas (CI 2 ) may be used as the etchant so that a relatively low temperature is used during the etching process.
  • a silicon source is usually provided simultaneously with the etchant in order to counter act any over-etching caused by the etchant.
  • the silicon source is used to deposit silicon on a substrate surface while the etchant removes the silicon.
  • the rates at which the etchant and the silicon source are exposed to the substrate are adjusted so that the overall reaction favors material removal and/or redistribution. Therefore, in one example, the etch rate may be finely controlled (e.g., several angstroms or less per minute) while removing a silicon-containing material during an overall reaction.
  • silicon-containing material is removed from higher portions of the surface (i.e., peaks) while added to the lower portions of the surface (i.e., troughs) during a redistribution process.
  • a silicon-containing surface with a surface roughness of about 6 nm root mean square (RMS) or more may be transformed into a much smoother surface with a surface roughness of less than about 0.1 nm RMS.
  • a method for etching a silicon-containing surface which includes removing silicon-containing material at a fast rate in order to form a recess in a source/drain (S/D) area on a substrate.
  • a substrate is placed into a process chamber and heated to a temperature within a range from about 500 0 C to about 800 0 C. While the substrate is heated, the silicon- containing surface is exposed to an etching gas containing an etchant and a carrier gas. Chlorine gas may be selected as an etchant used during a fast etch rate process that usually contains no silicon sources or a low concentration of a silicon source. The silicon source may be added to the etching gas to have additional control of the removal rate.
  • a process chamber is cleaned during a chamber clean process by exposing the interior surfaces of the process chamber to an etching gas to remove particulates and other contaminants.
  • the interior surfaces usually contain a silicon-containing material (e.g., quartz) that may be damaged during an etchant clean process. Therefore, besides an etchant and a carrier gas, the etching gas may further contain a silicon source to counter act any over-etching caused by the etchant.
  • a chamber clean gas contains chlorine gas and silane.
  • a carrier gas such as nitrogen, may be combined with the etchant, the silicon source, or both.
  • the process chamber is heated to a higher temperature during a chamber clean process than during either a slow etch process or a fast etch process.
  • the process chamber may be heated to a temperature within a range from about 700 0 C to about 1 ,000 0 C during a chamber clean process.
  • a method for forming a silicon-containing material on a substrate surface includes positioning a substrate containing a silicon material within a process chamber, and exposing the substrate to an etching gas containing chlorine gas and silane during an etching process.
  • the method may further provide exposing the substrate to a deposition gas containing the chlorine gas and the silane during an epitaxial deposition process, removing the substrate from the process chamber, and exposing the process chamber to a chamber clean gas containing the chlorine gas and the silane during a chamber clean process.
  • the silicon material is removed during the etching process at a rate of about 100 A/min or less, preferably, at the rate of about 10 A/min or less, and more preferably, at the rate of about 2 A/min or less. In another example, the silicon material is removed during the etching process at a rate greater than 100 A/min, preferably, at a rate within a range from about 200 A/min to about 1 ,000 A/min.
  • a method for etching a silicon-containing monocrystalline material on a substrate having at least a second material includes positioning a substrate within a process chamber, exposing the substrate to an etching gas containing chlorine gas and a carrier gas, removing a predetermined thickness of the silicon-containing monocrystalline material to form an exposed monocrystalline surface, and depositing an epitaxy layer on the exposed monocrystalline surface within the process chamber.
  • the etching gas may include a silicon source, such as silane, disilane, dichlorosilane, tetrachlorosilane, hexachlorodisilane, a derivative thereof, or a combination thereof and the carrier gas may include nitrogen, argon, helium, or a combination thereof.
  • the process chamber is heated at a temperature within a range from about 500°C to about 700°C and pressurized at a pressure within a range from about 10 Torr to about 750 Torr.
  • the monocrystalline material may be removed at a rate within a range from about 200 A per minute to about 1 ,000 A per minute to form a recess formation within a source/drain area on the substrate.
  • the source/drain area may be used within a CMOS, Bipolar, BiCMOS, or a similar device.
  • the epitaxial layer usually contains silicon, silicon-germanium, silicon-carbon, silicon-germanium- carbon, a derivative thereof, or a combination thereof.
  • a method for forming a silicon-containing monocrystalline material on a substrate includes exposing a substrate to a HF-last wet clean process, positioning the substrate within a process chamber, exposing the substrate to an etching gas comprising chlorine gas and a carrier gas, and removing a predetermined thickness of the silicon-containing monocrystalline material to form an exposed monocrystalline surface.
  • the method may further provide depositing an epitaxy layer on the exposed monocrystalline surface in the process chamber, and cleaning the process chamber with the chlorine gas to remove silicon-containing contaminant adhered thereon.
  • the epitaxy layer may be deposited by a deposition gas containing chlorine gas and the carrier gas may be nitrogen. In one example, nitrogen and chlorine-gas are co-flowed during the process chamber clean step.
  • Figure 1 is a flow chart depicting a process for treating a silicon-containing material by one embodiment described herein;
  • Figures 2A-2C show schematic illustrations of a substrate at different stages during a process described herein;
  • Figure 3 is a flow chart depicting a process for treating a silicon-containing material by another embodiment described herein;
  • Figures 4A-4C show schematic illustrations of another substrate at different stages during a process described herein.
  • Figure 5 is a flow chart depicting a process for fabricating substrates and thereafter cleaning the process chamber by another embodiment described herein.
  • Embodiments of the invention provide processes for etching and depositing silicon-containing materials on substrate surfaces.
  • a slow etch process e.g., ⁇ 100 A/min
  • fast etch process ⁇ e.g., >100 A/min
  • the process chamber is exposed to an etching gas during a chamber clean step for removing deposits or contaminants from the interior surfaces.
  • a process chamber is cleaned during a chamber clean process by exposing the interior surfaces of the process chamber to an etching gas to remove particulates and other contaminants.
  • a slow etch process ⁇ e.g., ⁇ 100 A/min may be conducted to remove contaminants and surface irregularities, such as roughness, from a substrate surface.
  • the substrate surface may be etched to expose an underlayer free or substantially free of contaminants.
  • material of the substrate surface may be redistributed to minimize or remove peaks and troughs that attribute to surface irregularities.
  • the substrate is exposed to an etching gas containing an etchant, a silicon source, and an optional carrier gas.
  • the overall reaction may be controlled in part by manipulating the relative flow rates of the etchant and the silicon source, using a specific etchant source and a silicon source and by adjusting the temperature and the pressure.
  • the substrate may be exposed to a pre-treatment process to prepare the substrate surface for the subsequent etching process.
  • a pre-treatment process may include a wet clean process, such as a HF-last process, a plasma clean, an acid wash process, or combinations thereof.
  • the substrate is treated with a HF-last wet clean process by exposing the surface to a hydrofluoric acid solution ⁇ e.g., about 0.5 wt% HF in water) for a duration of about 2 minutes.
  • Figure 1 illustrates a flow chart depicting process 100 for removing contaminants 212 and rough areas 218 from substrate 200 that is graphically illustrated by Figure 2A.
  • Substrate 200 contains silicon-containing layer 205 and surface 210. Contaminants 212 and rough areas 218 are contained on and in surface 210. Rough areas 218 may be formed by peaks 216 and troughs 214 within surface 210.
  • a predetermined thickness 220 of material from silicon-containing layer 205 may be removed during the slow etch process to reveal exposed surface 230 ( Figure 2B).
  • layer 240 may be formed on exposed surface 230 during an optional deposition process ( Figure 2C).
  • layer 240 contains a silicon-containing material deposited by an epitaxy deposition process.
  • Embodiments of the invention provide processes to etch and deposit silicon-containing materials on various substrates surfaces and substrates, such as substrates 200 and 400 and layers 205 and 405 ( Figures 2A-2C and 4A-4C)
  • substrates 200 and 400 and layers 205 and 405 Figures 2A-2C and 4A-4C
  • a "substrate” or “substrate surface” as used herein refers to any substrate or material surface formed on a substrate upon which film processing is performed.
  • a substrate surface on which processing may be performed include materials such as silicon, silicon-containing materials, silicon oxide, strained silicon, silicon on insulator (SOI), fluorine-doped silicate glass (FSG), carbon doped silicon oxides, silicon nitride, doped silicon, silicon germanium, silicon germanium carbon, germanium, silicon carbon, gallium arsenide, glass, sapphire, or other materials depending on the application.
  • a substrate surface may also include dielectric materials such as silicon dioxide, silicon nitride, silicon oxynitride, and/or carbon doped silicon oxides.
  • Substrates may have various dimensions, such as 200 mm or 300 mm diameter round wafers, as well as, rectangular or square panes.
  • Embodiments of the processes described herein etch and deposit on many substrates and surfaces, especially, silicon and silicon-containing materials.
  • Substrates on which embodiments of the invention may be useful include, but are not limited to semiconductor wafers, such as crystalline silicon ⁇ e.g., Si ⁇ 100> or Si ⁇ 111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers silicon nitride, and patterned or non- patterned wafers.
  • silicon-containing materials, compounds, films or layers should be construed to include a composition containing at least silicon and may contain germanium, carbon, boron, arsenic, phosphorous gallium and/or aluminum. Other elements, such as metals, halogens or hydrogen may be incorporated within a silicon-containing material, compound, film or layer, usually with concentrations of about part per million (ppm).
  • Compounds or alloys of silicon-containing materials may be represented by an abbreviation, such as Si for silicon, SiGe, for silicon germanium, SiC for silicon carbon and SiGeC for silicon germanium carbon. The abbreviations do not represent chemical equations with stoichiometrical relationships, nor represent any particular reduction/oxidation state of the silicon-containing materials. Silicon-containing materials, compounds, films, or layers may include substrates or substrate surfaces.
  • Contaminants 212 on surface 210 include organic residues, carbon, oxides, nitrides, halides ⁇ e.g., fluorides or chlorides), or combinations thereof.
  • surface 210 may contain a layer of silicon oxide after being exposed to the ambient air or may contain a layer of silicon fluoride after being treated with a HF- last wet clean process.
  • Surface 210 may also contain irregularities or regional areas of roughness, such as troughs 214 and peaks 216 within rough areas 218.
  • Substrate 200 may be positioned within a process chamber and heated to a predetermined temperature (step 110).
  • the substrate and the process chamber may be heated completely or a portion thereof to temperature within a range from about 300 0 C to about 800 0 C, preferably, from about 500 0 C to about 700 0 C, and more preferably, from about 550 0 C to about 650°C.
  • the process chamber may be maintained at a pressure within a range from about 1 mTorr to about 760 Torr, preferably, from about 0.1 Torr to about 500 Torr, and more preferably, from about 1 Torr to about 100 Torr.
  • a cold wall reactor is used as a process chamber for processes conducted at lower temperatures.
  • a cold wall reactor may provide temperature control of each independent portion within the reactor, such as reactor walls, reactor dome and substrate susceptor.
  • the reactor dome may be formed from quartz.
  • the cold wall reactor may have reactor walls maintained at a temperature less than about 400 0 C, preferably, less than about 200 0 C, and more preferably, less than about 150 0 C, a reactor dome maintained at a temperature within a range from about 300 0 C to about 800 0 C, preferably, from about 400 0 C to about 700 0 C, and more preferably, from about 500 0 C to about 600 0 C, and a substrate susceptor maintained at a temperature within a range from about 300 0 C to about 800 0 C, preferably, from about 500 0 C to about 700 0 C, and more preferably, from about 550 0 C to about 650 0 C.
  • the etching gas used during the slow etch process contains an etchant, a silicon source and an optional carrier gas.
  • the etchant, the silicon source and the carrier gas may be premixed, co-flowed or independently flowed into the process chamber.
  • the etchant and a carrier gas are either co-flowed or combined together as a gas mixture
  • the silicon source and a carrier gas are either co-flowed or combined together as a gas mixture and the two gas mixtures may be co-flowed together prior to entering the process chamber.
  • a gas mixture of chlorine and nitrogen may be co-flowed into the process chamber with a mixture of silane and nitrogen.
  • a gas mixture of chlorine and nitrogen may be co-flowed into the process chamber with a mixture of silane and hydrogen.
  • the etchant is chlorine gas (Cl 2 ).
  • Cl 2 chlorine gas
  • the silicon source may be administered simultaneously with the etchant in order to counter act any over-etching of susceptible surfaces on substrate 200.
  • the silicon source is used to deposit silicon on the silicon-containing layer while the etchant removes the silicon-containing material.
  • the rates at which the etchant and the silicon source are exposed to the substrate are adjusted so that the overall reaction favors material removal and/or material redistribution. Therefore, the overall reaction is removing or redistributing silicon-containing material and the etch rate may be finely controlled to several angstroms per minute.
  • the etchant is usually administered into the process chamber at a rate within a range from about 1 standard cubic centimeters per minute (seem) to about 1 standard liters per minute (slm), preferably, from about 5 seem to about 150 seem, and more preferably, from about 10 seem to about 30 seem, for example, about 20 seem. While chlorine is the preferred etchant, other etchants that may be used solely or in combination include chlorine trifluoride (CIF 3 ), tetrachlorosilane (SiCI 4 ), or a derivative thereof.
  • CIF 3 chlorine trifluoride
  • SiCI 4 tetrachlorosilane
  • the silicon source is usually provided into the process chamber for slow etch processes at a rate within a range from about 5 seem to about 500 seem, preferably, from about 10 seem to about 100 seem, and more preferably, from about 20 seem to about 80 seem, for example, about 50 seem.
  • Silicon sources that may be used in the etching include silanes, halogenated silanes, organosilanes, or derivatives thereof.
  • Silanes include silane (SiH 4 ) and higher silanes with the empirical formula Si x H(2x + 2), such as disilane (SJaH 6 ), trisilane (Si 3 H 8 ), and tetrasilane (Si 4 Hi 0 ), as well as others.
  • Halogenated silanes include compounds with the empirical formula X'ySi ⁇ H( 2 ⁇ + 2-y), where X' is independently selected from F, Cl, Br, or I, such as hexachlorodisilane (Si 2 CI 6 ), tetrachlorosilane (SiCI 4 ), trichlorosilane (CI 3 SiH), dichlorosilane (CI 2 SiH 2 ) and chlorosilane (CISiH 3 ).
  • Organosilanes include compounds with the empirical formula R y Si x H (2x+2-y) , where R is independently selected from methyl, ethyl, propyl or butyl, such as methylsilane ((CH 3 )SiH 3 ), dimethylsilane ((CH 3 ) 2 SiH 2 ), ethylsilane ((CH 3 CH 2 )SiH 3 ), methyldisilane ((CH 3 )Si 2 H 5 ), dimethyldisilane ((CH 3 ) 2 Si 2 H 4 ), and hexamethyldisilane ((CH 3 ) 6 Si 2 ).
  • the preferred silicon sources may include silane, dichlorosilane, or disilane.
  • the carrier gas is usually provided into the process chamber at a flow rate within a range from about 1 slm to about 100 slm, preferably, from about 5 slm to about 80 slm, and more preferably, from about 10 slm to about 40 slm, for example, about 20 slm.
  • Carrier gases may include nitrogen (N 2 ), hydrogen (H 2 ), argon, helium, or combinations thereof.
  • an inert carrier gas is preferred and includes nitrogen, argon, helium, or combinations thereof.
  • a carrier gas may be selected based on the precursor(s) used and/or the process temperature of the slow etch process of step 120.
  • nitrogen is utilized as a carrier gas in embodiments featuring low temperature ⁇ e.g., ⁇ 800°C) processes.
  • Low temperature processes are accessible due in part to the use of chlorine gas in the etching process. Nitrogen remains inert during low temperature etching processes. Therefore, nitrogen is not incorporated into the silicon-containing materials on the substrate during low temperature processes.
  • a nitrogen carrier gas does not form hydrogen- terminated surfaces as does a hydrogen carrier gas. The hydrogen-terminated surfaces formed by the adsorption of hydrogen carrier gas on the substrate surface inhibit the growth rate of subsequently deposited silicon-containing layers.
  • the low temperature processes may take economic advantage of nitrogen as a carrier gas, since nitrogen is far less expensive than hydrogen, argon, or helium.
  • chlorine is the etchant
  • silane is the silicon source
  • nitrogen is the carrier gas.
  • Substrate 200 and surface 210 may be exposed to a slow etch gas to remove a predetermined thickness 220 of silicon-containing layer 205 during step 120 ( Figures 2A-2B).
  • Surface 210 is etched during the removal of the predetermined thickness 220.
  • the slow etch gas is exposed to substrate 200 for a time period within a range from about 5 seconds to about 5 minutes, preferably, from about 30 seconds to about 2 minutes. The amount of time is adjusted relative to the etch rate used in a particular process.
  • the etch rate of a slow etch process is usually less than about 100 A/min, preferably, less than about 50 A/min.
  • the slow etch rate is within a range from about 2 A/min to about 20 A/min, preferably, from about 5 A/min to about 15 A/min, for example, about 10 A/min. In another embodiment, the etch rate is about 2 A/min or less, preferably, about 1 A/min or less, and more preferably, approaches a redistribution of material on the substrate such that the net removal rate is non-measurable relative to the thickness of the layer.
  • material of silicon-containing layer 205 may be removed from peaks 216 and added to troughs 214 within surface 210 to form exposed surface 230. Troughs 214 may be filled by the material derived from peaks 216 and/or virgin material being produced by the introduction of precursors (e.g., silicon source) within the slow etch gas.
  • a slow etch process may be utilized to reduce the surface roughness on substrate 200.
  • surface 210 with a surface roughness of about 6 nm root mean square (RMS) or more may be exposed to a slow etch gas to remove material from silicon-containing layer 205 by predetermined thickness 220 to reveal exposed surface 230.
  • Exposed surface 230 may have a surface roughness of about
  • Exposed surface 230 is usually free or substantially free of contaminants that include organic residues, carbon, oxides, nitrides, halides (e.g., fluorides or chlorides), or combinations thereof.
  • An optional purge process may be performed within the process chamber during step 125 ( Figure 1 ).
  • the purge process helps remove residual etch gas from substrate 200, which in turn enhances the growth during the subsequent deposition process (step 130).
  • the process chamber may have an internal pressure within a range from about 0.1 mTorr to about 100 Torr, preferably, from about 1.0 mTorr to about 10 Torr, and more preferably, from about 10.0 mTorr to about 1 Torr.
  • the purge process may be conducted for a time period within a range from about 30 seconds to about 10 minutes, preferably, from about 1 minute to about 5 minutes, and more preferably, from about 2 minutes to about 4 minutes.
  • a purge gas may be administered anytime during the purge process.
  • a purge gas may include nitrogen, hydrogen, argon, helium, forming gas, or combination thereof.
  • Layer 240 may be deposited on exposed surface 230 during step 130.
  • layer 240 is a silicon-containing material that may be selectively and epitaxially grown or deposited on exposed surface 230 by a chemical vapor deposition (CVD) process.
  • CVD chemical vapor deposition
  • Chemical vapor deposition processes include many techniques, such as atomic layer epitaxy (ALE), atomic layer deposition (ALD), plasma-assisted CVD (PA-CVD) or plasma-enhanced CVD (PE- CVD), plasma-assisted ALD (PA-ALD) or plasma-enhanced ALD (PE-ALD), atomic layer CVD (ALCVD), organometallic or metal-organic CVD (MOCVD or OMCVD), laser-assisted CVD (LA-CVD), ultraviolet CVD (UV-CVD), hot-wire (HWCVD), reduced-pressure CVD (RP-CVD), ultra-high vacuum CVD (UHV-CVD), derivatives thereof, or combinations thereof.
  • ALE atomic layer epitaxy
  • ALD plasma-assisted CVD
  • PE-CVD plasma-assisted ALD
  • PA-ALD plasma-assisted ALD
  • PE-ALD plasma-enhanced ALD
  • PE-ALD plasma-enhanced
  • the deposition gas used during step 130 may also contain at least one secondary elemental source, such as a germanium source and/or a carbon source.
  • the germanium source may be added to the process chamber with the silicon source, etchant and carrier gas to form a silicon-containing compound. Therefore, the silicon-containing compound may contain silicon, SiGe, SiC, SiGeC, doped variants thereof, or combinations thereof.
  • Germanium and/or carbon may be added to the silicon-containing material by including germanium source ⁇ e.g., germane), or a carbon source ⁇ e.g., methylsilane) during the deposition process.
  • the silicon-containing compound may also contain dopants by including a boron source ⁇ e.g., diborane), an arsenic source ⁇ e.g., arsine), or a phosphorous source ⁇ e.g., phosphine) during or after the deposition process.
  • the dopant may be included within the silicon source, etchant and carrier gas to form a silicon- containing compound.
  • the dopant may be added to the silicon- containing material by exposing the substrate to an ion implantation process.
  • a CVD process called alternating gas supply may be used to epitaxially grow or deposit a silicon-containing compound as layer 240 on exposed surface 230.
  • the AGS deposition process includes a cycle of alternating exposures of silicon-sources and etchants to the substrate surface.
  • An AGS deposition process is further disclosed in commonly assigned and co-pending United States Serial No. 11/001 ,774, filed December 1 , 2004, entitled "Selective Epitaxy Process with Alternating Gas Supply,” which is incorporated herein by reference in its entirety for the purpose of describing an AGS process.
  • Process 100 may be used to etch and deposit silicon-containing materials within the same process chamber.
  • the slow etch process (step 120) and the subsequent deposition process (step 130) are performed within the same process chamber to improve throughput, be more efficient, decrease probability of contamination and benefit process synergies, such as common chemical precursors.
  • a slow etch process and a deposition process each utilize the same silicon source, the same etchant and the same carrier gas.
  • an etch gas for a slow etch process may contain silane, chlorine, and nitrogen
  • a deposition gas for a selective, epitaxial deposition process may also contain silane, chlorine, and nitrogen.
  • the concentration ratio of the silicon source and the reductant may be adjusted during the overall process to encourage a particular step.
  • the concentration ratio of the silicon source and the reductant is increased to promote a deposition step.
  • the concentration ratio of the silicon source and the reductant is decreased to promote an etch step.
  • a fast etch process ⁇ e.g., >100 A/min
  • the fast etch process is a selective etch process to remove silicon-Gontaining material while leaving barrier material unscathed.
  • Barrier materials may include silicon nitride, silicon oxide, or silicon oxynitride used as spacers, capping layers, or mask materials.
  • Figure 3 illustrates a flow chart depicting process 300 is initiated by positioning the substrate into a process chamber and adjusting the process parameters during step 310.
  • the substrate and the process chamber may be heated completely or a portion thereof to a temperature within a range from about 400°C to about 800°C, preferably, from about 500 0 C to about 700°C, and more preferably, from about 550 0 C to about 650 0 C.
  • the process chamber is maintained at a pressure within a range from about 1 Torr to about 760 Torr, preferably, from about 0.1 Torr to about 500 Torr, and more preferably, from about 1 Torr to about 100 Torr.
  • the etching gas used during the fast etch process contains an etchant, a carrier gas and an optional silicon source (step 320).
  • the etching gas contains chlorine, nitrogen, and silane.
  • the etchant may be provided into the process chamber gas at a rate within a range from about 1 seem to about 100 seem, preferably from about 5 seem to about 50 seem, and more preferably, from about 10 seem to about 30 seem, for example, about 20 seem. While chlorine is the preferred etchant during a fast etch process, other etchants that may be used solely or in combination include chlorine trifluoride, tetrachlorosilane, or a derivative thereof.
  • the carrier gas is usually provided into the process chamber at a flow rate within a range from about 1 slm to about 100 slm, preferably, from about 5 slm to about 80 slm, and more preferably, from about 10 slm to about 40 slm, for example, about 20 slm.
  • Carrier gases may include nitrogen, hydrogen, argon, helium, or combinations thereof.
  • an inert carrier gas is preferred and includes nitrogen, argon, helium, or combinations thereof.
  • a carrier gas may be selected based on the precursor(s) used and/or the process temperature during the etching process of step 320.
  • nitrogen is used as a carrier gas during embodiments featuring low temperature ⁇ e.g., ⁇ 800°C) processes.
  • an etching gas for a first etch process contains chlorine and nitrogen.
  • a silicon source may be optionally added to the etching gas for providing additional control of the etch rate during a fast etch process.
  • the silicon source may be delivered into the process chamber at a rate within a range from about 5 seem to about 500 seem, preferably, from about 10 seem to about 100 seem, and more preferably, from about 20 seem to about 80 seem, for example, about 50 seem.
  • the etching gas may contain a silicon source, such as silanes, halogenated silanes, organosilanes, or derivatives thereof, as described herein.
  • Substrate 400 contains at least one film stack feature 410 (Fig 4A).
  • Silicon-containing layer 405 may be a doped or undoped, bare silicon substrate or include a silicon-containing layer disposed thereon.
  • Film stack feature 410 includes gate layer 412 on gate oxide layer 414 surrounded by spacers 416 and protective capping layer 418.
  • gate layer 412 is composed of a polysilicon and gate oxide layer 414 is composed of silicon dioxide, silicon oxynitride, or hafnium oxide.
  • a spacer 416 which is usually an isolation material containing silicon oxide, silicon nitride, silicon oxynitride, derivatives thereof, or combinations thereof.
  • spacer 416 is a nitride/oxide stack ⁇ e.g., Si 3 N 4 ZSiO 2 ZSi 3 N 4 ).
  • Gate layer 412 may optionally have a protective capping layer 418 adhered thereon.
  • substrate 400 is exposed to an etching gas to remove a predetermined thickness 425 of silicon-containing layer 405 and form a recess 430, as depicted in Figure 4B.
  • the etching gas is exposed to substrate 400 for a time period within a range from about 10 seconds to about 5 minutes, preferably, from about 1 minute to about 3 minutes. The amount of time is adjusted relative to the etch rate used in a particular process.
  • the etch rate of a fast etch process is usually faster than about 100 A/min, preferably, faster than about 200 A/min, such as at a rate within a range from about 200 A/min to about 1 ,500 A/min, preferably, from about 200 A/min to about 1 ,000 A/min, for example, about 600 A/min.
  • the etching process may be kept at a fast rate to remove the predetermined thickness 425, and then reduced to a slow rate process to smooth the remaining surface.
  • the reduced etching rate may be controlled by a slow etching process described by process 100.
  • An optional purge process may be performed within the process chamber during step 325.
  • the purge process helps remove residual etch gas from substrate 400, which in turn enhances the growth during the subsequent deposition process (step 330).
  • the process chamber may have an internal pressure within a range from about 0.1 mTorr to about 100 Torr, preferably, from about 1.0 mTorr to about 10 Torr, and more preferably, from about 10.0 mTorr to about 1 Torr.
  • the purge process may be conducted for a time period within a range from about 30 seconds to about 10 minutes, preferably, from about 1 minute to about 5 minutes, and more preferably, from about 2 minutes to about 4 minutes. Generally, all of the gas entering the process chamber may be turned off. However, in an alternative aspect, a purge gas may be administered into the process chamber anytime during the purge process.
  • layer 440 may be deposited during step 330 ( Figure 4C).
  • layer 440 is a silicon-containing material that may be selectively and epitaxially deposited on the exposed surface of recess 430 a CVD process.
  • the CVD process includes an AGS deposition technique.
  • recess 430 may be exposed to another fabrication process prior to the deposition of layer 440, such as a doping process.
  • a doping process includes ion implantation, in which a dopant ⁇ e.g., boron, phosphorous, or arsenic) may be implanted into the surface of the recess 430.
  • Process 300 may be used to etch and deposit silicon-containing materials in the same process chamber.
  • the fast etch process and the subsequent deposition is performed in the same process chamber to improve throughput; be more efficient, decrease probability of contamination and benefit process synergies, such as common chemical precursors.
  • both the fast etch process and the selective, epitaxial deposition process of a silicon-containing compound use chlorine as an etchant and nitrogen as a carrier gas.
  • FIG. 5 illustrates an alternative embodiment of the invention that includes cleaning the process chamber after finishing fabrication techniques during process 500.
  • the substrate may be exposed to a pre-treatment process that includes a wet clean process, a HF-last process, a plasma clean, an acid wash process, or combinations thereof (step 510).
  • a pre-treatment process that includes a wet clean process, a HF-last process, a plasma clean, an acid wash process, or combinations thereof
  • the substrate may have to remain outside the controlled environment of the process chamber for a period of time called queue time (Q-time).
  • Q-time in an ambient environment may last about 2 hours or more, usually, the Q-time last much longer, such as a predetermined time with a range from about 6 hours to about 24 hours or longer, such as about 36 hours.
  • a silicon oxide layer usually forms on the substrate surface during the Q-time due to the substrate being exposed to ambient water and oxygen.
  • the substrate is positioned into a process chamber and exposed to an etching process as described herein.
  • the etching process may be a slow etch process as described in step 120, a fast etch process as described in step 320 or both.
  • the etching process removes a pre-determined thickness of silicon- containing layer from the substrate to form an exposed silicon-containing layer.
  • an optional purge process may be performed within the process chamber (step 525).
  • a secondary material is deposited on the exposed silicon-containing layer (step 530).
  • the secondary material is in a selective, epitaxially deposited silicon-containing compound.
  • the deposition process may include the processes as described during steps 130 and 330. In one embodiment, processes 100 and 300 may be used during steps 520 and 530.
  • a chamber clean process is conducted inside the process chamber to remove various contaminants therein (step 540).
  • Etch processes and deposition processes may form deposits or contaminants on surfaces within the process chamber.
  • the deposits include silicon-containing materials adhered to the walls and other inner surfaces of the process chamber. Therefore, a chamber clean process may be used to remove contaminants while not damaging interior surfaces of the process chamber.
  • the substrate is first exposed to a HF-last process.
  • the substrate is placed into a process chamber and exposed to an etch process that contains chlorine and nitrogen at about 600 0 C. Thereafter, the process chamber is exposed to a purge process.
  • a silicon-containing layer is epitaxially deposited on the substrate by a deposition process utilizing chlorine and nitrogen at about 625°C within the same process chamber.
  • the substrate is removed and the process chamber is heated to about 675°C and exposed to a cleaning gas containing chlorine and nitrogen.
  • the etchant and the carrier gas are the same gases used during steps 520 and 540.
  • a chamber clean gas containing a silicon source may be used to remove various contaminants from inside a process chamber during a chamber clean process, such as step 540.
  • the interior surfaces of the process chamber usually contain a silicon-containing material ⁇ e.g., quartz) that may be damaged during a traditional etchant clean process. Therefore, besides an etchant and a carrier gas, the chamber clean gas may further contain a silicon source to counter act any over-etching caused by the etchant.
  • the process chamber may contain an interior surface or components having a surface that is chemically vulnerable to an etchant. Also, the interior surface or componential part within the process chamber may have a protective coating that is vulnerable to an etchant.
  • these interior surface within the process chamber may contain a silicon-containing surface, such as quartz, silicon oxide, silicon carbide, silicon carbide coated graphite, sapphire, suicide coatings, derivatives thereof, or combinations thereof.
  • the interior surface is a metal-containing surface within the process chamber, such as steel, stainless steel, iron, nickel, chromium, aluminum, alloys thereof, or combinations thereof.
  • the interior surfaces may be on the interior of the walls, floor, and lid of the chamber, as well as internal components or portions thereof, such as a susceptor, a linear, an upper dome, a lower dome, a preheat ring, a showerhead, a dispersion plate, a probe, or the like.
  • the cleaning process includes heating the substrate susceptor to a temperature within a range from about 600 0 C to about 1 ,200°C, preferably, from about 650°C to about 1 ,000 0 C, and more preferably, from about 700 0 C to about 900 0 C, for example, about 800 0 C.
  • the process chamber may have an internal pressure within a range from about 1 mTorr to about 760 Torr, preferably, from about 100 mTorr to about 750 Torr, and more preferably, from about 100 Torr to about 700 Torr, for example, 600 Torr.
  • a cold wall reactor is used as a process chamber and may have reactor walls maintained at a temperature less than about 400 0 C, preferably, less than about 200 0 C, and more preferably, less than about 150 0 C and a quartz reactor dome maintained at a temperature within a range from about 300 0 C to about 800°C, preferably, from about 400 0 C to about 700 0 C, and more preferably, from about 500 0 C to about 600 0 C.
  • the cleaning process is conducted for a time period within a range from about 30 seconds to about 10 minutes, preferably, from about 1 minute to about 5 minutes, and more preferably, from about 2 minutes to about 4 minutes.
  • a chamber cleaning gas may contain an etchant, a silicon source and a carrier gas.
  • the etchant, the silicon source and the carrier gas used during the chamber cleaning process are the same gases used during a previous fabrication step, such as a slow etch process or a fast etch process.
  • the etchant may be provided into the process chamber during the chamber clean process at a rate within a range from about 10 seem to about 100 slm, preferably, from about 100 seem to about 5 slm.
  • the etchant has a flow rate of about 5 slm, preferably, about 10 slm, and more preferably, about 20 slm. In another example, the etchant has a flow rate of about 50 seem, preferably, about 130 seem, and more preferably, about 1 ,000 seem.
  • Etchants that may be used within the cleaning gas include chlorine, chlorine trifluoride, tetrachlorosilane, hexachlorodisilane, or derivatives thereof.
  • the silicon source may be provided into the process chamber during the chamber clean process at a rate within a range from about 10 seem to about 100 slm, preferably, from about 100 seem to about 5 slm.
  • the silicon source has a flow rate of about 5 slm, preferably, about 10 slm, and more preferably, about 20 slm.
  • the silicon source has a flow rate of about 50 seem, preferably, about 130 seem, and more preferably, about 1 ,000 seem.
  • Silicon sources that may be used in the etching include silanes, halogenated silanes, organosilanes or derivatives thereof.
  • Silanes include silane (SiH 4 ) and higher silanes with the empirical formula Si x H( 2 ⁇ + 2), such as disilane (Si 2 H 6 ), trisilane (SJsH 8 ), and tetrasilane (Si 4 Hi 0 ), as well as others.
  • Halogenated silanes include compounds with the empirical formula X'ySi ⁇ H( 2 ⁇ +2 -y), where X 1 is independently selected from F, Cl, Br or I, such as hexachlorodisilane (Si 2 CI 6 ), tetrachlorosilane (SiCI 4 ), trichlorosilane (CI 3 SiH), dichlorosilane (CI 2 SiH 2 ), and chlorosilane (CISiH 3 ).
  • X 1 is independently selected from F, Cl, Br or I, such as hexachlorodisilane (Si 2 CI 6 ), tetrachlorosilane (SiCI 4 ), trichlorosilane (CI 3 SiH), dichlorosilane (CI 2 SiH 2 ), and chlorosilane (CISiH 3 ).
  • Organosilanes include compounds with the empirical formula R y Si x H (2x+2-y) , where R is independently selected from methyl, ethyl, propyl or butyl, such as methylsilane ((CH 3 )SiH 3 ), dimethylsilane ((CHs) 2 SiH 2 ), ethylsilane ((CH 3 CH 2 )SiH 3 ), methyldisilane ((CH 3 )Si 2 H 5 ), dimethyldisilane ((CHs) 2 Si 2 H 4 ), and hexamethyldisilane ((CHs) 6 Si 2 ).
  • Preferred silicon sources may include silane, dichlorosilane, or disilane.
  • the carrier gas may be provided into the process chamber during the chamber clean process at a rate within a range from about 100 seem to about 100 slm.
  • the carrier gas has a flow rate of about 20 slm, preferably, about 50 slm, and more preferably, about 100 slm.
  • the carrier gas has a flow rate of about 100 seem, preferably, about 1 slm, and more preferably, about 10 slm.
  • Carrier gases may include nitrogen, hydrogen, forming gas, argon, helium or combinations thereof.
  • a chamber clean gas contains chlorine gas, silane and a carrier gas, such as nitrogen.
  • a chamber clean process that may be used within embodiments of the invention described herein is further disclosed in commonly assigned U.S. Patent No. 6,042,654, which is incorporated herein by reference in its entirety.
  • the chamber clean process may be repeated after processing each individual substrate or after multiple substrates. In one example, the chamber clean process is conducted after processing every 25 substrates. In another example, the chamber clean process is conducted after processing every 5 substrates. In another example, the chamber clean process is conducted after processing every 100 substrates. Although a substrate may remain in the process chamber during the chamber clean process, preferably, the substrate is removed and the process is performed on an empty chamber.
  • Embodiments, as described herein, provide processes that may be utilized during fabrication processes for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and bipolar transistors, such as Bipolar device fabrication ⁇ e.g., base, emitter, collector, and emitter contact), BiCMOS device fabrication (e.g., base, emitter, collector, emitter contact), and CMOS device fabrication (e.g., channel, source/drain, source/drain extension, elevated source/drain, substrate, strained silicon, silicon on insulator, and contact plug).
  • Other embodiments provide processes that may be utilized during gate fabrication processes, base contact fabrication processes, collector contact fabrication processes, emitter contact fabrication processes, or elevated source/drain fabrication processes.
  • the processes of the invention may be conducted on fabrication equipment used for ALE, CVD 1 and ALD processes.
  • a system that may be used to etch or deposit the silicon-containing films as described herein include the Epi Centura ® system or the Poly Gen ® system, both available from Applied Materials, Inc., located in Santa Clara, California.
  • a process chamber useful to etch and deposit as described herein is further disclosed in commonly assigned U.S. Patent No. 6,562,720, which is incorporated herein by reference in its entirety for the purpose of describing the apparatus.
  • Other enabling apparatuses include batch furnaces and high-temperature furnaces.
  • Example 1 - Pre-clean process comparative without silane A substrate was exposed to an HF-last process to form a fluoride terminated surface. The substrate was placed in the process chamber and heated to about 600°C while the pressure was maintained at about 20 Torr. The substrate was exposed to an etching gas containing N 2 at a flow rate of about 20 slm and Cl 2 at flow rate of about 120 seem. The surface was etched at a rate of about 500 A/min.
  • Example 2 - Pre-clean process with silane A substrate was exposed to an HF-last process to form a fluoride terminated surface. The substrate was placed in the process chamber and heated to about 600°C while the pressure was maintained at about 20 Torr. The substrate was exposed to an etching gas containing N 2 at a flow rate of about 20 slm, Cl 2 at flow rate of about 20 seem and SiH 4 at a flow rate of about 50 seem. The surface was etched at a rate of about 10 A/min. Therefore, the addition of a silicon source, such as silane in Example 2, reduced the etch rate of the silicon-containing layer by about 50 times as compared to the etch rate in Example 1.
  • a silicon source such as silane in Example 2
  • Example 3 Smoothing process comparative without silane: A substrate surface containing a silicon-containing layer was cleaved forming a surface with a roughness of about 5.5 nm root mean square (RMS). The substrate was placed in the process chamber and heated to about 650°C while the pressure was maintained at about 200 Torr. The substrate was exposed to an etching gas containing N 2 at a flow rate of about 20 slm and Cl 2 at flow rate of about 20 seem. The surface was etched at a rate of about 200 A/min.
  • Example 4 Smoothing process with silane: A substrate surface containing a silicon-containing layer was cleaved forming a surface with a roughness of about 5.5 nm root mean square.
  • the substrate was placed in the process chamber and heated to about 650°C while the pressure was maintained at about 200 Torr.
  • the substrate was exposed to an etching gas containing N 2 at a flow rate of about 20 slm, Cl 2 at flow rate of about 20 seem and SiH 4 at a flow rate of about 50 seem.
  • the surface was etched at a rate of about 20 A/min.
  • the surface roughness was reduced to about 0.1 nm RMS. Therefore, the addition of a silicon source, such as silane used in Example 4, reduced the etch rate of the silicon-containing layer by about 10 times as compared to the etch rate in Example 3.
  • Example 5 - Chlorine etch process followed by silicon-epitaxy A silicon substrate contained a series of silicon nitride line features that are about 90 nm tall, about 100 nm wide and about 150 nm apart, baring the silicon surface. The substrate was placed in the process chamber and heated to about 600°C while the pressure was maintained at about 40 Torr. The substrate was exposed to an etching gas containing N 2 at a flow rate of about 20 slm and Cl 2 at flow rate of about 80 seem. The surface was etched at a rate of about 750 A/min. After about 30 seconds, about 35 nm of the silicon surface was etched. The silicon nitride features remain inert to the etching process.
  • the pressure was increased to about 200 Torr and SiH 4 was added to the etching gas at a flow rate of about 50 seem.
  • the etch rate was reduced to about 18 A/min to smooth the freshly etched silicon surface. After about 1 minute, the smooth surface is exposed to a selective epitaxy deposition process by increasing the flow of SiH 4 to about 100 seem and maintaining the flow of N 2 and Cl 2 unchanged.
  • a silicon-containing material was deposited on the silicon surface at a rate of about 25 A/min.
  • Example 6 - Chlorine fast etch process containing silane A silicon substrate contained a series of silicon nitride line features that are about 90 nm tall, about 100 nm wide and about 150 nm apart, baring the silicon surface. The substrate was placed in the process chamber and heated to about 600°C while the pressure was maintained at about 40 Torr. The substrate was exposed to an etching gas containing N 2 at a flow rate of about 20 slm, Cl 2 at flow rate of about 80 sccm and SiH 4 at flow rate of about 40 seem. The surface was etched at a rate of about 400 A/min.
  • Example 7 - Chamber clean process containing chlorine and silane After a silicon epitaxial deposition process, the substrate was removed from the chamber. The process chamber was heated to about 800°C while the pressure was adjusted to about 600 Torr. The process chamber was exposed to an etching gas containing N 2 at a flow rate of about 20 slm, Cl 2 at flow rate of about 2 slm and SiH 4 at flow rate of about 1 slm. The chamber clean process was conducted for about 2 minutes.

Abstract

In one embodiment, a method for treating a silicon-containing surface is provided which includes removing contaminants and/or smoothing the substrate surface by a slow etch process (e.g., about <100 Å/min). The substrate is exposed to an etching gas that contains an etchant and a silicon source. Preferably, the etchant is chlorine gas and the substrate is heated to a temperature of less than about 800°C. In another embodiment, a fast etch process (e.g., about >100 Å/min) is provided which includes removing silicon material while forming a recess within a source/drain (S/D) area on the substrate surface. In another embodiment, a method for cleaning a process chamber is provided which includes exposing the interior surfaces with a chamber clean gas that contains an etchant and a silicon source. The chamber clean process limits the etching of quartz and metal surfaces within the process chamber.

Description

ETCHANT TREATMENT PROCESSES FOR SUBSTRATE SURFACES AND CHAMBER SURFACES
BACKGROUND OF THE INVENTION Field of the Invention
[0001] Embodiments of the invention generally relate to the field of electronic manufacturing processes and devices, more particular, to methods of etching and depositing silicon-containing materials while forming electronic devices.
Description of the Related Art
[0002] Electronic devices such as semiconductor devices are fabricated by an assortment of steps including the deposition and removal of silicon-containing materials. The deposition and. removal steps as well as other process steps may cause the substrate surface containing a silicon-containing material to become rough and/or bare contaminants. Also, particulates and other contaminants accumulate on the interior surfaces within a process chamber during the deposition and removal steps. The particulates may eventually further contaminate the substrate surface. Rough or contaminated substrate surfaces generally lead to poor quality interfaces which provide poor device performance and reliability.
[0003] Etching processes have been developed to combat contaminants and roughness on substrate surfaces. However, the traditional etching processes have some draw backs. Usually, etchants, such as hydrogen chloride (HCI), require a high activation temperature in order to remove silicon-containing materials. Therefore, etching processes are often conducted at temperatures of 1 ,0000C or higher. Such high temperatures are not desirable during a fabrication process due to thermal budget considerations, possible uncontrolled nitridation reactions or over- etching to the substrate surface and loss of economically efficiencies. Etching processes with such extreme conditions may damage interior surfaces within the chamber, such as thermal quartz liners. Chlorine (Cl2) has been used to remove silicon-containing materials during etch processes at lower temperatures than processes that utilize hydrogen chloride etchants. However, chlorine reacts very quickly with silicon-containing materials and thus the etch rate is not easily controllable. Therefore, silicon-containing materials are usually over etched by processes using chlorine gas.
[0004] Also, traditional etching processes generally are conducted in an etching chamber or a thermal processing chamber. Once the etching of the silicon- containing material is complete, the substrate is transferred into a secondary chamber for a subsequent deposition process. Often, the substrate is exposed to the ambient environment between the etching process and the deposition process. The ambient environment may introduce water and/or oxygen to the substrate surface forming an oxide layer.
[0005] Prior to the etching process or the deposition process, a substrate is usually exposed to a pre-treatment process including a wet clean process (e.g., a HF-last process), a plasma clean or an acid wash process. After a pre-treatment process and prior to starting an etching process, the substrate may have to reside outside the process chamber or controlled environment for a period of time called the queue time (Q-time). During the Q-time, the substrate is exposed to ambient environmental conditions that include oxygen and water at atmospheric pressure and room temperature. The ambient exposure forms an oxide layer on the substrate surface, such as silicon oxide. Generally, longer Q-times form thicker oxide layers and therefore more extreme etching processes must be conducted at higher temperatures and pressures to maintain throughput.
[0006] Therefore, there is a need to have an etching process for treating a silicon-containing material on a substrate surface to remove any surface contaminants contained thereon and/or to smooth the substrate surface. There is also a need to be able to treat the substrate surface within a process chamber which could subsequently be used during the next process step, such as to deposit an epitaxy layer. Furthermore, there is a need to maintain the process temperature at a low temperature, such as below 1 ,000°C, and preferably below 800°C, even for substrates that have endured long Q-times {e.g., about 10 hours). Also, there is a need to reduce particulate accumulation on the interior surfaces of a process chamber, while not damaging these interior surfaces.
SUMMARY OF THE INVENTION
[0007] In one embodiment, a method for finishing or treating a silicon-containing surface is provided which includes smoothing the surface and removing contaminants contained on the surface. In one example, a substrate is placed into a process chamber and heated to a temperature within a range from about 5000C to about 7000C. The substrate is exposed to an etching gas containing an etchant, a silicon source and a carrier gas. Chlorine gas (CI2) may be used as the etchant so that a relatively low temperature is used during the etching process. A silicon source is usually provided simultaneously with the etchant in order to counter act any over-etching caused by the etchant. That is, the silicon source is used to deposit silicon on a substrate surface while the etchant removes the silicon. The rates at which the etchant and the silicon source are exposed to the substrate are adjusted so that the overall reaction favors material removal and/or redistribution. Therefore, in one example, the etch rate may be finely controlled (e.g., several angstroms or less per minute) while removing a silicon-containing material during an overall reaction. In another example, silicon-containing material is removed from higher portions of the surface (i.e., peaks) while added to the lower portions of the surface (i.e., troughs) during a redistribution process. A silicon-containing surface with a surface roughness of about 6 nm root mean square (RMS) or more may be transformed into a much smoother surface with a surface roughness of less than about 0.1 nm RMS.
[0008] In another embodiment, a method for etching a silicon-containing surface is provided which includes removing silicon-containing material at a fast rate in order to form a recess in a source/drain (S/D) area on a substrate. In another example, a substrate is placed into a process chamber and heated to a temperature within a range from about 5000C to about 8000C. While the substrate is heated, the silicon- containing surface is exposed to an etching gas containing an etchant and a carrier gas. Chlorine gas may be selected as an etchant used during a fast etch rate process that usually contains no silicon sources or a low concentration of a silicon source. The silicon source may be added to the etching gas to have additional control of the removal rate.
[0009] In another embodiment, a process chamber is cleaned during a chamber clean process by exposing the interior surfaces of the process chamber to an etching gas to remove particulates and other contaminants. The interior surfaces usually contain a silicon-containing material (e.g., quartz) that may be damaged during an etchant clean process. Therefore, besides an etchant and a carrier gas, the etching gas may further contain a silicon source to counter act any over-etching caused by the etchant. In one example, a chamber clean gas contains chlorine gas and silane. A carrier gas, such as nitrogen, may be combined with the etchant, the silicon source, or both. Generally, the process chamber is heated to a higher temperature during a chamber clean process than during either a slow etch process or a fast etch process. In one example, the process chamber may be heated to a temperature within a range from about 7000C to about 1 ,0000C during a chamber clean process.
[0010] In another embodiment, a method for forming a silicon-containing material on a substrate surface is provided which includes positioning a substrate containing a silicon material within a process chamber, and exposing the substrate to an etching gas containing chlorine gas and silane during an etching process. The method may further provide exposing the substrate to a deposition gas containing the chlorine gas and the silane during an epitaxial deposition process, removing the substrate from the process chamber, and exposing the process chamber to a chamber clean gas containing the chlorine gas and the silane during a chamber clean process. In one example, the silicon material is removed during the etching process at a rate of about 100 A/min or less, preferably, at the rate of about 10 A/min or less, and more preferably, at the rate of about 2 A/min or less. In another example, the silicon material is removed during the etching process at a rate greater than 100 A/min, preferably, at a rate within a range from about 200 A/min to about 1 ,000 A/min. [0011] In another embodiment, a method for etching a silicon-containing monocrystalline material on a substrate having at least a second material {e.g., a nitride material, an oxide material, or combinations thereof) is provided which includes positioning a substrate within a process chamber, exposing the substrate to an etching gas containing chlorine gas and a carrier gas, removing a predetermined thickness of the silicon-containing monocrystalline material to form an exposed monocrystalline surface, and depositing an epitaxy layer on the exposed monocrystalline surface within the process chamber. The etching gas may include a silicon source, such as silane, disilane, dichlorosilane, tetrachlorosilane, hexachlorodisilane, a derivative thereof, or a combination thereof and the carrier gas may include nitrogen, argon, helium, or a combination thereof. In one example, the process chamber is heated at a temperature within a range from about 500°C to about 700°C and pressurized at a pressure within a range from about 10 Torr to about 750 Torr. The monocrystalline material may be removed at a rate within a range from about 200 A per minute to about 1 ,000 A per minute to form a recess formation within a source/drain area on the substrate. The source/drain area may be used within a CMOS, Bipolar, BiCMOS, or a similar device. The epitaxial layer usually contains silicon, silicon-germanium, silicon-carbon, silicon-germanium- carbon, a derivative thereof, or a combination thereof.
[0012] In another embodiment, a method for forming a silicon-containing monocrystalline material on a substrate is provided which includes exposing a substrate to a HF-last wet clean process, positioning the substrate within a process chamber, exposing the substrate to an etching gas comprising chlorine gas and a carrier gas, and removing a predetermined thickness of the silicon-containing monocrystalline material to form an exposed monocrystalline surface. The method may further provide depositing an epitaxy layer on the exposed monocrystalline surface in the process chamber, and cleaning the process chamber with the chlorine gas to remove silicon-containing contaminant adhered thereon. The epitaxy layer may be deposited by a deposition gas containing chlorine gas and the carrier gas may be nitrogen. In one example, nitrogen and chlorine-gas are co-flowed during the process chamber clean step. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] So that the manner in which the above recited features of the invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
[0014] Figure 1 is a flow chart depicting a process for treating a silicon-containing material by one embodiment described herein;
[0015] Figures 2A-2C show schematic illustrations of a substrate at different stages during a process described herein;
[0016] Figure 3 is a flow chart depicting a process for treating a silicon-containing material by another embodiment described herein;
[0017] Figures 4A-4C show schematic illustrations of another substrate at different stages during a process described herein; and
[0018] Figure 5 is a flow chart depicting a process for fabricating substrates and thereafter cleaning the process chamber by another embodiment described herein.
DETAILED DESCRIPTION
[0019] Embodiments of the invention provide processes for etching and depositing silicon-containing materials on substrate surfaces. In one embodiment, a slow etch process (e.g., <100 A/min) and fast etch process {e.g., >100 A/min) utilizes an etchant and a silicon source within the etching gas. In another embodiment, the process chamber is exposed to an etching gas during a chamber clean step for removing deposits or contaminants from the interior surfaces. In another embodiment, a process chamber is cleaned during a chamber clean process by exposing the interior surfaces of the process chamber to an etching gas to remove particulates and other contaminants.
Slow Etch Process (pre-clean and smooth)
[0020] A slow etch process {e.g., <100 A/min) may be conducted to remove contaminants and surface irregularities, such as roughness, from a substrate surface. In one aspect, the substrate surface may be etched to expose an underlayer free or substantially free of contaminants. In another aspect, material of the substrate surface may be redistributed to minimize or remove peaks and troughs that attribute to surface irregularities. During the slow etch process, the substrate is exposed to an etching gas containing an etchant, a silicon source, and an optional carrier gas. The overall reaction may be controlled in part by manipulating the relative flow rates of the etchant and the silicon source, using a specific etchant source and a silicon source and by adjusting the temperature and the pressure.
[0021] The substrate may be exposed to a pre-treatment process to prepare the substrate surface for the subsequent etching process. A pre-treatment process may include a wet clean process, such as a HF-last process, a plasma clean, an acid wash process, or combinations thereof. In one example, the substrate is treated with a HF-last wet clean process by exposing the surface to a hydrofluoric acid solution {e.g., about 0.5 wt% HF in water) for a duration of about 2 minutes.
[0022] Figure 1 illustrates a flow chart depicting process 100 for removing contaminants 212 and rough areas 218 from substrate 200 that is graphically illustrated by Figure 2A. Substrate 200 contains silicon-containing layer 205 and surface 210. Contaminants 212 and rough areas 218 are contained on and in surface 210. Rough areas 218 may be formed by peaks 216 and troughs 214 within surface 210. A predetermined thickness 220 of material from silicon-containing layer 205 may be removed during the slow etch process to reveal exposed surface 230 (Figure 2B). Subsequently, layer 240 may be formed on exposed surface 230 during an optional deposition process (Figure 2C). In one example, layer 240 contains a silicon-containing material deposited by an epitaxy deposition process. [0023] Embodiments of the invention provide processes to etch and deposit silicon-containing materials on various substrates surfaces and substrates, such as substrates 200 and 400 and layers 205 and 405 (Figures 2A-2C and 4A-4C) A "substrate" or "substrate surface" as used herein refers to any substrate or material surface formed on a substrate upon which film processing is performed. For example, a substrate surface on which processing may be performed include materials such as silicon, silicon-containing materials, silicon oxide, strained silicon, silicon on insulator (SOI), fluorine-doped silicate glass (FSG), carbon doped silicon oxides, silicon nitride, doped silicon, silicon germanium, silicon germanium carbon, germanium, silicon carbon, gallium arsenide, glass, sapphire, or other materials depending on the application. A substrate surface may also include dielectric materials such as silicon dioxide, silicon nitride, silicon oxynitride, and/or carbon doped silicon oxides. Substrates may have various dimensions, such as 200 mm or 300 mm diameter round wafers, as well as, rectangular or square panes. Embodiments of the processes described herein etch and deposit on many substrates and surfaces, especially, silicon and silicon-containing materials. Substrates on which embodiments of the invention may be useful include, but are not limited to semiconductor wafers, such as crystalline silicon {e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers silicon nitride, and patterned or non- patterned wafers.
[0024] Throughout the application, the terms "silicon-containing" materials, compounds, films or layers should be construed to include a composition containing at least silicon and may contain germanium, carbon, boron, arsenic, phosphorous gallium and/or aluminum. Other elements, such as metals, halogens or hydrogen may be incorporated within a silicon-containing material, compound, film or layer, usually with concentrations of about part per million (ppm). Compounds or alloys of silicon-containing materials may be represented by an abbreviation, such as Si for silicon, SiGe, for silicon germanium, SiC for silicon carbon and SiGeC for silicon germanium carbon. The abbreviations do not represent chemical equations with stoichiometrical relationships, nor represent any particular reduction/oxidation state of the silicon-containing materials. Silicon-containing materials, compounds, films, or layers may include substrates or substrate surfaces.
[0025] Contaminants 212 on surface 210 include organic residues, carbon, oxides, nitrides, halides {e.g., fluorides or chlorides), or combinations thereof. For example, surface 210 may contain a layer of silicon oxide after being exposed to the ambient air or may contain a layer of silicon fluoride after being treated with a HF- last wet clean process. Surface 210 may also contain irregularities or regional areas of roughness, such as troughs 214 and peaks 216 within rough areas 218.
[0026] Substrate 200 may be positioned within a process chamber and heated to a predetermined temperature (step 110). The substrate and the process chamber may be heated completely or a portion thereof to temperature within a range from about 3000C to about 8000C, preferably, from about 5000C to about 7000C, and more preferably, from about 5500C to about 650°C. The process chamber may be maintained at a pressure within a range from about 1 mTorr to about 760 Torr, preferably, from about 0.1 Torr to about 500 Torr, and more preferably, from about 1 Torr to about 100 Torr.
[0027] In one embodiment, a cold wall reactor is used as a process chamber for processes conducted at lower temperatures. A cold wall reactor may provide temperature control of each independent portion within the reactor, such as reactor walls, reactor dome and substrate susceptor. Usually, the reactor dome may be formed from quartz. In one example, the cold wall reactor may have reactor walls maintained at a temperature less than about 4000C, preferably, less than about 2000C, and more preferably, less than about 1500C, a reactor dome maintained at a temperature within a range from about 3000C to about 8000C, preferably, from about 4000C to about 7000C, and more preferably, from about 5000C to about 6000C, and a substrate susceptor maintained at a temperature within a range from about 3000C to about 8000C, preferably, from about 5000C to about 7000C, and more preferably, from about 5500C to about 6500C. [0028] The etching gas used during the slow etch process (step 120) contains an etchant, a silicon source and an optional carrier gas. The etchant, the silicon source and the carrier gas may be premixed, co-flowed or independently flowed into the process chamber. In one aspect, the etchant and a carrier gas are either co-flowed or combined together as a gas mixture, the silicon source and a carrier gas are either co-flowed or combined together as a gas mixture and the two gas mixtures may be co-flowed together prior to entering the process chamber. For example, a gas mixture of chlorine and nitrogen may be co-flowed into the process chamber with a mixture of silane and nitrogen. In another example, a gas mixture of chlorine and nitrogen may be co-flowed into the process chamber with a mixture of silane and hydrogen.
[0029] Preferably, the etchant is chlorine gas (Cl2). In one example, it has been found that chlorine works exceptionally well as an etchant for silicon-containing materials at temperatures lower than processes using more common etchants, such as hydrogen chloride. Therefore, an etch process utilizing chlorine may be conducted at a lower process temperature. The silicon source may be administered simultaneously with the etchant in order to counter act any over-etching of susceptible surfaces on substrate 200. The silicon source is used to deposit silicon on the silicon-containing layer while the etchant removes the silicon-containing material. The rates at which the etchant and the silicon source are exposed to the substrate are adjusted so that the overall reaction favors material removal and/or material redistribution. Therefore, the overall reaction is removing or redistributing silicon-containing material and the etch rate may be finely controlled to several angstroms per minute.
[0030] The etchant is usually administered into the process chamber at a rate within a range from about 1 standard cubic centimeters per minute (seem) to about 1 standard liters per minute (slm), preferably, from about 5 seem to about 150 seem, and more preferably, from about 10 seem to about 30 seem, for example, about 20 seem. While chlorine is the preferred etchant, other etchants that may be used solely or in combination include chlorine trifluoride (CIF3), tetrachlorosilane (SiCI4), or a derivative thereof. [0031] The silicon source is usually provided into the process chamber for slow etch processes at a rate within a range from about 5 seem to about 500 seem, preferably, from about 10 seem to about 100 seem, and more preferably, from about 20 seem to about 80 seem, for example, about 50 seem. Silicon sources that may be used in the etching include silanes, halogenated silanes, organosilanes, or derivatives thereof. Silanes include silane (SiH4) and higher silanes with the empirical formula SixH(2x+2), such as disilane (SJaH6), trisilane (Si3H8), and tetrasilane (Si4Hi0), as well as others. Halogenated silanes include compounds with the empirical formula X'ySiχH(2χ+2-y), where X' is independently selected from F, Cl, Br, or I, such as hexachlorodisilane (Si2CI6), tetrachlorosilane (SiCI4), trichlorosilane (CI3SiH), dichlorosilane (CI2SiH2) and chlorosilane (CISiH3). Organosilanes include compounds with the empirical formula RySixH(2x+2-y), where R is independently selected from methyl, ethyl, propyl or butyl, such as methylsilane ((CH3)SiH3), dimethylsilane ((CH3)2SiH2), ethylsilane ((CH3CH2)SiH3), methyldisilane ((CH3)Si2H5), dimethyldisilane ((CH3)2Si2H4), and hexamethyldisilane ((CH3)6Si2). The preferred silicon sources may include silane, dichlorosilane, or disilane.
[0032] The carrier gas is usually provided into the process chamber at a flow rate within a range from about 1 slm to about 100 slm, preferably, from about 5 slm to about 80 slm, and more preferably, from about 10 slm to about 40 slm, for example, about 20 slm. Carrier gases may include nitrogen (N2), hydrogen (H2), argon, helium, or combinations thereof. In one embodiment, an inert carrier gas is preferred and includes nitrogen, argon, helium, or combinations thereof. A carrier gas may be selected based on the precursor(s) used and/or the process temperature of the slow etch process of step 120.
[0033] Preferably, nitrogen is utilized as a carrier gas in embodiments featuring low temperature {e.g., <800°C) processes. Low temperature processes are accessible due in part to the use of chlorine gas in the etching process. Nitrogen remains inert during low temperature etching processes. Therefore, nitrogen is not incorporated into the silicon-containing materials on the substrate during low temperature processes. Also, a nitrogen carrier gas does not form hydrogen- terminated surfaces as does a hydrogen carrier gas. The hydrogen-terminated surfaces formed by the adsorption of hydrogen carrier gas on the substrate surface inhibit the growth rate of subsequently deposited silicon-containing layers. Finally, the low temperature processes may take economic advantage of nitrogen as a carrier gas, since nitrogen is far less expensive than hydrogen, argon, or helium. In one example of an etching gas, chlorine is the etchant, silane is the silicon source and nitrogen is the carrier gas.
[0034] Substrate 200 and surface 210 may be exposed to a slow etch gas to remove a predetermined thickness 220 of silicon-containing layer 205 during step 120 (Figures 2A-2B). Surface 210 is etched during the removal of the predetermined thickness 220. The slow etch gas is exposed to substrate 200 for a time period within a range from about 5 seconds to about 5 minutes, preferably, from about 30 seconds to about 2 minutes. The amount of time is adjusted relative to the etch rate used in a particular process. The etch rate of a slow etch process is usually less than about 100 A/min, preferably, less than about 50 A/min. In one embodiment, the slow etch rate is within a range from about 2 A/min to about 20 A/min, preferably, from about 5 A/min to about 15 A/min, for example, about 10 A/min. In another embodiment, the etch rate is about 2 A/min or less, preferably, about 1 A/min or less, and more preferably, approaches a redistribution of material on the substrate such that the net removal rate is non-measurable relative to the thickness of the layer. As the etch process is slowed to a redistribution reaction, material of silicon-containing layer 205 may be removed from peaks 216 and added to troughs 214 within surface 210 to form exposed surface 230. Troughs 214 may be filled by the material derived from peaks 216 and/or virgin material being produced by the introduction of precursors (e.g., silicon source) within the slow etch gas.
[0035] A slow etch process may be utilized to reduce the surface roughness on substrate 200. In one example, surface 210 with a surface roughness of about 6 nm root mean square (RMS) or more, may be exposed to a slow etch gas to remove material from silicon-containing layer 205 by predetermined thickness 220 to reveal exposed surface 230. Exposed surface 230 may have a surface roughness of about
1 nm RMS or less, preferably, about 0.1 nm RMS or less, and more preferably, about 0.07 nm RMS. Contaminants 212 and rough areas 218 previously disposed on or in surface 210 are removed during process 100. Exposed surface 230 is usually free or substantially free of contaminants that include organic residues, carbon, oxides, nitrides, halides (e.g., fluorides or chlorides), or combinations thereof.
[0036] An optional purge process may be performed within the process chamber during step 125 (Figure 1 ). The purge process helps remove residual etch gas from substrate 200, which in turn enhances the growth during the subsequent deposition process (step 130). During a low pressure purge process, the process chamber may have an internal pressure within a range from about 0.1 mTorr to about 100 Torr, preferably, from about 1.0 mTorr to about 10 Torr, and more preferably, from about 10.0 mTorr to about 1 Torr. The purge process may be conducted for a time period within a range from about 30 seconds to about 10 minutes, preferably, from about 1 minute to about 5 minutes, and more preferably, from about 2 minutes to about 4 minutes. Generally, all of the gas entering the process chamber may be turned off. However, in an alternative aspect, a purge gas may be administered anytime during the purge process. A purge gas may include nitrogen, hydrogen, argon, helium, forming gas, or combination thereof.
[0037] Layer 240 may be deposited on exposed surface 230 during step 130. Preferably, layer 240 is a silicon-containing material that may be selectively and epitaxially grown or deposited on exposed surface 230 by a chemical vapor deposition (CVD) process. Chemical vapor deposition processes, as described herein, include many techniques, such as atomic layer epitaxy (ALE), atomic layer deposition (ALD), plasma-assisted CVD (PA-CVD) or plasma-enhanced CVD (PE- CVD), plasma-assisted ALD (PA-ALD) or plasma-enhanced ALD (PE-ALD), atomic layer CVD (ALCVD), organometallic or metal-organic CVD (MOCVD or OMCVD), laser-assisted CVD (LA-CVD), ultraviolet CVD (UV-CVD), hot-wire (HWCVD), reduced-pressure CVD (RP-CVD), ultra-high vacuum CVD (UHV-CVD), derivatives thereof, or combinations thereof. In one example, a preferred process utilizes thermal CVD to epitaxially grow or deposit a silicon-containing compound as layer
240 on exposed surface 230. The deposition gas used during step 130 may also contain at least one secondary elemental source, such as a germanium source and/or a carbon source. The germanium source may be added to the process chamber with the silicon source, etchant and carrier gas to form a silicon-containing compound. Therefore, the silicon-containing compound may contain silicon, SiGe, SiC, SiGeC, doped variants thereof, or combinations thereof. Germanium and/or carbon may be added to the silicon-containing material by including germanium source {e.g., germane), or a carbon source {e.g., methylsilane) during the deposition process. The silicon-containing compound may also contain dopants by including a boron source {e.g., diborane), an arsenic source {e.g., arsine), or a phosphorous source {e.g., phosphine) during or after the deposition process. The dopant may be included within the silicon source, etchant and carrier gas to form a silicon- containing compound. Alternatively, the dopant may be added to the silicon- containing material by exposing the substrate to an ion implantation process.
[0038] In another example, a CVD process called alternating gas supply (AGS) may be used to epitaxially grow or deposit a silicon-containing compound as layer 240 on exposed surface 230. The AGS deposition process includes a cycle of alternating exposures of silicon-sources and etchants to the substrate surface. An AGS deposition process is further disclosed in commonly assigned and co-pending United States Serial No. 11/001 ,774, filed December 1 , 2004, entitled "Selective Epitaxy Process with Alternating Gas Supply," which is incorporated herein by reference in its entirety for the purpose of describing an AGS process.
[0039] Process 100 may be used to etch and deposit silicon-containing materials within the same process chamber. Preferably, the slow etch process (step 120) and the subsequent deposition process (step 130) are performed within the same process chamber to improve throughput, be more efficient, decrease probability of contamination and benefit process synergies, such as common chemical precursors. In one aspect, a slow etch process and a deposition process each utilize the same silicon source, the same etchant and the same carrier gas. For example, an etch gas for a slow etch process may contain silane, chlorine, and nitrogen, while a deposition gas for a selective, epitaxial deposition process may also contain silane, chlorine, and nitrogen. The concentration ratio of the silicon source and the reductant may be adjusted during the overall process to encourage a particular step. In one example, the concentration ratio of the silicon source and the reductant is increased to promote a deposition step. In another example, the concentration ratio of the silicon source and the reductant is decreased to promote an etch step.
Fast Etch Process
[0040] In another embodiment, a fast etch process {e.g., >100 A/min) may be used to selectively remove a silicon-containing material from a substrate surface. The fast etch process is a selective etch process to remove silicon-Gontaining material while leaving barrier material unscathed. Barrier materials may include silicon nitride, silicon oxide, or silicon oxynitride used as spacers, capping layers, or mask materials.
[0041] Figure 3 illustrates a flow chart depicting process 300 is initiated by positioning the substrate into a process chamber and adjusting the process parameters during step 310. The substrate and the process chamber may be heated completely or a portion thereof to a temperature within a range from about 400°C to about 800°C, preferably, from about 5000C to about 700°C, and more preferably, from about 5500C to about 6500C. The process chamber is maintained at a pressure within a range from about 1 Torr to about 760 Torr, preferably, from about 0.1 Torr to about 500 Torr, and more preferably, from about 1 Torr to about 100 Torr.
[0042] The etching gas used during the fast etch process contains an etchant, a carrier gas and an optional silicon source (step 320). In one example, the etching gas contains chlorine, nitrogen, and silane. The etchant may be provided into the process chamber gas at a rate within a range from about 1 seem to about 100 seem, preferably from about 5 seem to about 50 seem, and more preferably, from about 10 seem to about 30 seem, for example, about 20 seem. While chlorine is the preferred etchant during a fast etch process, other etchants that may be used solely or in combination include chlorine trifluoride, tetrachlorosilane, or a derivative thereof. [0043] The carrier gas is usually provided into the process chamber at a flow rate within a range from about 1 slm to about 100 slm, preferably, from about 5 slm to about 80 slm, and more preferably, from about 10 slm to about 40 slm, for example, about 20 slm. Carrier gases may include nitrogen, hydrogen, argon, helium, or combinations thereof. In one embodiment, an inert carrier gas is preferred and includes nitrogen, argon, helium, or combinations thereof. A carrier gas may be selected based on the precursor(s) used and/or the process temperature during the etching process of step 320. Preferably, nitrogen is used as a carrier gas during embodiments featuring low temperature {e.g., <800°C) processes. In one example, an etching gas for a first etch process contains chlorine and nitrogen.
[0044] In some embodiments, a silicon source may be optionally added to the etching gas for providing additional control of the etch rate during a fast etch process. The silicon source may be delivered into the process chamber at a rate within a range from about 5 seem to about 500 seem, preferably, from about 10 seem to about 100 seem, and more preferably, from about 20 seem to about 80 seem, for example, about 50 seem. The etching gas may contain a silicon source, such as silanes, halogenated silanes, organosilanes, or derivatives thereof, as described herein.
[0045] Substrate 400 contains at least one film stack feature 410 (Fig 4A). Silicon-containing layer 405 may be a doped or undoped, bare silicon substrate or include a silicon-containing layer disposed thereon. Film stack feature 410 includes gate layer 412 on gate oxide layer 414 surrounded by spacers 416 and protective capping layer 418. Generally, gate layer 412 is composed of a polysilicon and gate oxide layer 414 is composed of silicon dioxide, silicon oxynitride, or hafnium oxide. Partially encompassing the gate oxide layer 414 is a spacer 416, which is usually an isolation material containing silicon oxide, silicon nitride, silicon oxynitride, derivatives thereof, or combinations thereof. In one example, spacer 416 is a nitride/oxide stack {e.g., Si3N4ZSiO2ZSi3N4). Gate layer 412 may optionally have a protective capping layer 418 adhered thereon. [0046] During step 320, substrate 400 is exposed to an etching gas to remove a predetermined thickness 425 of silicon-containing layer 405 and form a recess 430, as depicted in Figure 4B. The etching gas is exposed to substrate 400 for a time period within a range from about 10 seconds to about 5 minutes, preferably, from about 1 minute to about 3 minutes. The amount of time is adjusted relative to the etch rate used in a particular process. The etch rate of a fast etch process is usually faster than about 100 A/min, preferably, faster than about 200 A/min, such as at a rate within a range from about 200 A/min to about 1 ,500 A/min, preferably, from about 200 A/min to about 1 ,000 A/min, for example, about 600 A/min.
[0047] In one example, the etching process may be kept at a fast rate to remove the predetermined thickness 425, and then reduced to a slow rate process to smooth the remaining surface. The reduced etching rate may be controlled by a slow etching process described by process 100.
[0048] An optional purge process may be performed within the process chamber during step 325. The purge process helps remove residual etch gas from substrate 400, which in turn enhances the growth during the subsequent deposition process (step 330). During a low pressure purge process, the process chamber may have an internal pressure within a range from about 0.1 mTorr to about 100 Torr, preferably, from about 1.0 mTorr to about 10 Torr, and more preferably, from about 10.0 mTorr to about 1 Torr. The purge process may be conducted for a time period within a range from about 30 seconds to about 10 minutes, preferably, from about 1 minute to about 5 minutes, and more preferably, from about 2 minutes to about 4 minutes. Generally, all of the gas entering the process chamber may be turned off. However, in an alternative aspect, a purge gas may be administered into the process chamber anytime during the purge process.
[0049] Once the predetermined thickness 425 of substrate 400 is removed, layer 440 may be deposited during step 330 (Figure 4C). Preferably, layer 440 is a silicon-containing material that may be selectively and epitaxially deposited on the exposed surface of recess 430 a CVD process. In one example, the CVD process includes an AGS deposition technique. Alternatively, recess 430 may be exposed to another fabrication process prior to the deposition of layer 440, such as a doping process. One example of a doping process includes ion implantation, in which a dopant {e.g., boron, phosphorous, or arsenic) may be implanted into the surface of the recess 430.
[0050] Process 300 may be used to etch and deposit silicon-containing materials in the same process chamber. Preferably, the fast etch process and the subsequent deposition is performed in the same process chamber to improve throughput; be more efficient, decrease probability of contamination and benefit process synergies, such as common chemical precursors. In one example, both the fast etch process and the selective, epitaxial deposition process of a silicon-containing compound use chlorine as an etchant and nitrogen as a carrier gas.
[0051] Figure 5 illustrates an alternative embodiment of the invention that includes cleaning the process chamber after finishing fabrication techniques during process 500. The substrate may be exposed to a pre-treatment process that includes a wet clean process, a HF-last process, a plasma clean, an acid wash process, or combinations thereof (step 510). After a pre-treatment process and prior to starting an etching process described herein, the substrate may have to remain outside the controlled environment of the process chamber for a period of time called queue time (Q-time). The Q-time in an ambient environment may last about 2 hours or more, usually, the Q-time last much longer, such as a predetermined time with a range from about 6 hours to about 24 hours or longer, such as about 36 hours. A silicon oxide layer usually forms on the substrate surface during the Q-time due to the substrate being exposed to ambient water and oxygen.
[0052] During step 520, the substrate is positioned into a process chamber and exposed to an etching process as described herein. The etching process may be a slow etch process as described in step 120, a fast etch process as described in step 320 or both. The etching process removes a pre-determined thickness of silicon- containing layer from the substrate to form an exposed silicon-containing layer. Subsequently, an optional purge process may be performed within the process chamber (step 525). Thereafter, a secondary material is deposited on the exposed silicon-containing layer (step 530). Usually, the secondary material is in a selective, epitaxially deposited silicon-containing compound. The deposition process may include the processes as described during steps 130 and 330. In one embodiment, processes 100 and 300 may be used during steps 520 and 530.
[0053] A chamber clean process is conducted inside the process chamber to remove various contaminants therein (step 540). Etch processes and deposition processes may form deposits or contaminants on surfaces within the process chamber. Usually, the deposits include silicon-containing materials adhered to the walls and other inner surfaces of the process chamber. Therefore, a chamber clean process may be used to remove contaminants while not damaging interior surfaces of the process chamber.
[0054] In an example of process 500, the substrate is first exposed to a HF-last process. The substrate is placed into a process chamber and exposed to an etch process that contains chlorine and nitrogen at about 6000C. Thereafter, the process chamber is exposed to a purge process. Subsequently, a silicon-containing layer is epitaxially deposited on the substrate by a deposition process utilizing chlorine and nitrogen at about 625°C within the same process chamber. Thereafter, the substrate is removed and the process chamber is heated to about 675°C and exposed to a cleaning gas containing chlorine and nitrogen. Preferably, the etchant and the carrier gas are the same gases used during steps 520 and 540.
Chamber Clean Process
[0055] In another embodiment, a chamber clean gas containing a silicon source may be used to remove various contaminants from inside a process chamber during a chamber clean process, such as step 540. The interior surfaces of the process chamber usually contain a silicon-containing material {e.g., quartz) that may be damaged during a traditional etchant clean process. Therefore, besides an etchant and a carrier gas, the chamber clean gas may further contain a silicon source to counter act any over-etching caused by the etchant. [0056] The process chamber may contain an interior surface or components having a surface that is chemically vulnerable to an etchant. Also, the interior surface or componential part within the process chamber may have a protective coating that is vulnerable to an etchant. Generally, these interior surface within the process chamber may contain a silicon-containing surface, such as quartz, silicon oxide, silicon carbide, silicon carbide coated graphite, sapphire, suicide coatings, derivatives thereof, or combinations thereof. In other examples, the interior surface is a metal-containing surface within the process chamber, such as steel, stainless steel, iron, nickel, chromium, aluminum, alloys thereof, or combinations thereof. The interior surfaces may be on the interior of the walls, floor, and lid of the chamber, as well as internal components or portions thereof, such as a susceptor, a linear, an upper dome, a lower dome, a preheat ring, a showerhead, a dispersion plate, a probe, or the like.
[0057] The cleaning process includes heating the substrate susceptor to a temperature within a range from about 6000C to about 1 ,200°C, preferably, from about 650°C to about 1 ,0000C, and more preferably, from about 7000C to about 9000C, for example, about 8000C. The process chamber may have an internal pressure within a range from about 1 mTorr to about 760 Torr, preferably, from about 100 mTorr to about 750 Torr, and more preferably, from about 100 Torr to about 700 Torr, for example, 600 Torr. In one example, a cold wall reactor is used as a process chamber and may have reactor walls maintained at a temperature less than about 4000C, preferably, less than about 2000C, and more preferably, less than about 1500C and a quartz reactor dome maintained at a temperature within a range from about 3000C to about 800°C, preferably, from about 4000C to about 7000C, and more preferably, from about 5000C to about 6000C.
[0058] The cleaning process is conducted for a time period within a range from about 30 seconds to about 10 minutes, preferably, from about 1 minute to about 5 minutes, and more preferably, from about 2 minutes to about 4 minutes. A chamber cleaning gas may contain an etchant, a silicon source and a carrier gas. Preferably, the etchant, the silicon source and the carrier gas used during the chamber cleaning process are the same gases used during a previous fabrication step, such as a slow etch process or a fast etch process. The etchant may be provided into the process chamber during the chamber clean process at a rate within a range from about 10 seem to about 100 slm, preferably, from about 100 seem to about 5 slm. In one example, the etchant has a flow rate of about 5 slm, preferably, about 10 slm, and more preferably, about 20 slm. In another example, the etchant has a flow rate of about 50 seem, preferably, about 130 seem, and more preferably, about 1 ,000 seem. Etchants that may be used within the cleaning gas include chlorine, chlorine trifluoride, tetrachlorosilane, hexachlorodisilane, or derivatives thereof.
[0059] The silicon source may be provided into the process chamber during the chamber clean process at a rate within a range from about 10 seem to about 100 slm, preferably, from about 100 seem to about 5 slm. In one example, the silicon source has a flow rate of about 5 slm, preferably, about 10 slm, and more preferably, about 20 slm. In another example, the silicon source has a flow rate of about 50 seem, preferably, about 130 seem, and more preferably, about 1 ,000 seem. Silicon sources that may be used in the etching include silanes, halogenated silanes, organosilanes or derivatives thereof. Silanes include silane (SiH4) and higher silanes with the empirical formula SixH(2χ+2), such as disilane (Si2H6), trisilane (SJsH8), and tetrasilane (Si4Hi0), as well as others. Halogenated silanes include compounds with the empirical formula X'ySiχH(2χ+2-y), where X1 is independently selected from F, Cl, Br or I, such as hexachlorodisilane (Si2CI6), tetrachlorosilane (SiCI4), trichlorosilane (CI3SiH), dichlorosilane (CI2SiH2), and chlorosilane (CISiH3). Organosilanes include compounds with the empirical formula RySixH(2x+2-y), where R is independently selected from methyl, ethyl, propyl or butyl, such as methylsilane ((CH3)SiH3), dimethylsilane ((CHs)2SiH2), ethylsilane ((CH3CH2)SiH3), methyldisilane ((CH3)Si2H5), dimethyldisilane ((CHs)2Si2H4), and hexamethyldisilane ((CHs)6Si2). Preferred silicon sources may include silane, dichlorosilane, or disilane.
[0060] The carrier gas may be provided into the process chamber during the chamber clean process at a rate within a range from about 100 seem to about 100 slm. In one example, the carrier gas has a flow rate of about 20 slm, preferably, about 50 slm, and more preferably, about 100 slm. In another example, the carrier gas has a flow rate of about 100 seem, preferably, about 1 slm, and more preferably, about 10 slm. Carrier gases may include nitrogen, hydrogen, forming gas, argon, helium or combinations thereof. In a preferred example, a chamber clean gas contains chlorine gas, silane and a carrier gas, such as nitrogen. A chamber clean process that may be used within embodiments of the invention described herein is further disclosed in commonly assigned U.S. Patent No. 6,042,654, which is incorporated herein by reference in its entirety. The chamber clean process may be repeated after processing each individual substrate or after multiple substrates. In one example, the chamber clean process is conducted after processing every 25 substrates. In another example, the chamber clean process is conducted after processing every 5 substrates. In another example, the chamber clean process is conducted after processing every 100 substrates. Although a substrate may remain in the process chamber during the chamber clean process, preferably, the substrate is removed and the process is performed on an empty chamber.
[0061] Embodiments, as described herein, provide processes that may be utilized during fabrication processes for Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and bipolar transistors, such as Bipolar device fabrication {e.g., base, emitter, collector, and emitter contact), BiCMOS device fabrication (e.g., base, emitter, collector, emitter contact), and CMOS device fabrication (e.g., channel, source/drain, source/drain extension, elevated source/drain, substrate, strained silicon, silicon on insulator, and contact plug). Other embodiments provide processes that may be utilized during gate fabrication processes, base contact fabrication processes, collector contact fabrication processes, emitter contact fabrication processes, or elevated source/drain fabrication processes.
[0062] The processes of the invention may be conducted on fabrication equipment used for ALE, CVD1 and ALD processes. A system that may be used to etch or deposit the silicon-containing films as described herein include the Epi Centura® system or the Poly Gen® system, both available from Applied Materials, Inc., located in Santa Clara, California. A process chamber useful to etch and deposit as described herein is further disclosed in commonly assigned U.S. Patent No. 6,562,720, which is incorporated herein by reference in its entirety for the purpose of describing the apparatus. Other enabling apparatuses include batch furnaces and high-temperature furnaces.
EXAMPLES
[0063] The following hypothetical examples may be conducted on 300 mm silicon wafers within an Epi Centura® system, available from Applied Materials, Inc., located in Santa Clara, California.
[0064] Example 1 - Pre-clean process comparative without silane: A substrate was exposed to an HF-last process to form a fluoride terminated surface. The substrate was placed in the process chamber and heated to about 600°C while the pressure was maintained at about 20 Torr. The substrate was exposed to an etching gas containing N2 at a flow rate of about 20 slm and Cl2 at flow rate of about 120 seem. The surface was etched at a rate of about 500 A/min.
[0065] Example 2 - Pre-clean process with silane: A substrate was exposed to an HF-last process to form a fluoride terminated surface. The substrate was placed in the process chamber and heated to about 600°C while the pressure was maintained at about 20 Torr. The substrate was exposed to an etching gas containing N2 at a flow rate of about 20 slm, Cl2 at flow rate of about 20 seem and SiH4 at a flow rate of about 50 seem. The surface was etched at a rate of about 10 A/min. Therefore, the addition of a silicon source, such as silane in Example 2, reduced the etch rate of the silicon-containing layer by about 50 times as compared to the etch rate in Example 1.
[0066] Example 3 - Smoothing process comparative without silane: A substrate surface containing a silicon-containing layer was cleaved forming a surface with a roughness of about 5.5 nm root mean square (RMS). The substrate was placed in the process chamber and heated to about 650°C while the pressure was maintained at about 200 Torr. The substrate was exposed to an etching gas containing N2 at a flow rate of about 20 slm and Cl2 at flow rate of about 20 seem. The surface was etched at a rate of about 200 A/min. [0067] Example 4 - Smoothing process with silane: A substrate surface containing a silicon-containing layer was cleaved forming a surface with a roughness of about 5.5 nm root mean square. The substrate was placed in the process chamber and heated to about 650°C while the pressure was maintained at about 200 Torr. The substrate was exposed to an etching gas containing N2 at a flow rate of about 20 slm, Cl2 at flow rate of about 20 seem and SiH4 at a flow rate of about 50 seem. The surface was etched at a rate of about 20 A/min. The surface roughness was reduced to about 0.1 nm RMS. Therefore, the addition of a silicon source, such as silane used in Example 4, reduced the etch rate of the silicon-containing layer by about 10 times as compared to the etch rate in Example 3.
[0068] Example 5 - Chlorine etch process followed by silicon-epitaxy: A silicon substrate contained a series of silicon nitride line features that are about 90 nm tall, about 100 nm wide and about 150 nm apart, baring the silicon surface. The substrate was placed in the process chamber and heated to about 600°C while the pressure was maintained at about 40 Torr. The substrate was exposed to an etching gas containing N2 at a flow rate of about 20 slm and Cl2 at flow rate of about 80 seem. The surface was etched at a rate of about 750 A/min. After about 30 seconds, about 35 nm of the silicon surface was etched. The silicon nitride features remain inert to the etching process. The pressure was increased to about 200 Torr and SiH4 was added to the etching gas at a flow rate of about 50 seem. The etch rate was reduced to about 18 A/min to smooth the freshly etched silicon surface. After about 1 minute, the smooth surface is exposed to a selective epitaxy deposition process by increasing the flow of SiH4 to about 100 seem and maintaining the flow of N2 and Cl2 unchanged. A silicon-containing material was deposited on the silicon surface at a rate of about 25 A/min.
[0069] Example 6 - Chlorine fast etch process containing silane: A silicon substrate contained a series of silicon nitride line features that are about 90 nm tall, about 100 nm wide and about 150 nm apart, baring the silicon surface. The substrate was placed in the process chamber and heated to about 600°C while the pressure was maintained at about 40 Torr. The substrate was exposed to an etching gas containing N2 at a flow rate of about 20 slm, Cl2 at flow rate of about 80 sccm and SiH4 at flow rate of about 40 seem. The surface was etched at a rate of about 400 A/min.
[0070] Example 7 - Chamber clean process containing chlorine and silane: After a silicon epitaxial deposition process, the substrate was removed from the chamber. The process chamber was heated to about 800°C while the pressure was adjusted to about 600 Torr. The process chamber was exposed to an etching gas containing N2 at a flow rate of about 20 slm, Cl2 at flow rate of about 2 slm and SiH4 at flow rate of about 1 slm. The chamber clean process was conducted for about 2 minutes.
[0071] While the foregoing is directed to embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

Claims:
1. A method for forming a silicon-containing material on a substrate surface, comprising: positioning a substrate containing a silicon material having a contaminant within a process chamber; exposing the substrate to an etching gas containing chlorine gas, a silicon source and a carrier gas during an etching process; and removing the contaminant and a predetermined thickness of the silicon material, wherein the silicon material is removed at a rate of about 2 A per min or less.
2. The method of claim 1 , wherein the rate is about 1 A per minute or less.
3. A method for forming a silicon-containing material on a substrate surface, comprising: positioning a substrate containing a silicon material having a contaminant within a process chamber; heating the process chamber at a temperature within a range from about 5000C to about 7000C exposing the substrate to an etching gas containing chlorine gas and silane during an etching process; and removing the contaminant and a predetermined thickness of the silicon material, wherein the silicon material is removed at a rate within a range from about 2 A per minute to about 20 A per minute.
4. A method for forming a silicon-containing material on a substrate surface, comprising: positioning a substrate containing a silicon material having a contaminant within a process chamber; exposing the substrate to an etching gas containing chlorine gas, a silicon source and a carrier gas during an etching process; and removing the contaminant and a predetermined thickness of the silicon material.
5. The method of claim 4, wherein the process chamber is exposed to a chamber clean gas containing the chlorine gas and the silicon source during a chamber clean process after the etching process.
6. The method of claim 4, wherein the silicon material is removed at a rate within a range from about 2 A per minute to about 20 A per minute.
7. The method of claim 6, wherein the process chamber is heated at a temperature within a range from about 500°C to about 700°C.
8. The method of claim 7, wherein the carrier gas is selected from the group consisting of nitrogen, argon, helium, and combinations thereof.
9. The method of claim 8, wherein the silicon source is selected from the group consisting of silane, disilane, dichlorosilane, tetrachlorosilane, hexachlorodisiiane, derivatives thereof, and combinations thereof.
10. The method of claim 9, wherein the carrier gas is nitrogen and the silicon source is silane.
11. The method of claim 6, wherein an epitaxy deposition process is conducted within the process chamber after the removing step.
12. The method of claim 11 , wherein the contaminant is selected from the group consisting of oxides, fluorides, chlorides, nitrides, organic residues, carbon, derivatives thereof, and combinations thereof.
13. The method of claim 12, wherein the substrate is exposed to a wet clean process prior to positioning within the process chamber.
14. The method of claim 13, wherein the substrate is exposed to ambient conditions for a period of time within a range from about 6 hours to about 24 hours after the wet clean process and before positioning within the process chamber.
15. The method of claim 12, wherein the silicon material further comprises a rough surface that is removed during the removing step.
16. A method of smoothing a silicon-containing material on a substrate surface, comprising: positioning a substrate containing a silicon material within a process chamber, wherein the silicon material has a first surface roughness of about 1 nm RMS or greater; exposing the substrate to an etching gas containing an etchant and a silicon source; and redistributing material to form the silicon material having a second surface roughness of less than about 1 nm RMS.
17. The method of claim 16, wherein a predetermined thickness of the silicon material is removed at a rate within a range from about 2 A per minute to about 20 A per minute.
18. The method of claim 16, wherein the process chamber is heated at a temperature within a range from about 500°C to about 700°C.
19. The method of claim 18, wherein the etching gas further contains a carrier gas selected from the group consisting of nitrogen, argon, helium, and combinations thereof.
20. The method of claim 19, wherein the silicon source is selected from the group consisting of silane, disilane, dichlorosilane, tetrachlorosilane, hexachlorodisilane, derivatives thereof, and combinations thereof.
21. The method of claim 20, wherein the etchant is selected from the group consisting of chlorine, chlorine trifluoride, tetrachlorosilane, derivatives thereof, and combinations thereof.
22. The method of claim 21 , wherein the carrier gas is nitrogen, the silicon source is silane and the etchant is chlorine gas.
23. The method of claim 18, wherein an epitaxy deposition process is conducted within the process chamber after the removing step.
24. The method of claim 23, wherein the silicon material further comprises a contaminant that is removed during the removing step and the contaminant is selected from the group consisting of oxides, fluorides, chlorides, nitrides, organic residues, carbon, derivatives thereof, and combinations thereof.
25. The method of claim 23, wherein the substrate is exposed to a wet clean process prior to positioning within the process chamber.
26. The method of claim 25, wherein the substrate is exposed to ambient conditions for a period of time within a range from about 6 hours to about 24 hours after the wet clean process and before positioning within the process chamber.
27. A method for forming a silicon-containing material on a substrate surface, comprising: positioning a substrate containing a silicon material within a process chamber; exposing the substrate to an etching gas containing chlorine gas and a silicon source during an etching process; exposing the substrate to a deposition gas during a deposition process; and exposing the process chamber to a chamber clean gas containing the chlorine gas and the silicon source during a chamber clean process.
28. The method of claim 27, wherein the substrate is removed from the process chamber prior to starting the chamber clean process.
29. The method of claim 28, wherein the silicon source is selected from the group consisting of silane, disilane, chlorosilane, dichlorosilane, dichlorosilane, trichlorosilane, hexachlorodisilane, derivatives thereof, and combinations thereof.
30. The method of claim 29, wherein the chamber clean gas further contains a carrier gas selected from the group consisting of nitrogen, hydrogen, argon, helium, forming gas, and combinations thereof.
31. The method of claim 30, wherein the silicon source is silane and the carrier gas is nitrogen.
32. The method of claim 29, wherein the process chamber is heated to a temperature of about 600°C or higher during the chamber clean process.
33. The method of claim 32, wherein the temperature is within a range from about 700°C to about 9000C and the process chamber is at a pressure of about 760 Torr or less.
34. The method of claim 27, wherein the silicon material further contains a contaminant or a rough surface prior to the etching process.
35. The method of claim 34, wherein the rough surface has a roughness of greater than 1 nm RMS.
36. The method of claim 35, wherein the rough surface is removed during the etching process to form a smooth surface having a roughness of about 1 nm RMS or less.
37. The method of claim 28, wherein the deposition gas contains the chlorine gas and the silicon source.
38. The method of claim 37, wherein the deposition process is an epitaxy deposition process.
39. The method of claim 28, wherein the etching gas, the deposition gas and the chamber clean gas contain silane.
40. The method of claim 28, wherein the etching gas, the deposition gas and the chamber clean gas contain silane and chlorine gas.
41. A method for forming a silicon-containing material on a substrate surface, comprising: positioning a substrate containing a silicon material within a process chamber; exposing the substrate to a deposition gas during a deposition process; and exposing the process chamber to a chamber clean gas containing chlorine gas and a silicon source during a chamber clean process.
42. The method of claim 41 , wherein the substrate is removed from the process chamber prior to starting the chamber clean process.
43. The method of claim 42, wherein the silicon source is selected from the group consisting of silane, disilane, chlorosilane, dichlorosilane, dichlorosilane, trichlorosilane, hexachlorodisilane, derivatives thereof, and combinations thereof.
44. The method of claim 43, wherein the chamber clean gas further contains a carrier gas selected from the group consisting of nitrogen, hydrogen, argon, helium, forming gas, and combinations thereof.
45. The method of claim 44, wherein the silicon source is silane and the carrier gas is nitrogen.
46. The method of claim 43, wherein the process chamber is heated to a temperature of about 600°C or higher during the chamber clean process.
47. The method of claim 46, wherein the temperature is within a range from about 700°C to about 9000C and the process chamber is at a pressure of about 760 Torr or less.
48. The method of claim 41 , further comprising exposing the silicon material to an etching gas containing an etchant gas and the silicon source during an etching process prior to the deposition process.
49. The method of claim 48, wherein the etchant gas contains chlorine gas.
50. The method of claim 49, wherein the silicon material contains a smooth surface having a roughness of about 1 nm RMS or less after the etching process.
51. The method of claim 49, wherein the deposition process is an epitaxy deposition process.
52. The method of claim 49, wherein the etching gas, the deposition gas and the chamber clean gas contain silane.
53. A method for forming a silicon-containing material on a substrate surface, comprising: positioning a substrate containing a silicon material within a process chamber; exposing the substrate to an etching gas containing chlorine gas and a silicon source during an etching process; exposing the substrate to a deposition gas containing the silicon source during an epitaxial deposition process; removing the substrate from the process chamber; and exposing the process chamber to a chamber clean gas containing an etchant gas and the silicon source during a chamber clean process.
54. The method of claim 53, wherein the silicon source is selected from the group consisting of silane, disilane, chlorosilane, dichlorosilane, dichlorosilane, trichlorosilane, hexachlorodisilane, derivatives thereof, and combinations thereof.
55. The method of claim 54, wherein the chamber clean gas contains chlorine gas.
56. The method of claim 55, wherein the silicon source is silane.
PCT/US2006/002841 2005-01-31 2006-01-27 Etchant treatment processes for substrate surfaces and chamber surfaces WO2006083693A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP06719625A EP1848550A4 (en) 2005-01-31 2006-01-27 Etchant treatment processes for substrate surfaces and chamber surfaces
JP2007553243A JP5329094B2 (en) 2005-01-31 2006-01-27 Etch treatment process for substrate and chamber surfaces
CN200680010817.0A CN101155648B (en) 2005-01-31 2006-01-27 The etchant process technique of substrate surface and chamber surface

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/047,323 US7235492B2 (en) 2005-01-31 2005-01-31 Low temperature etchant for treatment of silicon-containing surfaces
US11/047,323 2005-01-31
US11/242,613 US8093154B2 (en) 2005-01-31 2005-10-03 Etchant treatment processes for substrate surfaces and chamber surfaces
US11/242,613 2005-10-03

Publications (3)

Publication Number Publication Date
WO2006083693A2 true WO2006083693A2 (en) 2006-08-10
WO2006083693A3 WO2006083693A3 (en) 2006-12-07
WO2006083693B1 WO2006083693B1 (en) 2007-01-18

Family

ID=36777783

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/002841 WO2006083693A2 (en) 2005-01-31 2006-01-27 Etchant treatment processes for substrate surfaces and chamber surfaces

Country Status (3)

Country Link
EP (1) EP1848550A4 (en)
KR (1) KR100938301B1 (en)
WO (1) WO2006083693A2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008085198A (en) * 2006-09-28 2008-04-10 Hitachi Kokusai Electric Inc Method of manufacturing semiconductor device
EP2642001A1 (en) * 2010-11-17 2013-09-25 Nippon Steel & Sumitomo Metal Corporation Method for producing epitaxial silicon carbide single crystal substrate
US9865596B2 (en) 2010-04-12 2018-01-09 Mie Fujitsu Semiconductor Limited Low power semiconductor transistor structure and method of fabrication thereof

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100868228B1 (en) * 2007-12-04 2008-11-11 주식회사 켐트로닉스 Etchant composition for glass substrate
US10504717B2 (en) 2016-09-16 2019-12-10 Applied Materials, Inc. Integrated system and method for source/drain engineering
KR102599378B1 (en) * 2017-09-29 2023-11-08 솔브레인 주식회사 Composition for etching and manufacturing method of semiconductor device using the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05217921A (en) * 1991-09-13 1993-08-27 Motorola Inc Temperature-controlled treatment for execution of epitaxial growth of material film
US6171965B1 (en) * 1999-04-21 2001-01-09 Silicon Genesis Corporation Treatment method of cleaved film for the manufacture of substrates
US6489241B1 (en) * 1999-09-17 2002-12-03 Applied Materials, Inc. Apparatus and method for surface finishing a silicon film

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of EP1848550A4 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008085198A (en) * 2006-09-28 2008-04-10 Hitachi Kokusai Electric Inc Method of manufacturing semiconductor device
US9865596B2 (en) 2010-04-12 2018-01-09 Mie Fujitsu Semiconductor Limited Low power semiconductor transistor structure and method of fabrication thereof
EP2642001A1 (en) * 2010-11-17 2013-09-25 Nippon Steel & Sumitomo Metal Corporation Method for producing epitaxial silicon carbide single crystal substrate
EP2642001A4 (en) * 2010-11-17 2015-03-25 Nippon Steel & Sumitomo Metal Corp Method for producing epitaxial silicon carbide single crystal substrate

Also Published As

Publication number Publication date
WO2006083693A3 (en) 2006-12-07
KR20070108212A (en) 2007-11-08
EP1848550A2 (en) 2007-10-31
KR100938301B1 (en) 2010-01-22
EP1848550A4 (en) 2008-04-09
WO2006083693B1 (en) 2007-01-18

Similar Documents

Publication Publication Date Title
US8445389B2 (en) Etchant treatment processes for substrate surfaces and chamber surfaces
US7651948B2 (en) Pre-cleaning of substrates in epitaxy chambers
US7166528B2 (en) Methods of selective deposition of heavily doped epitaxial SiGe
US20070286956A1 (en) Cluster tool for epitaxial film formation
US20070082451A1 (en) Methods to fabricate mosfet devices using a selective deposition process
US7732269B2 (en) Method of ultra-shallow junction formation using Si film alloyed with carbon
US20080044932A1 (en) Carbon precursors for use during silicon epitaxial film formation
US11615986B2 (en) Methods and apparatus for metal silicide deposition
WO2006083693A2 (en) Etchant treatment processes for substrate surfaces and chamber surfaces
US7700424B2 (en) Method of forming an embedded silicon carbon epitaxial layer
WO2020096696A1 (en) Methods and apparatus for silicon-germanium pre-clean

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200680010817.0

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2007553243

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2006719625

Country of ref document: EP

Ref document number: 1020077019991

Country of ref document: KR