WO2006087698A3 - Logic circuit and method of logic circuit design - Google Patents

Logic circuit and method of logic circuit design Download PDF

Info

Publication number
WO2006087698A3
WO2006087698A3 PCT/IL2006/000129 IL2006000129W WO2006087698A3 WO 2006087698 A3 WO2006087698 A3 WO 2006087698A3 IL 2006000129 W IL2006000129 W IL 2006000129W WO 2006087698 A3 WO2006087698 A3 WO 2006087698A3
Authority
WO
WIPO (PCT)
Prior art keywords
connection
type transistor
logic circuit
terminal
diffusion
Prior art date
Application number
PCT/IL2006/000129
Other languages
French (fr)
Other versions
WO2006087698A2 (en
Inventor
Alexander Fish
Arkadiy Morgenshtein
Original Assignee
Technion Res & Dev Foundation
Alexander Fish
Arkadiy Morgenshtein
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Technion Res & Dev Foundation, Alexander Fish, Arkadiy Morgenshtein filed Critical Technion Res & Dev Foundation
Priority to US11/884,374 priority Critical patent/US8004316B2/en
Priority to EP06701841A priority patent/EP1854215A2/en
Publication of WO2006087698A2 publication Critical patent/WO2006087698A2/en
Publication of WO2006087698A3 publication Critical patent/WO2006087698A3/en
Priority to IL185323A priority patent/IL185323A0/en
Priority to US13/177,582 priority patent/US8188767B2/en
Priority to US13/439,949 priority patent/US20120194219A1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors

Abstract

A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a high-voltage terminal configured for connection to a high constant voltage a low-voltage terminal configured for connection to a low constant voltage, a p-type transistor, and an n-type transistor. The p-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The n-type transistor has an outer diffusion connection, a gate connection, an inner diffusion connection, and a bulk connection. The first dedicated logic terminal is connected to the outer diffusion connection of the p-type transistor, the second dedicated logic terminal is connected to the outer diffusion connection of the n-type transistor, the inner diffusion connection of the p-type transistor and the inner diffusion connection of the n-type transistor is connected to form a common diffusion logic terminal, the high-voltage terminal is connected to the bulk connection of the p-type transistor, and the low-voltage terminal is connected to the bulk connection of the n-type transistor.
PCT/IL2006/000129 2005-02-16 2006-02-01 Logic circuit and method of logic circuit design WO2006087698A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US11/884,374 US8004316B2 (en) 2005-02-16 2006-02-01 Logic circuit and method of logic circuit design
EP06701841A EP1854215A2 (en) 2005-02-16 2006-02-01 Logic circuit and method of logic circuit design
IL185323A IL185323A0 (en) 2005-02-16 2007-08-16 Logic circuit and method of logic circuit design
US13/177,582 US8188767B2 (en) 2005-02-16 2011-07-07 Logic circuit and method of logic circuit design
US13/439,949 US20120194219A1 (en) 2005-02-16 2012-04-05 Logic circuit and method of logic circuit design

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US65311505P 2005-02-16 2005-02-16
US60/653,115 2005-02-16

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US11/884,374 A-371-Of-International US8004316B2 (en) 2005-02-16 2006-02-01 Logic circuit and method of logic circuit design
US13/177,582 Division US8188767B2 (en) 2005-02-16 2011-07-07 Logic circuit and method of logic circuit design

Publications (2)

Publication Number Publication Date
WO2006087698A2 WO2006087698A2 (en) 2006-08-24
WO2006087698A3 true WO2006087698A3 (en) 2006-11-02

Family

ID=36829688

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL2006/000129 WO2006087698A2 (en) 2005-02-16 2006-02-01 Logic circuit and method of logic circuit design

Country Status (3)

Country Link
US (3) US8004316B2 (en)
EP (1) EP1854215A2 (en)
WO (1) WO2006087698A2 (en)

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US8111089B2 (en) * 2009-05-28 2012-02-07 Syphermedia International, Inc. Building block for a secure CMOS logic cell library
US8239794B2 (en) * 2009-09-29 2012-08-07 International Business Machines Corporation System and method for estimating leakage current of an electronic circuit
US8516409B2 (en) * 2010-11-11 2013-08-20 International Business Machines Corporation Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor device
WO2013018061A1 (en) 2011-08-03 2013-02-07 Ben Gurion University Of The Negev Research And Development Authority Device and method for dual-mode logic
WO2013118119A1 (en) * 2012-02-09 2013-08-15 B.G. Negev Technologies & Applications Ltd. Design of dual mode logic circuits
US8595677B1 (en) * 2011-12-21 2013-11-26 Cadence Design Systems, Inc. Method and system for performing voltage-based fast electrical analysis and simulation of an electronic design
US8954917B1 (en) * 2011-12-21 2015-02-10 Cadence Design Systems, Inc. Method and system for performing fast electrical analysis and simulation of an electronic design for power gates
CN102571064B (en) * 2012-01-05 2015-09-09 福州大学 Based on the binary code-gray code converter of SET/MOS mixed structure
CN102571068B (en) * 2012-02-29 2014-04-09 福州大学 Mixed single-electron transistor/complementary metal oxide semiconductor (SET/CMOS) circuit with negative differential resistance (NDR) characteristic
US8762904B2 (en) * 2012-03-28 2014-06-24 Synopsys, Inc. Optimizing logic synthesis for environmental insensitivity
US8975952B2 (en) * 2012-11-13 2015-03-10 Honeywell International Inc. CMOS logic circuit using passive internal body tie bias
US8904322B2 (en) * 2013-03-26 2014-12-02 International Business Machines Corporation Structure for stacked CMOS circuits
US8826208B1 (en) * 2013-03-27 2014-09-02 International Business Machines Corporation Computational thermal analysis during microchip design
US9009642B1 (en) 2013-10-22 2015-04-14 International Business Machines Corporation Congestion estimation techniques at pre-synthesis stage
US9122823B2 (en) 2013-12-20 2015-09-01 International Business Machines Corporation Stacked multiple-input delay gates
US9520180B1 (en) 2014-03-11 2016-12-13 Hypres, Inc. System and method for cryogenic hybrid technology computing and memory
US10102327B2 (en) 2014-12-31 2018-10-16 Stmicroelectronics, Inc. Integrated circuit layout wiring for multi-core chips
US10097182B2 (en) 2014-12-31 2018-10-09 Stmicroelectronics, Inc. Integrated circuit layout wiring for multi-core chips
US9569570B2 (en) * 2015-04-01 2017-02-14 Freescale Semiconductor, Inc. Configurable delay cell
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WO2018015833A1 (en) * 2016-07-19 2018-01-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
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US10826498B2 (en) * 2019-03-07 2020-11-03 Purdue Research Foundation Low power logic family
US10923596B2 (en) 2019-03-08 2021-02-16 Rambus Inc. Camouflaged FinFET and method for producing same
CN110995238B (en) * 2019-11-26 2023-04-25 宁波大学 Full adder based on swing recovery transmission pipe logic
CN111654280B (en) * 2020-05-08 2023-09-22 深圳市元视芯智能科技有限公司 One-bit full adder based on three-input TFET device
CN113395067B (en) * 2021-05-12 2022-04-08 宁波大学科学技术学院 Logic gate circuit based on MOS tube stacking extension structure

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Also Published As

Publication number Publication date
US8188767B2 (en) 2012-05-29
US8004316B2 (en) 2011-08-23
US20120194219A1 (en) 2012-08-02
US20120005639A1 (en) 2012-01-05
WO2006087698A2 (en) 2006-08-24
EP1854215A2 (en) 2007-11-14
US20100231263A1 (en) 2010-09-16

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