WO2006102182A2 - Process for electroless copper deposition - Google Patents

Process for electroless copper deposition Download PDF

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Publication number
WO2006102182A2
WO2006102182A2 PCT/US2006/009920 US2006009920W WO2006102182A2 WO 2006102182 A2 WO2006102182 A2 WO 2006102182A2 US 2006009920 W US2006009920 W US 2006009920W WO 2006102182 A2 WO2006102182 A2 WO 2006102182A2
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WO
WIPO (PCT)
Prior art keywords
feature
copper
leveler
ruthenium
layer
Prior art date
Application number
PCT/US2006/009920
Other languages
French (fr)
Other versions
WO2006102182A3 (en
Inventor
Dmitry Lubomirsky
Timothy W. Weidman
Arulkumar Shanmugasundram
Nicolay Y. Kovarsky
Kapila Wijekoon
Schubert S. Chu
Frederick C. Wu
Kavita Shah
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Applied Materials, Inc.
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Application filed by Applied Materials, Inc. filed Critical Applied Materials, Inc.
Publication of WO2006102182A2 publication Critical patent/WO2006102182A2/en
Publication of WO2006102182A3 publication Critical patent/WO2006102182A3/en

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1603—Process or apparatus coating on selected surface areas
    • C23C18/1607—Process or apparatus coating on selected surface areas by direct patterning
    • C23C18/1608—Process or apparatus coating on selected surface areas by direct patterning from pretreatment step, i.e. selective pre-treatment
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601—Process or apparatus
    • C23C18/1633—Process of electroless plating
    • C23C18/1646—Characteristics of the product obtained
    • C23C18/165—Multilayered product
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/18—Pretreatment of the material to be coated
    • C23C18/1851—Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material
    • C23C18/1872—Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material by chemical pretreatment
    • C23C18/1875—Pretreatment of the material to be coated of surfaces of non-metallic or semiconducting in organic material by chemical pretreatment only one step pretreatment
    • C23C18/1882—Use of organic or inorganic compounds other than metals, e.g. activation, sensitisation with polymers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31—Coating with metals
    • C23C18/32—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron
    • C23C18/34—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron using reducing agents
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76874—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Definitions

  • Embodiments of the invention generally relate to methods for depositing materials within a feature, and more specifically to methods for depositing a seed layer prior to filling a contact plug with a copper-containing material by an electroless deposition process.
  • VLSI very large scale integration
  • ULSI ultra large scale integration
  • VLSI very large scale integration
  • ULSI ultra large scale integration
  • the multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is very important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates.
  • Copper has a lower electrical resistivity (about 1.7 ⁇ -cm compared to about 3.1 ⁇ -cm for aluminum), a higher current carrying capacity, and significantly higher electromigration resistance than aluminum. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure form.
  • Electroless deposition processes unlike electroplating processes, utilize autocatalyzed chemical deposition instead of an applied current to induce chemical reduction.
  • An electroless deposition process typically involves exposing a substrate to a solution by either immersing the substrate into a bath or spraying the solution over the substrate.
  • An electroless deposition process of a copper-containing material within nanotechnology requires a surface capable of electron transfer for nucleation of the copper material to occur over the surface, such as a catalytic seed layer.
  • Non-metallic surfaces and oxidized surfaces are examples of surfaces which usually do not support electron transfer.
  • a barrier layer containing tantalum, tantalum nitride, titanium, or titanium nitride may provide for a poor nucleation surface to a subsequently deposited copper-containing material. Native oxides that are easily formed on the barrier layer may cause the poor nucleation.
  • An electroless deposition process may utilize a seed layer as both a catalytic surface as well as an adhesion surface.
  • a seed layer may serve as a surface capable of electron transfer during an electroless deposition process to deposit copper-containing material. However, if there are discontinuities in the seed layer across the surface, then a subsequently deposited copper-containing layer may not form uniformly to cover the seed layer.
  • a seed layer may also function as an adhesion layer to the underlying barrier layer or contact surface. For example, a copper layer deposited on a tantalum nitride barrier layer without an intermediate adhesion seed layer is easily peeled away during a standard tape test.
  • a method for forming a conductive material within a feature on a substrate includes selectively depositing a seed layer onto a bottom surface of a feature on a substrate during a collimated physical vapor deposition (PVD) process, and depositing a copper- containing layer on the seed layer to fill the feature during an electroless deposition process.
  • PVD physical vapor deposition
  • the sidewalls of the feature are maintained substantially free of the seed metal during the collimated PVD process.
  • the seed layer may contain copper, ruthenium, cobalt, tantalum, titanium, tungsten, rhenium, palladium, platinum, nickel, alloys thereof, or combinations thereof.
  • the seed metal is deposited on a barrier layer that contains tantalum, tantalum nitride, tantalum silicon nitride, titanium, titanium nitride, titanium silicon nitride, ruthenium, tungsten, tungsten nitride, alloys thereof, derivatives thereof, or combinations thereof.
  • the seed metal is deposited on a tantalum nitride barrier layer.
  • the seed metal is deposited onto contact surfaces.
  • An electroless solution used during the electroless deposition process, may contain a copper source and at least one additive, such as an accelerator, a suppressor, or a leveler.
  • the accelerator may be a sulfur-based compound, such as bis(3-sulfopropyl) disulfide, 3-mercapto-1 -propane sulfonic acid, or derivatives thereof.
  • the suppressor may include polyethylene glycol, polypropylene glycol, polyoxyethylene-polyoxypropylene copolymer, or derivatives thereof.
  • the leveler may be an alkylpolyimine compound or an organic sulfonate compound, such as 1- (2-hydroxyethyl)-2-imidazolidinethione (HIT), 4-mercaptopyridine, 2- mercaptothiazoline, ethylene thiourea, thiourea, or derivatives thereof.
  • HIT 1- (2-hydroxyethyl)-2-imidazolidinethione
  • the concentration of the leveler is adjusted to control the angle in which the surface of a copper-containing layer adjoins the sidewall of a feature.
  • the angle is usually maintained less than 90° from the sidewall, while filling the feature during the deposition process.
  • the angle is maintained within a range from about 5° to about 45°.
  • a method for forming a conductive material within a feature on a substrate includes depositing a seed layer by a PVD process onto a barrier layer disposed on a substrate containing a feature. The method further provides plasma etching a bottom surface of the feature to expose a conductive underlayer while removing a portion of the seed layer and the barrier layer, and depositing a copper-containing layer on the conductive underlayer while filling the feature during an electroless deposition process.
  • a method for forming a conductive material within a feature on a substrate includes depositing a seed layer onto a barrier layer within a feature that contains sidewalls and a bottom, and depositing a copper-containing layer on the seed layer by an electroless deposition process.
  • the electroless deposition process utilizes a deposition solution containing a leveler at a concentration to form a convexed or concaved copper surface.
  • the copper surface adjoins the sidewall of the feature at an angle less than 90° from the sidewall, and preferably less than about 45°.
  • a method for forming a conductive material within a feature on a substrate includes depositing a ruthenium seed layer selectively on a contact surface at the bottom of a feature on a substrate by a vapor deposition process, and depositing a copper- containing layer on the ruthenium seed layer while filling the feature during an electroless deposition process.
  • the method further includes maintaining the sidewalls of the feature substantially free of the ruthenium seed layer during the vapor deposition process.
  • the ruthenium seed layer is formed from ruthenium tetroxide during a vapor deposition process.
  • a ruthenium oxide layer is initially deposited and subsequently reduced to form the ruthenium seed layer.
  • ruthenium oxide is concurrently reduced and deposited to form the ruthenium seed layer.
  • a method for forming a conductive material within a feature on a substrate includes exposing a copper-containing surface within the feature to a process gas containing ruthenium tetroxide to form a ruthenium-containing layer thereon and depositing a copper-containing layer to fill the feature during an electroless deposition process.
  • a ruthenium oxide layer is formed on the copper-containing surface and subsequently exposed to a reductant to form the ruthenium-containing layer.
  • the ruthenium oxide layer is concurrently reduced and deposited to form the ruthenium-containing layer. Thereafter, the copper-containing layer is deposited on the ruthenium-containing layer while filling the feature during an electroless deposition process.
  • a method for forming a conductive material within a feature on a substrate includes selectively depositing a seed layer onto a barrier layer within the feature by a collimated PVD process.
  • the sidewalls of the feature remain substantially free of the seed layer during the collimated PVD process while the seed layer is selectively deposited on the bottom surface of the feature.
  • the method further includes depositing a copper-containing layer on the seed layer while filling the feature during an electroless deposition process.
  • the seed layer may contain copper, ruthenium, cobalt, tantalum, titanium, tungsten, rhenium, palladium, platinum, nickel, alloys thereof, or combinations thereof.
  • a method for forming a conductive material within a feature on a substrate includes depositing a barrier layer within the feature and plasma etching the bottom surface of the feature to expose a contact surface while removing a portion of the barrier layer. The method further includes exposing the contact surface to a process gas containing ruthenium tetroxide to form a ruthenium-containing layer thereon, and filling the feature with a copper-containing layer during an electroless deposition process.
  • Figures 1A-1E illustrate schematic cross-sectional views of integrated circuits formed by deposition processes described within embodiments herein;
  • Figures 2A-2D illustrate schematic cross-sectional views of integrated circuits formed by other deposition processes described within embodiments herein;
  • Figures 3A-3D illustrate schematic cross-sectional views of integrated circuits formed by other deposition processes described within embodiments herein;
  • Figures 4A-4D illustrate schematic cross-sectional views of integrated circuits formed by other deposition processes described within embodiments herein.
  • Embodiments of the invention provide methods for forming conductive materials within an aperture of a feature on a substrate surface.
  • the method provides depositing a seed layer within the feature by a vapor deposition process.
  • the seed layer may contain copper, ruthenium, cobalt, tantalum, titanium, tungsten, rhenium, palladium, platinum, nickel, alloys thereof, or combinations thereof.
  • the feature may be bottom up filled with a copper-containing material during an electroless deposition process.
  • the electroless deposition process may employ an innovative copper deposition solution to ensure that features are free of defects, such as voids or seams.
  • the seed layer may be deposited directly onto a contact surface or on a barrier layer.
  • the seed layer is selectively deposited by a collimated physical vapor deposition (PVD) process on the bottom surface of the feature while maintaining the sidewalls of the feature substantially free of the seed material.
  • the seed layer is conformably deposited across the substrate surface and features therein by a PVD process. Subsequently, the bottom surfaces of the features are plasma etched to expose an underlying contact surface while removing a portion of the seed layer and underlying layer.
  • a ruthenium seed layer is deposited on an exposed contact surface within a feature.
  • the ruthenium seed layer is formed by initially depositing a ruthenium oxide layer on the contact surface during an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process utilizing the chemical precursor ruthenium tetroxide.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the ruthenium oxide layer may be chemically reduced to form a ruthenium-containing layer either during the vapor deposition process or thereafter.
  • an electroless solution containing a copper source and at least one additive may be used during the electroless deposition process.
  • the additives include an accelerator, a suppressor, or a leveler.
  • the accelerator may be a sulfur-based compound, such as bis(3-sulfopropyl) disulfide, 3- mercapto-1 -propane sulfonic acid, derivatives thereof, or combinations thereof.
  • the suppressor may include polyethylene glycol, polypropylene glycol, polyoxyethylene- polyoxypropylene copolymer, or derivatives thereof.
  • the leveler may be an alkylpolyimine compound or an organic sulfonate compound, such as 1-(2- hydroxyethyl)-2-imidazolidinethione (HIT), 4-mercaptopyridine, 2- mercaptothiazoline, ethylene thiourea, thiourea, or derivatives thereof.
  • HIT 1-(2- hydroxyethyl)-2-imidazolidinethione
  • the leveler concentration may be adjusted to control the angle that the surface of the copper- containing layer meets or adjoins the sidewall of the feature. The angle is usually maintained less than 90° from the sidewall while filling the feature during the electroless deposition process.
  • Figure 1A illustrates a cross-sectional view of substrate 100 containing dielectric layer 102 and apertures 103 formed therein.
  • Apertures 103 may include features, such as vias, trenches, or contact holes.
  • Barrier layer 104 deposited on substrate 100 covers bottom surface 101 and sidewalls 105 of each aperture 103.
  • Dielectric layer 102 may contain a semiconductor material that includes silicon or silicon-containing materials, such as silicon germanium, silicon dioxide, silicon nitride, silicon on insulator (SOI), doped silicon, fluorine-doped silicate glass (FSG), silicon oxynitride, or carbon doped silicon oxides, such as SiO x Cy, for example, BLACK DIAMOND ® low-k dielectric, available from Applied Materials, Inc., located in Santa Clara, California.
  • silicon or silicon-containing materials such as silicon germanium, silicon dioxide, silicon nitride, silicon on insulator (SOI), doped silicon, fluorine-doped silicate glass (FSG), silicon oxynitride, or carbon doped silicon oxides, such as SiO x Cy, for example, BLACK DIAMOND ®
  • apertures 103 containing sidewalls 105 may be formed in dielectric layer 102 by techniques well known in the art, such as a mask and etch process. In one example, apertures 103 may be formed to reveal conductive contacts (not shown) within substrate 100.
  • Barrier layer 104 may be deposited by a vapor deposition process, such as a PVD process, an ALD process, a CVD process, an electroless deposition process, or combinations thereof.
  • Barrier layer 104 may contain a single layer of one material or multiple layers of varying materials.
  • Barrier layer 104 may contain tantalum, tantalum nitride, tantalum silicon nitride, titanium, titanium nitride, titanium silicon nitride, ruthenium, tungsten, tungsten nitride, alloys thereof, derivatives thereof, or combinations thereof. Examples provide barrier layer 104 containing tantalum and/or tantalum nitride.
  • barrier layer 104 is formed by depositing a tantalum layer by a PVD process onto a tantalum nitride layer deposited by an ALD process. In another example, barrier layer 104 is formed by depositing a tantalum layer by a PVD process onto a tantalum nitride layer deposited by a PVD process. In another example, barrier .layer 104 is formed by depositing a tantalum layer by an ALD process onto a tantalum nitride layer deposited by an ALD process.
  • Figure 1 B depicts seed layer 110 deposited on substrate 100. Seed layer 110 is selectively deposited onto barrier layer 104 at bottom surfaces 101 of apertures 103 and across field 109 of substrate 100 by a collimated PVD process.
  • Seed layer 110 contains a metal selected from copper, ruthenium, cobalt, tantalum, titanium, tungsten, rheniur ⁇ , palladium, platinum, nickel, alloys thereof, or combinations thereof.
  • a PVD process deposits sputtered target atoms on the barrier layer 104 to form a continuous seed layer 110.
  • Use of a vacuum deposition process, such as a PVD deposition process provides for a strong interfacial bond between seed layer 110 and barrier layer 104, and thus improves adhesion between the layers.
  • seed layer 110 provides a catalytic surface to subsequently form copper-containing layer 120 thereon.
  • Seed layer 110 may have a thickness within a range from about a single atomic layer to about 50 A. Seed layer 110 may be discontinuous, but preferably continuous across bottom surfaces 101 of apertures 103.
  • argon is admitted into the process chamber containing substrate 100 and the power supply is turned "on" to form an argon plasma. Positive argon ions thereby are generated, and a target of selected material is biased negatively relative to the grounded shield. These positively charged argon ions are attracted to the negatively charged target, and strike the target with sufficient energy to cause target atoms to be sputtered from the target. The sputtered atoms that strike substrate 100 are deposited on barrier layer 104 to form seed layer 110 of the target material.
  • the PVD process is typically performed in a chamber having pressure within a range from about 0.1 mTorr to about 2.0 mTorr.
  • the power applied to the target may be, for example, about 18 kW and the RF bias signal applied to the pedestal containing substrate 100 may be about 250 W or less.
  • Seed layer 110 may contain a variety of metals deposited by PVD processes utilizing targets or sources composed of copper, ruthenium, cobalt, tantalum, titanium, tungsten, rhenium, palladium, platinum, nickel, alloys thereof, or combinations thereof. Seed layer 110 may be deposited by a self ionizing plasma (SIP) chamber, such as a SIP ENCORETM chamber or an ionized metal plasma (IMP) chamber, such as a VECTRA IMP SOURCE ® chamber, each available from Applied Materials, Inc., located in Santa Clara, California. Further description of the PVD chambers that may be used to deposit seed layer 110 is disclosed in commonly assigned U.S. Patent Nos.
  • SIP self ionizing plasma
  • IMP ionized metal plasma
  • Magnetrons may be utilized to produce an asymmetric magnetic field which extends deep into the plasma chamber to enhance the ionization density of the plasma, as disclosed in commonly assigned U.S. Patent No. 6,183,614, which is herein incorporated by reference in its entirety.
  • Electroless deposition is a process for depositing conductive materials over a catalytically active surface by chemical reduction in the absence of an external electric current. Electroless deposition processes selectively deposit at locations where a catalytic material already exists, such as seed layer 110. Also, electroless processes are self-perpetuating to the extent of the availability of the electroless deposition solution and other reactive conditions. Therefore, electroless deposition processes are herein discussed in context for depositing copper- containing layers throughout embodiments of the invention.
  • FIGS 1 C and 1 D illustrate copper-containing layer 120 deposited on seed layer 110 by several embodiments described herein.
  • Copper-containing layer 120 is deposited by an electroless deposition process to bottom up fill apertures 103, such as from bottom surface 101 to field 109. Apertures 103 are filled with copper-containing material while avoiding defects (e.g., seams, voids, or gaps) within copper-containing layer 120.
  • the electroless deposition process utilizes an electroless solution containing a copper source and at least one additive, such as an accelerator, a suppressor, or a leveler.
  • Figure 1 E illustrates substrate 100 lacking free space or void within aperture 103 which has been filled with copper-containing layer 120. Copper-containing layer 120 contains pure copper or a copper alloy.
  • Copper-containing layer 120 may have convexed surface 126 (Figure 1C) or concaved surface 128 ( Figure 1 D).
  • the surface of copper-containing layer 120 adjoins sidewall 105 at vertex 125 or vertex 127 having an angle a of less than 90° from sidewall 105.
  • Angle a is typically within a range from about 5° to about 45° and is adjusted proportionally by the leveler concentration within the electroless solution. In one embodiment, depicted in Figure 1C, angle a is less than 90° from sidewall 105 while vertex 125 of angle a is below point 122 at the center highest portion of convexed surface 126.
  • angle a may also be less than 90° from sidewall 105 while vertex 127 of angle a is above point 122 at the center lowest portion of concaved surface 128. Angle a is preferably maintained at an angle having an absolute value within a range from about 5° to about 45° during the electroless deposition process to minimize or exclude defects forming within copper-containing layer 120 while promoting a bottom up growth. In one embodiment, angle a may have an angle of less than 90° from sidewall 105, such as within a range from about 5° to about 60°, preferably, from about 5° to about 45°, and more preferably, from about 5° to about 30°.
  • the electroless deposition solution is an aqueous solution that contains a copper source, a reductant, a complexing agent, a pH adjusting agent, additives (e.g., levelers) and an optional surfactant used as a wetting agent.
  • Levelers within the electroless solution are used to achieve different deposition thickness as a function of leveler concentration and feature geometry by controlling angle a while depositing copper-containing layer 120.
  • the electroless deposition solution may contain a leveler at concentration within a range from about 20 parts per billion (ppb) to about 600 parts per million (ppm), preferably, from about 100 ppb to about 100 ppm.
  • levelers examples include, but are not limited to, alkylpolyimines and organic sulfonates, such as 1-(2- hydroxyethyl)-2-imidazolidinethione (HIT), 4-mercaptopyridine, 2- mercaptothiazoline, ethylene thiourea, thiourea, or derivatives thereof.
  • HIT 1-(2- hydroxyethyl)-2-imidazolidinethione
  • 4-mercaptopyridine 2- mercaptothiazoline
  • ethylene thiourea thiourea
  • thiourea or derivatives thereof.
  • the electroless deposition solution may contain brighteners or accelerators and suppressors as alternative additives to provide further control of the deposition process. Accelerators help to provide a smoothly deposited surface of the copper-containing layer 120.
  • the electroless deposition solution may contain an accelerator at a concentration within a range from about 20 ppb to about 600 ppm, preferably, from about 100 ppb to about 100 ppm.
  • Accelerators that are useful in an electroless solution for depositing copper-containing layer 120 may include sulfur-based compounds such as bis(3-sulfopropyl) disulfide (SPS), 3-mercapto-1 - propane sulfonic acid (MPSA), aminoethane sulfonic acids, thiourea, derivatives thereof, or combinations thereof.
  • Suppressors are used to suppress copper deposition by initially adsorbing onto underlying catalytic surfaces (e.g., seed layer 110) and therefore blocking access to the catalyst of the reaction.
  • Suppressors may include polyethylene glycol (PEG), polypropylene glycol (PPG), polyoxyethylene- polyoxypropylene copolymer (POCP), benzotriazole (BTA), dipyridyl, dimethyl dipyridyl, derivatives thereof, or combinations thereof.
  • the electroless deposition solution may contain a suppressor at a concentration within a range from about 20 ppb to about 600 ppm, preferably, from about 100 ppb to about 100 ppm.
  • Copper sources provide copper ions (e.g., Cu 1+ or Cu 2+ ) dissolved within the electroless solution to be reduced out as the deposited copper-containing material.
  • Useful copper sources include copper sulfate, copper chloride, copper acetate, copper phosphate, derivatives thereof, hydrates thereof, or combinations thereof.
  • the electroless deposition solution may contain a copper source at a concentration within a range from about 5 mM to about 100 mM, preferably, from about 25 mM to about 75 mM.
  • Reductants provide electrons to induce chemical reduction of the copper ions that form and deposit the copper-containing material.
  • Reductants may include organic reductants (e.g., formaldehyde or glyoxylic acid), hydrazine, organic hydrazines (e.g., methyl hydrazine), hypophosphite sources (e.g., hypophosphorous acid (H 3 PO 2 ), ammonium hypophosphite ((NH 4 ) 4-x H ⁇ PO 2 ) or salts thereof), borane sources (e.g., dimethylamine borane complex ((CHa) 2 NHeBH 3 ), DMAB), trimethylamine borane complex ((CH 3 ) 3 N «BH 3 ), TMAB), terf-butylamine borane complex ( 1 BuNH 2 ⁇ BH 3 ), tetrahydrofuran borane complex (THF*BH 3 ), pyridine borane complex (C 5 H 5 N»BH 3 ), am
  • Chelators or complexing agents are in the electroless solution to complex copper ions thereby stabilizing the solubility and reduction of copper ions.
  • Complexing agents generally may have functional groups, such as amino acids, carboxylic acids, dicarboxylic acids, polycarboxylic acids, amino acids, amines, diamines, polyamines, alkylamines, alkanolamines and alkoxyamines.
  • Useful complexing agents include citric acid, citrates, glycolic acid, glycine, malonic acid, maleic acid, lactic acid, ethylenediaminetetraacetic acid (EDTA), ethylenediamine (EDA), triethylenetetramine (TETA), diaminoethane, monoethanolamine, diethanolamine (DEA), triethanolamine (TEA), hydroxylamine hydrochloride, ammonia, ammonium chloride, derivatives thereof, salts thereof, or combinations thereof.
  • the electroless deposition solution may contain complexing agents at a concentration within a range from about 10 mM to about 2 M, preferably, from about 20 mM to about 300 mM.
  • a pH adjusting agent may be added to adjust the electroless solution to a pH value within a range from about 4 to about 14.
  • the pH adjusting agent may be an acidic compound to decrease the pH value of the electroless solution and include hydrochloric acid, sulfuric acid, phosphoric acid, derivatives thereof, or combinations thereof.
  • the pH adjusting agent may be a basic compound to increase the pH value of the electroless solution and include metal hydroxides (e.g., Cu(OH) 2 ), tetraalkylammonium hydroxides (e.g., tetramethylammonium hydroxide ((CHa) 4 NOH, TMAH) or tetraethylammonium hydroxide ((CH 3 CH 2 ) 4 NOH, TEAH)), ammonium hydroxide, DEA, TEA, derivatives thereof, or combinations thereof.
  • the pH adjusting agent may be dissolved in water prior to adjusting the pH value of the electroless solution.
  • an electroless copper solution has a pH value of greater than 7, such as within a range from about 9 to about 14, preferably, from about 10 to about 13.5, and more preferably, from about 11 to about 13.
  • an optional surfactant may be added to the electroless solution.
  • the surfactant is a wetting agent to reduce the surface tension between the plating solution and the substrate surface.
  • the electroless solution may contain a surfactant at a concentration of about 1 ,000 ppm or less, preferably, about 800 ppm or less, such as within a range from about 20 ppb to about 600 ppm.
  • the surfactant may have ionic or non-ionic characteristics.
  • a preferred surfactant includes dodecyl sulfates, such as sodium dodecyl sulfate (SDS).
  • glycol ether based surfactants e.g., polyethylene glycol or PEG-PPG-PEG
  • a glycol ether based surfactants may contain polyoxyethylene units, such as TRITON ® 100, available from Dow Chemical Company.
  • a nonylphenol ethoxylate surfactant is useful in the electroless deposition solution, such as TERGITOL ® , available from Dow Chemical Company or IGEPAL-630, available from GAF Corporation.
  • Other useful surfactants may contain phosphate units, for example, sodium poly(oxyethylene) phenyl ether phosphate, such as RHODAFAC ® RE-610, available from Rhodia, Inc.
  • the surfactants may be single compounds or a mixture of compounds of molecules containing varying length of hydrocarbon chains.
  • the electroless deposition process to deposit copper-containing layers may use either a pre-mixed electroless solution or an electroless solution formed by an in-line mixing process that combines componential solution.
  • the electroless deposition process may be conducted at a temperature within a range from about 35 0 C to about 80 0 C.
  • Platforms, systems, cells, or chambers that may be useful for conducting electroless deposition processes, as described herein for depositing copper-containing layers, are further disclosed in commonly assigned U.S. Ser. No. 10/059,572, entitled “Electroless Deposition Apparatus," filed January 28, 2002, and published as US 2003-0141018, U.S. Ser. No.
  • Figure 2A illustrates a cross-sectional view of substrate 200 containing conductive contacts 208 formed within dielectric layer 207 and capped with barrier layer 206.
  • Substrate 200 further contains barrier layer 204 disposed over dielectric layer 202 and apertures 203 formed therein.
  • Apertures 203 may include features, such as vias, trenches, or contact holes.
  • Barrier layer 204 covers sidewalls 205 and bottom surfaces 201 of apertures 203.
  • Dielectric layers 202 and 207 may contain a semiconductor material that includes silicon or silicon-containing materials such as silicon germanium, silicon dioxide, silicon nitride, SOI, doped silicon, FSG, silicon oxynitride, or carbon doped silicon oxides, such as SiO x Cy, for example, BLACK DIAMOND ® low-k dielectric, available from Applied Materials, Inc., located in Santa Clara, California.
  • Apertures 203 may be formed in dielectric layer 202 by techniques well known in the art, such as a mask and etch process.
  • Conductive contacts 208 contain a metal that includes copper, tungsten, aluminum, silver, alloys thereof, or derivatives thereof. Although not shown, conductive contacts 208 are usually encompassed by at least one barrier material to prevent diffusion of the conductive material into neighboring dielectric layer 207.
  • Barrier layer 204 may be deposited by a vapor deposition process, such as a PVD process, an ALD process, a CVD process, or combinations thereof.
  • Barrier layer 204 may contain a single layer of one material or multiple layers of different materials.
  • Barrier layers 204 and 206 may independently contain tantalum, tantalum nitride, tantalum silicon nitride, titanium, titanium nitride, titanium silicon nitride, ruthenium, tungsten, tungsten nitride, silicon nitride, alloys thereof, derivatives thereof, or combinations thereof.
  • barrier layer 204 contains tantalum and/or tantalum nitride.
  • barrier layer 204 is formed by depositing a tantalum layer by a PVD process onto a tantalum nitride layer deposited by an ALD process. In another example, barrier layer 204 is formed by depositing a tantalum layer by a PVD process onto a tantalum nitride layer deposited by a PVD process. In another example, barrier layer 204 is formed by depositing a tantalum layer by an ALD process onto a tantalum nitride layer deposited by an ALD process.
  • FIG. 2B depicts seed layer 210 deposited on substrate 200.
  • Seed layer 210 is deposited onto barrier layer 204 including bottom surfaces 201 and sidewalls 205 of apertures 203 and across field 209 of substrate 200 by a PVD process.
  • seed layer 210 may be deposited by an ALD process or a CVD process.
  • Seed layer 210 may contain copper, ruthenium, cobalt, tantalum, titanium, tungsten, rhenium, palladium, platinum, nickel, alloys thereof, or combinations thereof.
  • the PVD process deposits sputtered target atoms on the barrier layer 204 to form a continuous seed layer 210.
  • seed layer 210 provides a catalytic surface to form copper-containing layer 220 thereon.
  • Seed layer 210 may be formed having a thickness within a range from about a single atomic layer to about 50 A. Seed layer 210 may be discontinuous, but preferably continuous across barrier layer 204.
  • argon is admitted into the process chamber containing substrate 200 and the power supply is turned "on" to form an argon plasma. Positive argon ions thereby are generated, and a target of selected material is biased negatively relative to the grounded shield. These positively charged argon ions are attracted to the negatively charged target, and strike the target with sufficient energy to cause target atoms to be sputtered from the target. The sputtered atoms that strike substrate 200 are deposited on barrier layer 204 to form seed layer 210 of the target material.
  • the PVD process is typically performed in a chamber at a pressure within a range from about 0.1 mTorr to about 2.0 mTorr.
  • the power applied to the target may be, for example, about 18 kW and the RF bias signal applied to the pedestal containing substrate 200 may be about 250 W or less.
  • Seed layer 210 may contain a variety of metals deposited by PVD processes utilizing targets or sources composed of copper, ruthenium, cobalt, tantalum, titanium, tungsten, rhenium, palladium, platinum, nickel, alloys thereof, or combinations thereof. Seed layer 210 may be deposited by a self ionizing plasma (SIP) chamber, such as a SIP ENCORETM chamber or an ionized metal plasma (IMP) chamber, such as a VECTRA IMP SOURCE ® chamber, each available from Applied Materials, Inc., located in Santa Clara, California. Magnetrons may be utilized to produce an asymmetric magnetic field which extends deep into the plasma chamber to enhance the ionization density of the plasma.
  • SIP self ionizing plasma
  • IMP ionized metal plasma
  • FIG. 2C depicts substrate 200 after being exposed to a plasma etch process to increase the depth of apertures 203 and reveal contacts 208.
  • Plasma etch processes may include a re-sputter process conducted in a PVD chamber as described herein or in a process chamber equipped with a remote plasma system (RPS) or a remote plasma clean (RPC) unit that is adapted to perform a dry etch process.
  • a plasma etch process may be performed in a DPS ® CENTURA ® etch chamber or an E-MAX ® CENTURA ® etch chamber available from Applied Materials, Inc., located in Santa Clara, California.
  • Material from seed layer 210 and barrier layer 204 at bottom surface 201 of apertures 203 is removed during the plasma etch process.
  • Material from dielectric layer 202 and barrier layer 206 that is aligned between apertures 203 and contacts 208 is also removed during the plasma etch process.
  • the plasma etch process is performed by flowing an inert gas (e.g., argon) into a PVD chamber and striking a plasma.
  • the PVD chamber may be maintained at a pressure within a range from about 0.5 mTorr to about 30 mTorr.
  • the target, the pedestal, and the coil are suitably biased to generate a plasma within the chamber.
  • a power signal may be applied to the coil via the RF power supply, little or no power may be applied to the target by the DC power supply and a negative bias may be applied to the pedestal (e.g., via the RF power supply) containing substrate 200.
  • the RF power signal applied to the coil causes argon atoms within the chamber to ionize and form a plasma.
  • a negative bias may be created between the pedestal and the plasma.
  • the negative bias between the pedestal and the plasma causes argon ions to accelerate toward the pedestal and substrate 200 supported thereon. Accordingly, substrate 200 is sputter-etched by the argon ions.
  • the argon ions strike substrate 200 substantially perpendicularly.
  • the high ion density generated by the PVD chamber typically greater than 10 10 , 10 11 or 10 12 ions/cm 3 , may increase the anisotropic nature of the sputter-etch process.
  • Such a high degree of anisotropy is especially beneficial, and in some cases essential, to form narrow width, high aspect ratio features (e.g., aperture feature having aspect ratios of about 4:1 or greater and/or apertures widths of about 65 nm or less).
  • sputter etching is performed within a PVD chamber at a pressure within a range from about 0.5 mTorr to about 30 mTorr, a pedestal bias within a range from about 400 W to about 1 ,000 W at about 13.56 MHz, a coil power within a range from about 1 kW to about 5 kW at about 2 MHz, a target power of less than about 500 W, and a target/substrate spacing of about 400 mm.
  • a plasma etch process is conducted in an ALD chamber or a CVD chamber equipped with an RPC unit.
  • the RPC unit generates and emits a plasma (e.g., argon plasma) into the deposition chamber to remove material from the substrate 200.
  • a plasma e.g., argon plasma
  • a single process chamber e.g., PVD, ALD or CVD chamber
  • the deposition of barrier layer 204, the deposition of seed layer 210, and the plasma etch of substrate 200 may be performed independently within individual process chambers.
  • Figure 2D illustrates copper-containing layer 220 deposited on seed layer 210 by an electroless deposition process which fills apertures 203 from the bottom up. Apertures 203 are filled with copper-containing material while avoiding defects (e.g., seams, voids, or gaps) within copper-containing layer 220.
  • the electroless deposition process utilizes an electroless solution containing a copper source and at least one additive, such as an accelerator, a suppressor, a leveler and combinations thereof.
  • Copper-containing layer 220 contains copper or a copper alloy and is deposited according to electroless deposition processes and solutions previously discussed that may be used to form copper-containing layer 120.
  • copper-containing layer 220 may have a convexed copper surface or a concaved copper surface, as described similarly for copper-containing layer 120 having convexed surface 126 ( Figure 1C) or concaved surface 128 ( Figure 1 D).
  • the convexed/concaved copper surfaces may adjoin sidewalls 205 at an angle of less than 90° from sidewall 205, such as within a range from about 5° to about 60°, preferably, from about 5° to about 45°, and more preferably, from about 5° to about 30°.
  • Figures 3A-3D and 4A-4D illustrate cross- sectional views of substrates 300 and 400 during deposition processes to form conductive materials thereon.
  • the deposition processes include forming a ruthenium seed layer on the surface of a conductive contact within a feature.
  • the ruthenium seed layer is formed by a vapor deposition process utilizing ruthenium tetroxide (RuO 4 ) as a precursor.
  • RuO 4 ruthenium tetroxide
  • a ruthenium oxide layer may be deposited and subsequently and/or concurrently chemically reduced to form the ruthenium seed layer.
  • a copper- containing layer is deposited by an electroless deposition process to fill the feature.
  • Figure 3A illustrates a cross-sectional view of substrate 300 containing conductive contacts 308 formed within dielectric layer 307, capped with barrier layer 306 and dielectric layer 302 disposed thereon.
  • Features, such as vias, trenches or apertures 303, are formed within substrate 300 to expose contacts 308.
  • Apertures 303 further contain sidewalls 305.
  • Figure 3B depicts barrier layer 304 selectively deposited on sidewalls 305 of apertures 303 and across the field of substrate 300 by a vapor deposition process, while not deposited on the surfaces of conductive contacts 308.
  • Barrier layer 304 may be selectively deposited by a vapor deposition process, such as an ALD process, a CVD process, a PVD process, or a combination thereof.
  • barrier layer 304 is formed by depositing a tantalum nitride layer by a selective ALD process.
  • the selective ALD process may include pretreatment of substrate 300 to form a sacrificial layer on the surface of conductive contacts 308.
  • the sacrificial layer may be etched away by one of the ALD precursors.
  • the sacrificial layer may be removed from the surface of conductive contacts 308 by an etch process, such as a plasma etch process described herein.
  • Figure 4A illustrates a cross-sectional view of substrate 400 containing conductive contacts 408 formed within dielectric layer 407 and capped by barrier layer 406.
  • Substrate 400 further contains barrier layer 404 disposed over dielectric layer 402 containing features, such as vias, trenches, or apertures 403, formed therein.
  • Barrier layer 404 and covers sidewalls 405 and bottom surfaces 401 of apertures 403.
  • FIG. 4B depicts substrate 400 after being exposed to a plasma etch process to increase the depth of apertures 403 and reveal contacts 408.
  • Plasma etch processes may include a re-sputter process conducted in a PVD chamber as described herein or in any process chamber equipped with a RPS or RPC unit.
  • a plasma etch process removes a portion of material from barrier layer 404 at bottom surface 401 of apertures 403, as well portions of material from dielectric layer 402 and barrier layer 406 that are aligned between apertures 403 and contacts 408.
  • Plasma etch processes useful to expose conductive contacts 408 are further described during the process to expose conductive contacts 208 depicted in Figure 2C.
  • Dielectric layers 302, 307, 402, and 407 may contain silicon or silicon- containing materials such as silicon germanium, silicon dioxide, silicon nitride, SOI, doped silicon, FSG, silicon oxynitride, or carbon doped silicon oxides, such as SiO x Cy 1 for example, BLACK DIAMOND ® low-k dielectric, available from Applied Materials, Inc., located in Santa Clara, California.
  • Apertures 303 may be formed through dielectric layer 302 to expose contacts 308, as well as, apertures 403 may be formed through dielectric layer 402 and barrier layer 406 to expose contacts 408 by techniques well known in the art, such as a mask and etch process.
  • Barrier layers 304 and 404 may contain a single layer of one material or multiple layers of varying materials.
  • Barrier layers 304, 306, 404, and 406 may contain tantalum, tantalum nitride, tantalum silicon nitride, titanium, titanium nitride, titanium silicon nitride, ruthenium, tungsten, tungsten nitride, silicon nitride, alloys thereof, derivatives thereof, or combinations thereof.
  • barrier layers 304 and 404 contain tantalum and/or tantalum nitride.
  • Conductive contacts 308 and 408 contain copper, tungsten, aluminum, alloys thereof, or derivatives thereof. Although not shown, conductive contacts 308 and 408 are usually encompassed by at least one barrier material to prevent diffusion of conductive material into neighboring dielectric layers 307 and 407.
  • FIGS 3C and 4C illustrate cross-sectional views of substrates 300 and 400 after the formation of ruthenium seed layers 310 and 410 on conductive contacts 308 and 408.
  • Ruthenium seed layers 310 and 410 are formed by depositing ruthenium oxide onto conductive contacts 308 and 408 and subsequently and/or concurrently chemically reducing the ruthenium oxide to form a ruthenium- containing material.
  • Ruthenium-containing material may include metallic ruthenium or a ruthenium alloy.
  • Ruthenium seed layers 310 and 410 are deposited having a thickness within a range from about 1 A to about 30 A, preferably, from about 2 A to about 20 A, and more preferably, from about 3 A to about 10 A, such as about 5 A.
  • Ruthenium seed layers 310 and 410 have several characteristic properties that are useful during the process of forming conductive materials described herein. Ruthenium seed layers 310 and 410 are excellent catalytic surfaces to initiate the subsequently deposited copper-containing layers 320 and 420. Also, ruthenium- containing materials are excellent electrical conductors and therefore minimally increase the resistance throughout a conductive material, such as a contact. Further, ruthenium seed layers 310 and 410 form strong adhesion to the underlying conductive contacts 308 and 408. It is believed that this strong adhesion is in part due to the transformations that occur at the interface between seed layers 310 and 410 and conductive contacts 308 and 408.
  • conductive contacts 308 and 408 contain copper
  • the interface transforms from ruthenium oxide on copper, to ruthenium on copper oxide to ruthenium on copper during the complete reduction process. Therefore, ruthenium and copper atoms are covalently bonded at the interface to produce the utmost adhesion between two surfaces.
  • Ruthenium seed layers 310 and 410 are formed by a vapor deposition process that includes an ALD process, a CVD process, a PVD process, or combinations thereof.
  • ruthenium seed layers 310 and 410 are deposited by sequentially pulsing a ruthenium precursor (e.g., ruthenium tetroxide) and a reductant (e.g., hydrogen) during an ALD process. Thereafter, substrates 300 and 400 may be thermally processed in a reducing atmosphere, such as in an annealing chamber containing an environment of hydrogen, to further reduce any remaining ruthenium oxide to a ruthenium-containing material.
  • a ruthenium precursor e.g., ruthenium tetroxide
  • reductant e.g., hydrogen
  • Ruthenium tetroxide may be delivered to the substrate in a vapor deposition process, such as an in situ generated process.
  • ruthenium tetroxide is generated in situ by exposing a ruthenium-containing source to an oxidizing gas prior and exposing the resulting product to conductive contacts 308 and 408.
  • Ruthenium tetroxide is a strong oxidant and therefore readily reacts with any exposed copper, copper oxides, tungsten, or tungsten oxides on the surfaces of conductive contacts 308 and 408.
  • ozone gas is produced by supplying an oxygen source gas into an ozone generator.
  • the oxygen source may include oxygen (O 2 ), nitrous oxide (N 2 O), nitric oxide (NO), nitrogen dioxide (NO 2 ), or combinations thereof.
  • a 12 vol% ozone is generated by flowing oxygen through the ozone generator.
  • the oxidizing gas containing ozone may be purified when passed or bubbled through a silicon gel. Subsequently, the ozone is exposed to a metallic ruthenium source to form ruthenium tetroxide that is condensed in a cooled cold trap.
  • the ozone flow is stopped and the cold trap is purged with an inert gas (e.g., nitrogen) to rid the line of excess oxygen. Thereafter, the cold trap is warmed to a temperature to sublime the ruthenium tetroxide while a flow of inert gas is passed therethrough.
  • the vaporized ruthenium tetroxide forms a deposition gas by saturating an inert gas selected from argon, nitrogen, or helium.
  • a deposition gas containing ruthenium tetroxide is sequentially pulsed with a reductant into an ALD chamber to form a ruthenium metal layer or a ruthenium oxide layer on the underlying copper contacts.
  • the ALD process contains a consistent flow of carrier gas while the ruthenium tetroxide and the reductant are sequentially pulsed into the carrier gas.
  • the ALD process cycle contains a pulse of purge gas, a pulse of ruthenium tetroxide, a pulse of purge gas, and a pulse of the reductant.
  • the carrier gas and the purge gas may be independently selected from hydrogen, argon, nitrogen, or helium.
  • Reductants that are useful during vapor deposition process for forming ruthenium-containing materials include hydrogen, diborane, silane, disilane, phosphine, plasmas thereof, derivatives thereof, or combinations thereof.
  • a more thorough disclosure of ALD processes to deposit ruthenium- containing materials is described in commonly assigned U.S. Ser. No. 10/811 ,230, entitled, “Ruthenium Layer Formation for Copper Film Deposition,” filed March 26, 2004, and published as US 2004-0241321 , which is herein incorporated by reference.
  • the substrate may be exposed to a thermal process by heating to a temperature within a range from about 100°C to about 800 0 C, preferably, from about 200°C to about 600°C, and more preferably, from about 300°C to about 500 0 C.
  • the thermal process may be conducted in an environment containing hydrogen gas.
  • the oxygen concentration within the substrate, especially within the conductive contact and ruthenium- containing material thereon, is decreased. Any remaining ruthenium oxides and copper oxides are chemically reduced to form their respective metal.
  • a deposition gas containing ruthenium tetroxide is delivered to substrates 300 or 400.
  • Substrates 300 or 400 are maintained at a temperature of about 100 0 C during the process.
  • a ruthenium oxide layer is formed on conductive contacts 308 and 408.
  • the ruthenium oxide layer may be exposed to a reductant to form a ruthenium- containing layer.
  • the ruthenium oxide may be chemically reduced to ruthenium.
  • a ruthenium oxide layer may be exposed to a hydrogen plasma to remove the oxygen and form a metallic ruthenium-containing layer.
  • a ruthenium oxide layer is exposed to diborane during a vapor deposition process to remove oxygen and form a ruthenium-containing layer containing ruthenium boride.
  • a ruthenium oxide layer is exposed to phosphine during a vapor deposition process to remove oxygen and form ruthenium- containing layer containing ruthenium phosphide.
  • Figures 3D and 4D illustrate copper-containing layers 320 and 420 deposited on ruthenium seed layers 310 and 410 deposited during an electroless deposition process.
  • Apertures 303 and 403 are bottom up filled with copper- containing material while avoiding defects (e.g., seams, voids or gaps) within copper-containing layers 320 and 420.
  • the electroless deposition process utilizes an electroless solution containing a copper source and at least one additive, such as an accelerator, a suppressor, or a leveler. Copper-containing layers 320 and 420 contain copper or a copper alloy and are deposited according to electroless deposition processes and solutions previously discussed to form copper-containing layer 120.
  • copper-containing layers 320 and 420 have a convexed copper surface or a concaved copper surface, as described similarly for copper-containing layer 120 having convexed surface 126 ( Figure 1C) or concaved surface 128 ( Figure 1 D).
  • the convexed/concaved copper surfaces may adjoin sidewalls 305 or 405 at an angle of less than 90° from sidewall 305 or 405, such as within a range from about 5° to about 60°, preferably, from about 5° to about 45°, and more preferably, from about 5° to about 30°.
  • an electroless copper solution may be prepared combining three solutions (e.g., Solutions A, B, and C) and water.
  • Solution A may contain about 525 ml_ of TMAH (25%), about 475 ml_ of deionized water, and about 1 g/L of surfactant (e.g., PEG, PEG-PPG-PEG, TRITON ® 100, TERGITOL ® , or RHODAFAC ® RE-610).
  • surfactant e.g., PEG, PEG-PPG-PEG, TRITON ® 100, TERGITOL ® , or RHODAFAC ® RE-610.
  • Solution B may contain about 62.5 g/L of copper sulfate, about 146 g/L of EDTA, and enough TMAH to provide Solution B with a pH value of about 12.5 at about 2O 0 C.
  • Solution C may contain about 200 g/L of glyoxylic acid and enough TMAH to provide Solution C with a pH value of about 9 at about 20 0 C.
  • the copper deposition rate is increased by increasing the concentration of the glyoxylic acid.
  • Solution C may contain about 138 g/L of glyoxylic acid, about 13.5 g/L of hypophosphorous acid, and enough TMAH to provide Solution C with a pH value of about 9 at about 20 ° C.
  • a mixture is formed by adding about 10 mL of Solution A to about 70 mL of heated deionized water (about 75 0 C). Subsequently, about 10 mL of Solution C is added to the mixture, then, about 10 mL of Solution B is added to the mixture to form about 100 mL of the copper electroless deposition solution.
  • At least one leveler may be added to the copper electroless deposition solution to provide better deposition control during copper surface plating processes.
  • Leveler may be added to any of the solutions, but preferably to either Solution A or Solution C.
  • the electroless deposition solution may contain a leveler at concentration within a range from about 20 parts per billion (ppb) to about 600 parts per million (ppm), preferably, from about 100 ppb to about 100 ppm.
  • levelers examples include, but are not limited to, alkylpolyimines and organic sulfonates, such as 1-(2- hydroxyethyl)-2-imidazolidinethione (HIT), 4-mercaptopyridine, 2- mercaptothiazoline, ethylene thiourea, thiourea, or derivatives thereof.
  • HIT 1-(2- hydroxyethyl)-2-imidazolidinethione
  • 4-mercaptopyridine 2- mercaptothiazoline
  • ethylene thiourea thiourea
  • thiourea or derivatives thereof.
  • Solution A may contain about 525 mL of TMAH (25%), about 475 mL of deionized water, about 10 ppm of HIT, and about 1 g/L of surfactant.
  • Solution C may contain about 200 g/L of glyoxylic acid, about 10 ppm of HIT, and enough TMAH to provide Solution C with a pH value of about 9.
  • Solution C may contain about 138 g/L of glyoxylic acid, about 13.5 g/L of hypophosphorous acid, about 10 ppm of HIT, and enough TMAH to provide Solution C with a pH value of about 9.

Abstract

Embodiments of the invention provide methods for forming conductive materials within contact features on a substrate by depositing a seed layer within a feature and subsequently filling the feature with a copper-containing material during an electroless deposition process. In one example, a copper electroless deposition solution contains levelers to form convexed or concaved copper surfaces. In another example, a seed layer is selectively deposited on the bottom surface of the aperture while leaving the sidewalls substantially free of the seed material during a collimated PVD process. In another example, the seed layer is conformably deposited by a PVD process and subsequently, a portion of the seed layer and the underlayer are plasma etched to expose an underlying contact surface. In another example, a ruthenium seed layer is formed on an exposed contact surface by an ALD process utilizing the chemical precursor ruthenium tetroxide.

Description

PROCESS FOR ELECTROLESS COPPER DEPOSITION
BACKGROUND OF THE INVENTION Field of the Invention
[0001] Embodiments of the invention generally relate to methods for depositing materials within a feature, and more specifically to methods for depositing a seed layer prior to filling a contact plug with a copper-containing material by an electroless deposition process.
Description of the Related Art
[0002] Reliably producing nanometer-sized features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is very important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates.
[0003] As circuit densities increase, the widths of vias, apertures, trenches, contacts, and other features, as well as the dielectric layers between them, decrease to nanometer dimensions, whereas the thickness of the dielectric layers remain substantially constant. Therefore, the aspect ratios of the features increase with the duration of time. Many traditional deposition processes have difficulty filling nanometer-sized structures where the aspect ratio exceeds 4:1 , and particularly where the aspect ratio exceeds 10:1. Therefore, there is much effort directed at the formation of substantially void-free, nanometer-sized features having high aspect ratios. [0004] Currently, copper and copper alloys have become the metals of choice over aluminum for nanometer-sized interconnect technology. Copper has a lower electrical resistivity (about 1.7 μΩ-cm compared to about 3.1 μΩ-cm for aluminum), a higher current carrying capacity, and significantly higher electromigration resistance than aluminum. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure form.
[0005] Electroless deposition processes, unlike electroplating processes, utilize autocatalyzed chemical deposition instead of an applied current to induce chemical reduction. An electroless deposition process typically involves exposing a substrate to a solution by either immersing the substrate into a bath or spraying the solution over the substrate. An electroless deposition process of a copper-containing material within nanotechnology requires a surface capable of electron transfer for nucleation of the copper material to occur over the surface, such as a catalytic seed layer. Non-metallic surfaces and oxidized surfaces are examples of surfaces which usually do not support electron transfer. A barrier layer containing tantalum, tantalum nitride, titanium, or titanium nitride may provide for a poor nucleation surface to a subsequently deposited copper-containing material. Native oxides that are easily formed on the barrier layer may cause the poor nucleation.
[0006] An electroless deposition process may utilize a seed layer as both a catalytic surface as well as an adhesion surface. A seed layer may serve as a surface capable of electron transfer during an electroless deposition process to deposit copper-containing material. However, if there are discontinuities in the seed layer across the surface, then a subsequently deposited copper-containing layer may not form uniformly to cover the seed layer. A seed layer may also function as an adhesion layer to the underlying barrier layer or contact surface. For example, a copper layer deposited on a tantalum nitride barrier layer without an intermediate adhesion seed layer is easily peeled away during a standard tape test. [0007] Therefore, there exists a need to deposit a seed layer within a feature on a substrate surface prior to filling the feature with a copper-containing material by an electroless deposition process, wherein the seed layer adheres the copper- containing layer to the underlying surface and the copper-containing layer is free of defects.
SUMMARY OF THE INVENTION
[0008] In one embodiment of the invention, a method for forming a conductive material within a feature on a substrate is provided which includes selectively depositing a seed layer onto a bottom surface of a feature on a substrate during a collimated physical vapor deposition (PVD) process, and depositing a copper- containing layer on the seed layer to fill the feature during an electroless deposition process. In one example, the sidewalls of the feature are maintained substantially free of the seed metal during the collimated PVD process. The seed layer may contain copper, ruthenium, cobalt, tantalum, titanium, tungsten, rhenium, palladium, platinum, nickel, alloys thereof, or combinations thereof. In one example, the seed metal is deposited on a barrier layer that contains tantalum, tantalum nitride, tantalum silicon nitride, titanium, titanium nitride, titanium silicon nitride, ruthenium, tungsten, tungsten nitride, alloys thereof, derivatives thereof, or combinations thereof. In a preferred example, the seed metal is deposited on a tantalum nitride barrier layer. In other examples, the seed metal is deposited onto contact surfaces.
[0009] An electroless solution, used during the electroless deposition process, may contain a copper source and at least one additive, such as an accelerator, a suppressor, or a leveler. The accelerator may be a sulfur-based compound, such as bis(3-sulfopropyl) disulfide, 3-mercapto-1 -propane sulfonic acid, or derivatives thereof. The suppressor may include polyethylene glycol, polypropylene glycol, polyoxyethylene-polyoxypropylene copolymer, or derivatives thereof. The leveler may be an alkylpolyimine compound or an organic sulfonate compound, such as 1- (2-hydroxyethyl)-2-imidazolidinethione (HIT), 4-mercaptopyridine, 2- mercaptothiazoline, ethylene thiourea, thiourea, or derivatives thereof. In one example, the concentration of the leveler is adjusted to control the angle in which the surface of a copper-containing layer adjoins the sidewall of a feature. The angle is usually maintained less than 90° from the sidewall, while filling the feature during the deposition process. Preferably, the angle is maintained within a range from about 5° to about 45°.
[0010] In another embodiment of the invention, a method for forming a conductive material within a feature on a substrate is provided which includes depositing a seed layer by a PVD process onto a barrier layer disposed on a substrate containing a feature. The method further provides plasma etching a bottom surface of the feature to expose a conductive underlayer while removing a portion of the seed layer and the barrier layer, and depositing a copper-containing layer on the conductive underlayer while filling the feature during an electroless deposition process.
[0011] In another embodiment of the invention, a method for forming a conductive material within a feature on a substrate is provided which includes depositing a seed layer onto a barrier layer within a feature that contains sidewalls and a bottom, and depositing a copper-containing layer on the seed layer by an electroless deposition process. The electroless deposition process utilizes a deposition solution containing a leveler at a concentration to form a convexed or concaved copper surface. The copper surface adjoins the sidewall of the feature at an angle less than 90° from the sidewall, and preferably less than about 45°.
[0012] In another embodiment of the invention, a method for forming a conductive material within a feature on a substrate is provided which includes depositing a ruthenium seed layer selectively on a contact surface at the bottom of a feature on a substrate by a vapor deposition process, and depositing a copper- containing layer on the ruthenium seed layer while filling the feature during an electroless deposition process. The method further includes maintaining the sidewalls of the feature substantially free of the ruthenium seed layer during the vapor deposition process. In one example, the ruthenium seed layer is formed from ruthenium tetroxide during a vapor deposition process. In one example of the vapor deposition process, a ruthenium oxide layer is initially deposited and subsequently reduced to form the ruthenium seed layer. In another example of the vapor deposition process, ruthenium oxide is concurrently reduced and deposited to form the ruthenium seed layer.
[0013] In another embodiment of the invention, a method for forming a conductive material within a feature on a substrate is provided which includes exposing a copper-containing surface within the feature to a process gas containing ruthenium tetroxide to form a ruthenium-containing layer thereon and depositing a copper-containing layer to fill the feature during an electroless deposition process. In one example, a ruthenium oxide layer is formed on the copper-containing surface and subsequently exposed to a reductant to form the ruthenium-containing layer. In another example, the ruthenium oxide layer is concurrently reduced and deposited to form the ruthenium-containing layer. Thereafter, the copper-containing layer is deposited on the ruthenium-containing layer while filling the feature during an electroless deposition process.
[0014] In another embodiment of the invention, a method for forming a conductive material within a feature on a substrate is provided which includes selectively depositing a seed layer onto a barrier layer within the feature by a collimated PVD process. The sidewalls of the feature remain substantially free of the seed layer during the collimated PVD process while the seed layer is selectively deposited on the bottom surface of the feature. The method further includes depositing a copper-containing layer on the seed layer while filling the feature during an electroless deposition process. The seed layer may contain copper, ruthenium, cobalt, tantalum, titanium, tungsten, rhenium, palladium, platinum, nickel, alloys thereof, or combinations thereof.
[0015] In another embodiment of the invention, a method for forming a conductive material within a feature on a substrate is provided which includes depositing a barrier layer within the feature and plasma etching the bottom surface of the feature to expose a contact surface while removing a portion of the barrier layer. The method further includes exposing the contact surface to a process gas containing ruthenium tetroxide to form a ruthenium-containing layer thereon, and filling the feature with a copper-containing layer during an electroless deposition process.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] So that the manner in which the above recited features of the invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of the invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
[0017] Figures 1A-1E illustrate schematic cross-sectional views of integrated circuits formed by deposition processes described within embodiments herein;
[0018] Figures 2A-2D illustrate schematic cross-sectional views of integrated circuits formed by other deposition processes described within embodiments herein;
[0019] Figures 3A-3D illustrate schematic cross-sectional views of integrated circuits formed by other deposition processes described within embodiments herein; and
[0020] Figures 4A-4D illustrate schematic cross-sectional views of integrated circuits formed by other deposition processes described within embodiments herein.
DETAILED DESCRIPTION
[0021] Embodiments of the invention provide methods for forming conductive materials within an aperture of a feature on a substrate surface. In one example, the method provides depositing a seed layer within the feature by a vapor deposition process. The seed layer may contain copper, ruthenium, cobalt, tantalum, titanium, tungsten, rhenium, palladium, platinum, nickel, alloys thereof, or combinations thereof. Once the seed layer has been deposited, the feature may be bottom up filled with a copper-containing material during an electroless deposition process. The electroless deposition process may employ an innovative copper deposition solution to ensure that features are free of defects, such as voids or seams. The seed layer may be deposited directly onto a contact surface or on a barrier layer.
[0022] In one embodiment, the seed layer is selectively deposited by a collimated physical vapor deposition (PVD) process on the bottom surface of the feature while maintaining the sidewalls of the feature substantially free of the seed material. In another embodiment, the seed layer is conformably deposited across the substrate surface and features therein by a PVD process. Subsequently, the bottom surfaces of the features are plasma etched to expose an underlying contact surface while removing a portion of the seed layer and underlying layer. In another embodiment, a ruthenium seed layer is deposited on an exposed contact surface within a feature. Preferably, the ruthenium seed layer is formed by initially depositing a ruthenium oxide layer on the contact surface during an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process utilizing the chemical precursor ruthenium tetroxide. The ruthenium oxide layer may be chemically reduced to form a ruthenium-containing layer either during the vapor deposition process or thereafter.
[0023] In another embodiment, an electroless solution containing a copper source and at least one additive may be used during the electroless deposition process. The additives include an accelerator, a suppressor, or a leveler. The accelerator may be a sulfur-based compound, such as bis(3-sulfopropyl) disulfide, 3- mercapto-1 -propane sulfonic acid, derivatives thereof, or combinations thereof. The suppressor may include polyethylene glycol, polypropylene glycol, polyoxyethylene- polyoxypropylene copolymer, or derivatives thereof. The leveler may be an alkylpolyimine compound or an organic sulfonate compound, such as 1-(2- hydroxyethyl)-2-imidazolidinethione (HIT), 4-mercaptopyridine, 2- mercaptothiazoline, ethylene thiourea, thiourea, or derivatives thereof. The leveler concentration may be adjusted to control the angle that the surface of the copper- containing layer meets or adjoins the sidewall of the feature. The angle is usually maintained less than 90° from the sidewall while filling the feature during the electroless deposition process. [0024] Figure 1A illustrates a cross-sectional view of substrate 100 containing dielectric layer 102 and apertures 103 formed therein. Apertures 103 may include features, such as vias, trenches, or contact holes. Barrier layer 104 deposited on substrate 100 covers bottom surface 101 and sidewalls 105 of each aperture 103. Dielectric layer 102 may contain a semiconductor material that includes silicon or silicon-containing materials, such as silicon germanium, silicon dioxide, silicon nitride, silicon on insulator (SOI), doped silicon, fluorine-doped silicate glass (FSG), silicon oxynitride, or carbon doped silicon oxides, such as SiOxCy, for example, BLACK DIAMOND® low-k dielectric, available from Applied Materials, Inc., located in Santa Clara, California. In one example, apertures 103 containing sidewalls 105 may be formed in dielectric layer 102 by techniques well known in the art, such as a mask and etch process. In one example, apertures 103 may be formed to reveal conductive contacts (not shown) within substrate 100.
[0025] Barrier layer 104 may be deposited by a vapor deposition process, such as a PVD process, an ALD process, a CVD process, an electroless deposition process, or combinations thereof. Barrier layer 104 may contain a single layer of one material or multiple layers of varying materials. Barrier layer 104 may contain tantalum, tantalum nitride, tantalum silicon nitride, titanium, titanium nitride, titanium silicon nitride, ruthenium, tungsten, tungsten nitride, alloys thereof, derivatives thereof, or combinations thereof. Examples provide barrier layer 104 containing tantalum and/or tantalum nitride. In one example, barrier layer 104 is formed by depositing a tantalum layer by a PVD process onto a tantalum nitride layer deposited by an ALD process. In another example, barrier layer 104 is formed by depositing a tantalum layer by a PVD process onto a tantalum nitride layer deposited by a PVD process. In another example, barrier .layer 104 is formed by depositing a tantalum layer by an ALD process onto a tantalum nitride layer deposited by an ALD process.
[0026] Figure 1 B depicts seed layer 110 deposited on substrate 100. Seed layer 110 is selectively deposited onto barrier layer 104 at bottom surfaces 101 of apertures 103 and across field 109 of substrate 100 by a collimated PVD process.
Sidewalls 105 of apertures 103 remain substantially free of seed layer 110 during and after the collimated PVD process. Seed layer 110 contains a metal selected from copper, ruthenium, cobalt, tantalum, titanium, tungsten, rheniurή, palladium, platinum, nickel, alloys thereof, or combinations thereof. In one example, a PVD process deposits sputtered target atoms on the barrier layer 104 to form a continuous seed layer 110. Use of a vacuum deposition process, such as a PVD deposition process, provides for a strong interfacial bond between seed layer 110 and barrier layer 104, and thus improves adhesion between the layers. Also, seed layer 110 provides a catalytic surface to subsequently form copper-containing layer 120 thereon. Seed layer 110 may have a thickness within a range from about a single atomic layer to about 50 A. Seed layer 110 may be discontinuous, but preferably continuous across bottom surfaces 101 of apertures 103.
[0027] In one example of a collimated PVD process for depositing seed layer 110, argon is admitted into the process chamber containing substrate 100 and the power supply is turned "on" to form an argon plasma. Positive argon ions thereby are generated, and a target of selected material is biased negatively relative to the grounded shield. These positively charged argon ions are attracted to the negatively charged target, and strike the target with sufficient energy to cause target atoms to be sputtered from the target. The sputtered atoms that strike substrate 100 are deposited on barrier layer 104 to form seed layer 110 of the target material. The PVD process is typically performed in a chamber having pressure within a range from about 0.1 mTorr to about 2.0 mTorr. The power applied to the target may be, for example, about 18 kW and the RF bias signal applied to the pedestal containing substrate 100 may be about 250 W or less.
[0028] Seed layer 110 may contain a variety of metals deposited by PVD processes utilizing targets or sources composed of copper, ruthenium, cobalt, tantalum, titanium, tungsten, rhenium, palladium, platinum, nickel, alloys thereof, or combinations thereof. Seed layer 110 may be deposited by a self ionizing plasma (SIP) chamber, such as a SIP ENCORE™ chamber or an ionized metal plasma (IMP) chamber, such as a VECTRA IMP SOURCE® chamber, each available from Applied Materials, Inc., located in Santa Clara, California. Further description of the PVD chambers that may be used to deposit seed layer 110 is disclosed in commonly assigned U.S. Patent Nos. 6,784,096, 6,277,249, and 6,251 ,242, which are herein incorporated by references in their entirety. Magnetrons may be utilized to produce an asymmetric magnetic field which extends deep into the plasma chamber to enhance the ionization density of the plasma, as disclosed in commonly assigned U.S. Patent No. 6,183,614, which is herein incorporated by reference in its entirety.
[0029] Electroless deposition is a process for depositing conductive materials over a catalytically active surface by chemical reduction in the absence of an external electric current. Electroless deposition processes selectively deposit at locations where a catalytic material already exists, such as seed layer 110. Also, electroless processes are self-perpetuating to the extent of the availability of the electroless deposition solution and other reactive conditions. Therefore, electroless deposition processes are herein discussed in context for depositing copper- containing layers throughout embodiments of the invention.
[0030] Figures 1 C and 1 D illustrate copper-containing layer 120 deposited on seed layer 110 by several embodiments described herein. Copper-containing layer 120 is deposited by an electroless deposition process to bottom up fill apertures 103, such as from bottom surface 101 to field 109. Apertures 103 are filled with copper-containing material while avoiding defects (e.g., seams, voids, or gaps) within copper-containing layer 120. The electroless deposition process utilizes an electroless solution containing a copper source and at least one additive, such as an accelerator, a suppressor, or a leveler. Figure 1 E illustrates substrate 100 lacking free space or void within aperture 103 which has been filled with copper-containing layer 120. Copper-containing layer 120 contains pure copper or a copper alloy.
[0031] Copper-containing layer 120 may have convexed surface 126 (Figure 1C) or concaved surface 128 (Figure 1 D). During the electroless deposition process, the surface of copper-containing layer 120 adjoins sidewall 105 at vertex 125 or vertex 127 having an angle a of less than 90° from sidewall 105. Angle a is typically within a range from about 5° to about 45° and is adjusted proportionally by the leveler concentration within the electroless solution. In one embodiment, depicted in Figure 1C, angle a is less than 90° from sidewall 105 while vertex 125 of angle a is below point 122 at the center highest portion of convexed surface 126. In another embodiment, depicted in Figure 1 D, angle a may also be less than 90° from sidewall 105 while vertex 127 of angle a is above point 122 at the center lowest portion of concaved surface 128. Angle a is preferably maintained at an angle having an absolute value within a range from about 5° to about 45° during the electroless deposition process to minimize or exclude defects forming within copper-containing layer 120 while promoting a bottom up growth. In one embodiment, angle a may have an angle of less than 90° from sidewall 105, such as within a range from about 5° to about 60°, preferably, from about 5° to about 45°, and more preferably, from about 5° to about 30°.
[0032] The electroless deposition solution is an aqueous solution that contains a copper source, a reductant, a complexing agent, a pH adjusting agent, additives (e.g., levelers) and an optional surfactant used as a wetting agent. Levelers within the electroless solution are used to achieve different deposition thickness as a function of leveler concentration and feature geometry by controlling angle a while depositing copper-containing layer 120. The electroless deposition solution may contain a leveler at concentration within a range from about 20 parts per billion (ppb) to about 600 parts per million (ppm), preferably, from about 100 ppb to about 100 ppm. Examples of levelers that may be employed in an electroless solution include, but are not limited to, alkylpolyimines and organic sulfonates, such as 1-(2- hydroxyethyl)-2-imidazolidinethione (HIT), 4-mercaptopyridine, 2- mercaptothiazoline, ethylene thiourea, thiourea, or derivatives thereof.
[0033] The electroless deposition solution may contain brighteners or accelerators and suppressors as alternative additives to provide further control of the deposition process. Accelerators help to provide a smoothly deposited surface of the copper-containing layer 120. The electroless deposition solution may contain an accelerator at a concentration within a range from about 20 ppb to about 600 ppm, preferably, from about 100 ppb to about 100 ppm. Accelerators that are useful in an electroless solution for depositing copper-containing layer 120 may include sulfur-based compounds such as bis(3-sulfopropyl) disulfide (SPS), 3-mercapto-1 - propane sulfonic acid (MPSA), aminoethane sulfonic acids, thiourea, derivatives thereof, or combinations thereof. Suppressors are used to suppress copper deposition by initially adsorbing onto underlying catalytic surfaces (e.g., seed layer 110) and therefore blocking access to the catalyst of the reaction. Suppressors may include polyethylene glycol (PEG), polypropylene glycol (PPG), polyoxyethylene- polyoxypropylene copolymer (POCP), benzotriazole (BTA), dipyridyl, dimethyl dipyridyl, derivatives thereof, or combinations thereof. The electroless deposition solution may contain a suppressor at a concentration within a range from about 20 ppb to about 600 ppm, preferably, from about 100 ppb to about 100 ppm.
[0034] Copper sources provide copper ions (e.g., Cu1+ or Cu2+) dissolved within the electroless solution to be reduced out as the deposited copper-containing material. Useful copper sources include copper sulfate, copper chloride, copper acetate, copper phosphate, derivatives thereof, hydrates thereof, or combinations thereof. The electroless deposition solution may contain a copper source at a concentration within a range from about 5 mM to about 100 mM, preferably, from about 25 mM to about 75 mM.
[0035] Reductants provide electrons to induce chemical reduction of the copper ions that form and deposit the copper-containing material. Reductants may include organic reductants (e.g., formaldehyde or glyoxylic acid), hydrazine, organic hydrazines (e.g., methyl hydrazine), hypophosphite sources (e.g., hypophosphorous acid (H3PO2), ammonium hypophosphite ((NH4)4-xHχPO2) or salts thereof), borane sources (e.g., dimethylamine borane complex ((CHa)2NHeBH3), DMAB), trimethylamine borane complex ((CH3)3N«BH3), TMAB), terf-butylamine borane complex (1BuNH2^BH3), tetrahydrofuran borane complex (THF*BH3), pyridine borane complex (C5H5N»BH3), ammonia borane complex (NH3-BH3), borane (BH3), diborane (B2H6), derivatives thereof, complexes thereof, or combinations thereof. The electroless deposition solution may contain a reductant at a concentration within a range from about 10 mM to about 2 M, preferably, from about 20 mM to about 500 mM.
[0036] Chelators or complexing agents are in the electroless solution to complex copper ions thereby stabilizing the solubility and reduction of copper ions.
Complexing agents generally may have functional groups, such as amino acids, carboxylic acids, dicarboxylic acids, polycarboxylic acids, amino acids, amines, diamines, polyamines, alkylamines, alkanolamines and alkoxyamines. Useful complexing agents include citric acid, citrates, glycolic acid, glycine, malonic acid, maleic acid, lactic acid, ethylenediaminetetraacetic acid (EDTA), ethylenediamine (EDA), triethylenetetramine (TETA), diaminoethane, monoethanolamine, diethanolamine (DEA), triethanolamine (TEA), hydroxylamine hydrochloride, ammonia, ammonium chloride, derivatives thereof, salts thereof, or combinations thereof. The electroless deposition solution may contain complexing agents at a concentration within a range from about 10 mM to about 2 M, preferably, from about 20 mM to about 300 mM.
[0037] A pH adjusting agent may be added to adjust the electroless solution to a pH value within a range from about 4 to about 14. The pH adjusting agent may be an acidic compound to decrease the pH value of the electroless solution and include hydrochloric acid, sulfuric acid, phosphoric acid, derivatives thereof, or combinations thereof. Alternatively, the pH adjusting agent may be a basic compound to increase the pH value of the electroless solution and include metal hydroxides (e.g., Cu(OH)2), tetraalkylammonium hydroxides (e.g., tetramethylammonium hydroxide ((CHa)4NOH, TMAH) or tetraethylammonium hydroxide ((CH3CH2)4NOH, TEAH)), ammonium hydroxide, DEA, TEA, derivatives thereof, or combinations thereof. The pH adjusting agent may be dissolved in water prior to adjusting the pH value of the electroless solution. In one example, an electroless copper solution has a pH value of greater than 7, such as within a range from about 9 to about 14, preferably, from about 10 to about 13.5, and more preferably, from about 11 to about 13.
[0038] Also, an optional surfactant may be added to the electroless solution. The surfactant is a wetting agent to reduce the surface tension between the plating solution and the substrate surface. The electroless solution may contain a surfactant at a concentration of about 1 ,000 ppm or less, preferably, about 800 ppm or less, such as within a range from about 20 ppb to about 600 ppm. The surfactant may have ionic or non-ionic characteristics. A preferred surfactant includes dodecyl sulfates, such as sodium dodecyl sulfate (SDS). Other surfactants that may be used in the electroless deposition solution include glycol ether based surfactants (e.g., polyethylene glycol or PEG-PPG-PEG). For example, a glycol ether based surfactants may contain polyoxyethylene units, such as TRITON® 100, available from Dow Chemical Company. A nonylphenol ethoxylate surfactant is useful in the electroless deposition solution, such as TERGITOL®, available from Dow Chemical Company or IGEPAL-630, available from GAF Corporation. Other useful surfactants may contain phosphate units, for example, sodium poly(oxyethylene) phenyl ether phosphate, such as RHODAFAC® RE-610, available from Rhodia, Inc. The surfactants may be single compounds or a mixture of compounds of molecules containing varying length of hydrocarbon chains.
[0039] The electroless deposition process to deposit copper-containing layers may use either a pre-mixed electroless solution or an electroless solution formed by an in-line mixing process that combines componential solution. The electroless deposition process may be conducted at a temperature within a range from about 350C to about 800C. Platforms, systems, cells, or chambers that may be useful for conducting electroless deposition processes, as described herein for depositing copper-containing layers, are further disclosed in commonly assigned U.S. Ser. No. 10/059,572, entitled "Electroless Deposition Apparatus," filed January 28, 2002, and published as US 2003-0141018, U.S. Ser. No. 10/965,220, entitled, "Apparatus for Electroless Deposition," filed on October 14, 2004, and published as US 2005- 0081785, U.S. Ser. No. 10/996,342, entitled, "Apparatus for Electroless Deposition of Metals on Semiconductor Wafers," filed on November 22, 2004, and published as US 2005-0160990, U.S. Ser. No. 11/043,442, entitled, "Apparatus for Electroless Deposition of Metals on Semiconductor Wafers," filed on January 26, 2005, and published as US 2005-0263066, and U.S. Ser. No. 11/175,251 , entitled, "Apparatus for Electroless Deposition of Metals on Semiconductor Wafers," filed on July 6, 2005, and published as US 2005-0260345, which are each incorporated by reference to the extent not inconsistent with the claimed aspects and description herein.
[0040] Figure 2A illustrates a cross-sectional view of substrate 200 containing conductive contacts 208 formed within dielectric layer 207 and capped with barrier layer 206. Substrate 200 further contains barrier layer 204 disposed over dielectric layer 202 and apertures 203 formed therein. Apertures 203 may include features, such as vias, trenches, or contact holes. Barrier layer 204 covers sidewalls 205 and bottom surfaces 201 of apertures 203.
[0041] Dielectric layers 202 and 207 may contain a semiconductor material that includes silicon or silicon-containing materials such as silicon germanium, silicon dioxide, silicon nitride, SOI, doped silicon, FSG, silicon oxynitride, or carbon doped silicon oxides, such as SiOxCy, for example, BLACK DIAMOND® low-k dielectric, available from Applied Materials, Inc., located in Santa Clara, California. Apertures 203 may be formed in dielectric layer 202 by techniques well known in the art, such as a mask and etch process. Conductive contacts 208 contain a metal that includes copper, tungsten, aluminum, silver, alloys thereof, or derivatives thereof. Although not shown, conductive contacts 208 are usually encompassed by at least one barrier material to prevent diffusion of the conductive material into neighboring dielectric layer 207.
[0042] Barrier layer 204 may be deposited by a vapor deposition process, such as a PVD process, an ALD process, a CVD process, or combinations thereof. Barrier layer 204 may contain a single layer of one material or multiple layers of different materials. Barrier layers 204 and 206 may independently contain tantalum, tantalum nitride, tantalum silicon nitride, titanium, titanium nitride, titanium silicon nitride, ruthenium, tungsten, tungsten nitride, silicon nitride, alloys thereof, derivatives thereof, or combinations thereof. Preferably, barrier layer 204 contains tantalum and/or tantalum nitride. In one example, barrier layer 204 is formed by depositing a tantalum layer by a PVD process onto a tantalum nitride layer deposited by an ALD process. In another example, barrier layer 204 is formed by depositing a tantalum layer by a PVD process onto a tantalum nitride layer deposited by a PVD process. In another example, barrier layer 204 is formed by depositing a tantalum layer by an ALD process onto a tantalum nitride layer deposited by an ALD process.
[0043] Figure 2B depicts seed layer 210 deposited on substrate 200. Seed layer 210 is deposited onto barrier layer 204 including bottom surfaces 201 and sidewalls 205 of apertures 203 and across field 209 of substrate 200 by a PVD process. Alternatively, seed layer 210 may be deposited by an ALD process or a CVD process. Seed layer 210 may contain copper, ruthenium, cobalt, tantalum, titanium, tungsten, rhenium, palladium, platinum, nickel, alloys thereof, or combinations thereof. In one embodiment, the PVD process deposits sputtered target atoms on the barrier layer 204 to form a continuous seed layer 210. Use of a vacuum deposition process, such as a PVD deposition process, provides for a strong interfacial bond between seed layer 210 and the barrier layer 204, and thus improves adhesion between the layers. Also, seed layer 210 provides a catalytic surface to form copper-containing layer 220 thereon. Seed layer 210 may be formed having a thickness within a range from about a single atomic layer to about 50 A. Seed layer 210 may be discontinuous, but preferably continuous across barrier layer 204.
[0044] In one example of a PVD process for depositing seed layer 210, argon is admitted into the process chamber containing substrate 200 and the power supply is turned "on" to form an argon plasma. Positive argon ions thereby are generated, and a target of selected material is biased negatively relative to the grounded shield. These positively charged argon ions are attracted to the negatively charged target, and strike the target with sufficient energy to cause target atoms to be sputtered from the target. The sputtered atoms that strike substrate 200 are deposited on barrier layer 204 to form seed layer 210 of the target material. The PVD process is typically performed in a chamber at a pressure within a range from about 0.1 mTorr to about 2.0 mTorr. The power applied to the target may be, for example, about 18 kW and the RF bias signal applied to the pedestal containing substrate 200 may be about 250 W or less.
[0045] Seed layer 210 may contain a variety of metals deposited by PVD processes utilizing targets or sources composed of copper, ruthenium, cobalt, tantalum, titanium, tungsten, rhenium, palladium, platinum, nickel, alloys thereof, or combinations thereof. Seed layer 210 may be deposited by a self ionizing plasma (SIP) chamber, such as a SIP ENCORE™ chamber or an ionized metal plasma (IMP) chamber, such as a VECTRA IMP SOURCE® chamber, each available from Applied Materials, Inc., located in Santa Clara, California. Magnetrons may be utilized to produce an asymmetric magnetic field which extends deep into the plasma chamber to enhance the ionization density of the plasma.
[0046] Figure 2C depicts substrate 200 after being exposed to a plasma etch process to increase the depth of apertures 203 and reveal contacts 208. Plasma etch processes may include a re-sputter process conducted in a PVD chamber as described herein or in a process chamber equipped with a remote plasma system (RPS) or a remote plasma clean (RPC) unit that is adapted to perform a dry etch process. A plasma etch process may be performed in a DPS® CENTURA® etch chamber or an E-MAX® CENTURA® etch chamber available from Applied Materials, Inc., located in Santa Clara, California. Material from seed layer 210 and barrier layer 204 at bottom surface 201 of apertures 203 is removed during the plasma etch process. Material from dielectric layer 202 and barrier layer 206 that is aligned between apertures 203 and contacts 208 is also removed during the plasma etch process.
[0047] In one example, the plasma etch process is performed by flowing an inert gas (e.g., argon) into a PVD chamber and striking a plasma. The PVD chamber may be maintained at a pressure within a range from about 0.5 mTorr to about 30 mTorr. During the plasma etch process, the target, the pedestal, and the coil are suitably biased to generate a plasma within the chamber. For example, a power signal may be applied to the coil via the RF power supply, little or no power may be applied to the target by the DC power supply and a negative bias may be applied to the pedestal (e.g., via the RF power supply) containing substrate 200. The RF power signal applied to the coil causes argon atoms within the chamber to ionize and form a plasma. By adjusting the duty cycle and/or magnitude of the RF power signal applied to the pedestal, a negative bias may be created between the pedestal and the plasma. The negative bias between the pedestal and the plasma causes argon ions to accelerate toward the pedestal and substrate 200 supported thereon. Accordingly, substrate 200 is sputter-etched by the argon ions.
[0048] Under the influence of the negative bias applied to the pedestal, the argon ions strike substrate 200 substantially perpendicularly. Further, the high ion density generated by the PVD chamber, typically greater than 1010, 1011 or 1012 ions/cm3, may increase the anisotropic nature of the sputter-etch process. Such a high degree of anisotropy is especially beneficial, and in some cases essential, to form narrow width, high aspect ratio features (e.g., aperture feature having aspect ratios of about 4:1 or greater and/or apertures widths of about 65 nm or less).
[0049] Little or no material is sputtered from the target and deposits on substrate 200 during the plasma etch process, since little or no power is applied to the target {e.g., from about 0 W to about 500 W). Portions of seed layer 210, barrier layers 204 and 206, and dielectric layer 202 are removed at each bottom surface 201 of each aperture 203. In one example, sputter etching is performed within a PVD chamber at a pressure within a range from about 0.5 mTorr to about 30 mTorr, a pedestal bias within a range from about 400 W to about 1 ,000 W at about 13.56 MHz, a coil power within a range from about 1 kW to about 5 kW at about 2 MHz, a target power of less than about 500 W, and a target/substrate spacing of about 400 mm.
[0050] In another example, a plasma etch process is conducted in an ALD chamber or a CVD chamber equipped with an RPC unit. The RPC unit generates and emits a plasma (e.g., argon plasma) into the deposition chamber to remove material from the substrate 200. Therefore, a single process chamber (e.g., PVD, ALD or CVD chamber) may be used to deposit barrier layer 204 and/or seed layer 210, as well as to plasma etch substrate 200 thereafter. Alternatively, the deposition of barrier layer 204, the deposition of seed layer 210, and the plasma etch of substrate 200 may be performed independently within individual process chambers.
[0051] Figure 2D illustrates copper-containing layer 220 deposited on seed layer 210 by an electroless deposition process which fills apertures 203 from the bottom up. Apertures 203 are filled with copper-containing material while avoiding defects (e.g., seams, voids, or gaps) within copper-containing layer 220. The electroless deposition process utilizes an electroless solution containing a copper source and at least one additive, such as an accelerator, a suppressor, a leveler and combinations thereof. Copper-containing layer 220 contains copper or a copper alloy and is deposited according to electroless deposition processes and solutions previously discussed that may be used to form copper-containing layer 120. In one embodiment, copper-containing layer 220 may have a convexed copper surface or a concaved copper surface, as described similarly for copper-containing layer 120 having convexed surface 126 (Figure 1C) or concaved surface 128 (Figure 1 D). The convexed/concaved copper surfaces may adjoin sidewalls 205 at an angle of less than 90° from sidewall 205, such as within a range from about 5° to about 60°, preferably, from about 5° to about 45°, and more preferably, from about 5° to about 30°.
[0052] In alternative embodiments, Figures 3A-3D and 4A-4D illustrate cross- sectional views of substrates 300 and 400 during deposition processes to form conductive materials thereon. The deposition processes include forming a ruthenium seed layer on the surface of a conductive contact within a feature. Preferably, the ruthenium seed layer is formed by a vapor deposition process utilizing ruthenium tetroxide (RuO4) as a precursor. During the deposition process, a ruthenium oxide layer may be deposited and subsequently and/or concurrently chemically reduced to form the ruthenium seed layer. Thereafter, a copper- containing layer is deposited by an electroless deposition process to fill the feature.
[0053] Figure 3A illustrates a cross-sectional view of substrate 300 containing conductive contacts 308 formed within dielectric layer 307, capped with barrier layer 306 and dielectric layer 302 disposed thereon. Features, such as vias, trenches or apertures 303, are formed within substrate 300 to expose contacts 308. Apertures 303 further contain sidewalls 305.
[0054] Figure 3B depicts barrier layer 304 selectively deposited on sidewalls 305 of apertures 303 and across the field of substrate 300 by a vapor deposition process, while not deposited on the surfaces of conductive contacts 308. Barrier layer 304 may be selectively deposited by a vapor deposition process, such as an ALD process, a CVD process, a PVD process, or a combination thereof. In one example, barrier layer 304 is formed by depositing a tantalum nitride layer by a selective ALD process. The selective ALD process may include pretreatment of substrate 300 to form a sacrificial layer on the surface of conductive contacts 308. During the sequential cycles for depositing barrier layer 304, the sacrificial layer may be etched away by one of the ALD precursors. Alternatively, after the ALD process, the sacrificial layer may be removed from the surface of conductive contacts 308 by an etch process, such as a plasma etch process described herein.
[0055] Figure 4A illustrates a cross-sectional view of substrate 400 containing conductive contacts 408 formed within dielectric layer 407 and capped by barrier layer 406. Substrate 400 further contains barrier layer 404 disposed over dielectric layer 402 containing features, such as vias, trenches, or apertures 403, formed therein. Barrier layer 404 and covers sidewalls 405 and bottom surfaces 401 of apertures 403.
[0056] Figure 4B depicts substrate 400 after being exposed to a plasma etch process to increase the depth of apertures 403 and reveal contacts 408. Plasma etch processes may include a re-sputter process conducted in a PVD chamber as described herein or in any process chamber equipped with a RPS or RPC unit. A plasma etch process removes a portion of material from barrier layer 404 at bottom surface 401 of apertures 403, as well portions of material from dielectric layer 402 and barrier layer 406 that are aligned between apertures 403 and contacts 408. Plasma etch processes useful to expose conductive contacts 408 are further described during the process to expose conductive contacts 208 depicted in Figure 2C.
[0057] Dielectric layers 302, 307, 402, and 407 may contain silicon or silicon- containing materials such as silicon germanium, silicon dioxide, silicon nitride, SOI, doped silicon, FSG, silicon oxynitride, or carbon doped silicon oxides, such as SiOxCy1 for example, BLACK DIAMOND® low-k dielectric, available from Applied Materials, Inc., located in Santa Clara, California. Apertures 303 may be formed through dielectric layer 302 to expose contacts 308, as well as, apertures 403 may be formed through dielectric layer 402 and barrier layer 406 to expose contacts 408 by techniques well known in the art, such as a mask and etch process.
[0058] Barrier layers 304 and 404 may contain a single layer of one material or multiple layers of varying materials. Barrier layers 304, 306, 404, and 406 may contain tantalum, tantalum nitride, tantalum silicon nitride, titanium, titanium nitride, titanium silicon nitride, ruthenium, tungsten, tungsten nitride, silicon nitride, alloys thereof, derivatives thereof, or combinations thereof. In one example, barrier layers 304 and 404 contain tantalum and/or tantalum nitride. Conductive contacts 308 and 408 contain copper, tungsten, aluminum, alloys thereof, or derivatives thereof. Although not shown, conductive contacts 308 and 408 are usually encompassed by at least one barrier material to prevent diffusion of conductive material into neighboring dielectric layers 307 and 407.
[0059] Figures 3C and 4C illustrate cross-sectional views of substrates 300 and 400 after the formation of ruthenium seed layers 310 and 410 on conductive contacts 308 and 408. Ruthenium seed layers 310 and 410 are formed by depositing ruthenium oxide onto conductive contacts 308 and 408 and subsequently and/or concurrently chemically reducing the ruthenium oxide to form a ruthenium- containing material. Ruthenium-containing material may include metallic ruthenium or a ruthenium alloy. Ruthenium seed layers 310 and 410 are deposited having a thickness within a range from about 1 A to about 30 A, preferably, from about 2 A to about 20 A, and more preferably, from about 3 A to about 10 A, such as about 5 A.
[0060] Ruthenium seed layers 310 and 410 have several characteristic properties that are useful during the process of forming conductive materials described herein. Ruthenium seed layers 310 and 410 are excellent catalytic surfaces to initiate the subsequently deposited copper-containing layers 320 and 420. Also, ruthenium- containing materials are excellent electrical conductors and therefore minimally increase the resistance throughout a conductive material, such as a contact. Further, ruthenium seed layers 310 and 410 form strong adhesion to the underlying conductive contacts 308 and 408. It is believed that this strong adhesion is in part due to the transformations that occur at the interface between seed layers 310 and 410 and conductive contacts 308 and 408. For example, when conductive contacts 308 and 408 contain copper, the interface transforms from ruthenium oxide on copper, to ruthenium on copper oxide to ruthenium on copper during the complete reduction process. Therefore, ruthenium and copper atoms are covalently bonded at the interface to produce the utmost adhesion between two surfaces.
[0061] Ruthenium seed layers 310 and 410 are formed by a vapor deposition process that includes an ALD process, a CVD process, a PVD process, or combinations thereof. In one example, ruthenium seed layers 310 and 410 are deposited by sequentially pulsing a ruthenium precursor (e.g., ruthenium tetroxide) and a reductant (e.g., hydrogen) during an ALD process. Thereafter, substrates 300 and 400 may be thermally processed in a reducing atmosphere, such as in an annealing chamber containing an environment of hydrogen, to further reduce any remaining ruthenium oxide to a ruthenium-containing material.
[0062] Ruthenium tetroxide may be delivered to the substrate in a vapor deposition process, such as an in situ generated process. Preferably, ruthenium tetroxide is generated in situ by exposing a ruthenium-containing source to an oxidizing gas prior and exposing the resulting product to conductive contacts 308 and 408. Ruthenium tetroxide is a strong oxidant and therefore readily reacts with any exposed copper, copper oxides, tungsten, or tungsten oxides on the surfaces of conductive contacts 308 and 408.
[0063] In one example of forming ruthenium tetroxide, ozone gas is produced by supplying an oxygen source gas into an ozone generator. The oxygen source may include oxygen (O2), nitrous oxide (N2O), nitric oxide (NO), nitrogen dioxide (NO2), or combinations thereof. Preferably, a 12 vol% ozone is generated by flowing oxygen through the ozone generator. The oxidizing gas containing ozone may be purified when passed or bubbled through a silicon gel. Subsequently, the ozone is exposed to a metallic ruthenium source to form ruthenium tetroxide that is condensed in a cooled cold trap. The ozone flow is stopped and the cold trap is purged with an inert gas (e.g., nitrogen) to rid the line of excess oxygen. Thereafter, the cold trap is warmed to a temperature to sublime the ruthenium tetroxide while a flow of inert gas is passed therethrough. The vaporized ruthenium tetroxide forms a deposition gas by saturating an inert gas selected from argon, nitrogen, or helium.
[0064] In one exemplary vapor deposition process, a deposition gas containing ruthenium tetroxide is sequentially pulsed with a reductant into an ALD chamber to form a ruthenium metal layer or a ruthenium oxide layer on the underlying copper contacts. In one aspect, the ALD process contains a consistent flow of carrier gas while the ruthenium tetroxide and the reductant are sequentially pulsed into the carrier gas. In another aspect, the ALD process cycle contains a pulse of purge gas, a pulse of ruthenium tetroxide, a pulse of purge gas, and a pulse of the reductant. The carrier gas and the purge gas may be independently selected from hydrogen, argon, nitrogen, or helium. Reductants that are useful during vapor deposition process for forming ruthenium-containing materials include hydrogen, diborane, silane, disilane, phosphine, plasmas thereof, derivatives thereof, or combinations thereof. A more thorough disclosure of ALD processes to deposit ruthenium- containing materials is described in commonly assigned U.S. Ser. No. 10/811 ,230, entitled, "Ruthenium Layer Formation for Copper Film Deposition," filed March 26, 2004, and published as US 2004-0241321 , which is herein incorporated by reference.
[0065] After an ALD process, the substrate may be exposed to a thermal process by heating to a temperature within a range from about 100°C to about 8000C, preferably, from about 200°C to about 600°C, and more preferably, from about 300°C to about 5000C. The thermal process may be conducted in an environment containing hydrogen gas. During the thermal process, the oxygen concentration within the substrate, especially within the conductive contact and ruthenium- containing material thereon, is decreased. Any remaining ruthenium oxides and copper oxides are chemically reduced to form their respective metal.
[0066] In another exemplary vapor deposition process, a deposition gas containing ruthenium tetroxide is delivered to substrates 300 or 400. Substrates 300 or 400 are maintained at a temperature of about 1000C during the process. After exposing substrates 300 or 400 to the ruthenium tetroxide containing gas for about 30 seconds, a ruthenium oxide layer is formed on conductive contacts 308 and 408. The ruthenium oxide layer may be exposed to a reductant to form a ruthenium- containing layer. The ruthenium oxide may be chemically reduced to ruthenium. For example, a ruthenium oxide layer may be exposed to a hydrogen plasma to remove the oxygen and form a metallic ruthenium-containing layer. In another example, a ruthenium oxide layer is exposed to diborane during a vapor deposition process to remove oxygen and form a ruthenium-containing layer containing ruthenium boride. In another example, a ruthenium oxide layer is exposed to phosphine during a vapor deposition process to remove oxygen and form ruthenium- containing layer containing ruthenium phosphide. [0067] Figures 3D and 4D illustrate copper-containing layers 320 and 420 deposited on ruthenium seed layers 310 and 410 deposited during an electroless deposition process. Apertures 303 and 403 are bottom up filled with copper- containing material while avoiding defects (e.g., seams, voids or gaps) within copper-containing layers 320 and 420. The electroless deposition process utilizes an electroless solution containing a copper source and at least one additive, such as an accelerator, a suppressor, or a leveler. Copper-containing layers 320 and 420 contain copper or a copper alloy and are deposited according to electroless deposition processes and solutions previously discussed to form copper-containing layer 120. In one embodiment, copper-containing layers 320 and 420 have a convexed copper surface or a concaved copper surface, as described similarly for copper-containing layer 120 having convexed surface 126 (Figure 1C) or concaved surface 128 (Figure 1 D). The convexed/concaved copper surfaces may adjoin sidewalls 305 or 405 at an angle of less than 90° from sidewall 305 or 405, such as within a range from about 5° to about 60°, preferably, from about 5° to about 45°, and more preferably, from about 5° to about 30°.
Copper Electroless Deposition Process
[0068] In one embodiment, an electroless copper solution may be prepared combining three solutions (e.g., Solutions A, B, and C) and water.
[0069] Solution A may contain about 525 ml_ of TMAH (25%), about 475 ml_ of deionized water, and about 1 g/L of surfactant (e.g., PEG, PEG-PPG-PEG, TRITON® 100, TERGITOL®, or RHODAFAC® RE-610).
[0070] Solution B may contain about 62.5 g/L of copper sulfate, about 146 g/L of EDTA, and enough TMAH to provide Solution B with a pH value of about 12.5 at about 2O0C.
[0071] In one example, Solution C may contain about 200 g/L of glyoxylic acid and enough TMAH to provide Solution C with a pH value of about 9 at about 200C. The copper deposition rate is increased by increasing the concentration of the glyoxylic acid. In another example, Solution C may contain about 138 g/L of glyoxylic acid, about 13.5 g/L of hypophosphorous acid, and enough TMAH to provide Solution C with a pH value of about 9 at about 20°C.
[0072] In one example, a mixture is formed by adding about 10 mL of Solution A to about 70 mL of heated deionized water (about 750C). Subsequently, about 10 mL of Solution C is added to the mixture, then, about 10 mL of Solution B is added to the mixture to form about 100 mL of the copper electroless deposition solution.
[0073] In another embodiment, at least one leveler may be added to the copper electroless deposition solution to provide better deposition control during copper surface plating processes. Leveler may be added to any of the solutions, but preferably to either Solution A or Solution C. The electroless deposition solution may contain a leveler at concentration within a range from about 20 parts per billion (ppb) to about 600 parts per million (ppm), preferably, from about 100 ppb to about 100 ppm. Examples of levelers that may be employed in an electroless solution include, but are not limited to, alkylpolyimines and organic sulfonates, such as 1-(2- hydroxyethyl)-2-imidazolidinethione (HIT), 4-mercaptopyridine, 2- mercaptothiazoline, ethylene thiourea, thiourea, or derivatives thereof.
[0074] In one example of a solution containing a leveler, Solution A may contain about 525 mL of TMAH (25%), about 475 mL of deionized water, about 10 ppm of HIT, and about 1 g/L of surfactant. In another example, Solution C may contain about 200 g/L of glyoxylic acid, about 10 ppm of HIT, and enough TMAH to provide Solution C with a pH value of about 9. In another example, Solution C may contain about 138 g/L of glyoxylic acid, about 13.5 g/L of hypophosphorous acid, about 10 ppm of HIT, and enough TMAH to provide Solution C with a pH value of about 9.
[0075] While the foregoing is directed to embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

Claims:
1. A method for forming a conductive material within a feature on a substrate, comprising: depositing a seed layer selectively onto a bottom surface of a feature on a substrate while sidewalls of the feature remain substantially free of the seed layer during a collimated physical vapor deposition process; and depositing a copper-containing layer on the seed layer to fill the feature during an electroless deposition process.
2. The method of claim 1 , wherein the seed layer comprises a metal selected from the group consisting of copper, ruthenium, cobalt, tantalum, titanium, tungsten, rhenium, palladium, platinum, nickel, alloys thereof, and combinations thereof.
3. The method of claim 2, wherein the seed layer is deposited on a barrier layer disposed on the substrate, the barrier layer comprises a material selected from the group consisting of tantalum, tantalum nitride, tantalum silicon nitride, titanium, titanium nitride, titanium silicon nitride, ruthenium, tungsten, tungsten nitride, alloys thereof, derivatives thereof, and combinations thereof.
4. The method of claim 3, wherein the bottom surface of the feature is exposed to a plasma to remove a portion of the seed layer and the barrier layer and to expose a conductive underlayer prior to filling the feature by the electroless deposition process.
5. The method of claim 1 , wherein the electroless deposition process comprises exposing the substrate to an electroless solution comprising a copper source and at least one additive selected from the group consisting of an accelerator, a suppressor, a leveler, and combinations thereof.
6. The method of claim 5, wherein the accelerator is a sulfur-based compound selected from the group consisting of bis(3-sulfopropyl) disulfide, 3-mercapto-1- propane sulfonic acid, derivatives thereof, and combinations thereof.
7. The method of claim 5, wherein the suppressor is polyethylene glycol, polypropylene glycol, polyoxyethylene-polyoxypropylene copolymer, or derivatives thereof.
8. The method of claim 5, wherein a surface of the copper-containing layer adjoins the sidewall of the feature at an angle of less than 90° from the sidewall.
9. The method of claim 8, wherein the angle is within a range from about 5° to about 45°.
10. The method of claim 8, wherein a concentration of the leveler is adjusted to control the angle.
11. The method of claim 10, wherein the leveler is an alkylpolyimine compound or an organic sulfonate compound.
12. The method of claim 11 , wherein the leveler is selected from the group consisting of 1-(2-hydroxyethyl)-2-imidazolidinethione, 4-mercaptopyridine, 2- mercaptothiazoline, ethylene thiourea, thiourea, derivatives thereof, and combinations thereof.
13. The method of claim 10, wherein the concentration of the leveler is within a range from about 20 ppb to about 600 ppm.
14. The method of claim 13, wherein the leveler is 1-(2-hydroxyethyl)-2- imidazolidinethione.
15. A method for forming a conductive material within a feature on a substrate, comprising: depositing a seed layer onto a barrier layer disposed on a substrate during a physical vapor deposition process, wherein the substrate contains a feature having sidewalls and a bottom surface; etching the bottom surface of the feature with a plasma to remove a portion of the seed layer and the barrier layer and to expose a conductive underlayer; and depositing a copper-containing layer on the conductive underlayer while filling the feature during an electroless deposition process.
16. The method of claim 15, wherein the seed layer comprises a metal selected from the group consisting of copper, ruthenium, cobalt, tantalum, titanium, tungsten, rhenium, palladium, platinum, nickel, alloys thereof, and combinations thereof.
17. The method of claim 16, wherein the seed layer is selectively deposited on the bottom surface of the feature while the sidewalls of the feature remain substantially free of the seed layer during a collimated physical vapor deposition process.
18. The method of claim 16, wherein the barrier layer comprises a material selected from the group consisting of tantalum, tantalum nitride, tantalum silicon nitride, titanium, titanium nitride, titanium silicon nitride, ruthenium, tungsten, tungsten nitride, alloys thereof, derivatives thereof, and combinations thereof.
19. The method of claim 16, wherein the conductive underlayer contains a metal selected from the group consisting of copper, tungsten, aluminum, alloys thereof, and combinations thereof.
20. The method of claim 19, wherein the plasma is formed by a remote plasma source.
21. The method of claim 15, wherein the electroless deposition process comprises exposing the substrate to an electroless solution comprising a copper source and at least one additive selected from the group consisting of an accelerator, a suppressor, a leveler, and combinations thereof.
22. The method of claim 21 , wherein the accelerator is a sulfur-based compound selected from the group consisting of bis(3-sulfopropyl) disulfide, 3-mercapto-1- propane sulfonic acid, derivatives thereof, and combinations thereof.
23. The method of claim 21 , wherein the suppressor is polyethylene glycol, polypropylene glycol, polyoxyethylene-polyoxypropylene copolymer, or derivatives thereof.
24. The method of claim 21 , wherein a surface of the copper-containing layer adjoins the sidewall of the feature at an angle of less than 90° from the sidewalk
25. The method of claim 24, wherein the angle is within a range from about 5° to about 45°.
26. The method of claim 24, wherein a concentration of the leveler is adjusted to control the angle.
27. The method of claim 26, wherein the leveler is an alkylpolyimine compound or an organic sulfonate compound.
28. The method of claim 27, wherein the leveler is selected from the group consisting of 1-(2-hydroxyethyl)-2-imidazolidinethione, 4-mercaptopyridine, 2- mercaptothiazoline, ethylene thiourea, thiourea, derivatives thereof, and combinations thereof.
29. The method of claim 26, wherein the concentration of the leveler is within a range from about 20 ppb to about 600 ppm.
30. The method of claim 29, wherein the leveler is 1-(2-hydroxyethyl)-2- imidazolidinethione.
31. A method for forming a conductive material within a feature on a substrate, comprising: depositing a seed layer onto a barrier layer disposed on a substrate during a physical vapor deposition process, wherein the substrate contains a feature having sidewalls and a bottom surface; and exposing the substrate to an electroless deposition solution to deposit a copper-containing layer over the seed layer, wherein the electroless deposition solution comprises a leveler at a concentration to form a surface of the copper- containing layer adjoining the sidewall of the feature at an angle of less than 90° from the sidewall.
32. The method of claim 31 , wherein the angle is within a range from about 5° to about 45°.
33. The method of claim 31 , wherein the concentration of the leveler is adjusted to control the angle.
34. The method of claim 33, wherein the leveler is an alkylpolyimine compound or an organic sulfonate compound.
35. The method of claim 34, wherein the leveler is selected from the group consisting of 1-(2-hydroxyethyl)-2-imidazolidinethione, 4-mercaptopyridine, 2- mercaptothiazoline, ethylene thiourea, thiourea, derivatives thereof, and combinations thereof.
36. The method of claim 33, wherein the concentration of the leveler is within a range from about 20 ppb to about 600 ppm.
37. The method of claim 36, wherein the leveler is 1-(2-hydroxyethyl)-2- imidazolidinethione.
38. The method of claim 32, wherein the electroless solution further comprises a copper source and at least one additive selected from the group consisting of an accelerator, a suppressor, and combinations thereof.
39. The method of claim 38, wherein the accelerator is a sulfur-based compound selected from the group consisting of bis(3-sulfopropyl) disulfide, 3-mercapto-1- propane sulfonic acid, derivatives thereof, and combinations thereof.
40. The method of claim 38, wherein the suppressor is polyethylene glycol, polypropylene glycol, polyoxyethylene-polyoxypropylene copolymer or derivatives thereof.
41. The method of claim 32, wherein the seed layer comprises a metal selected from the group consisting of copper, ruthenium, cobalt, tantalum, titanium, tungsten, rhenium, palladium, platinum, nickel, alloys thereof, and combinations thereof.
42. The method of claim 41 , wherein the seed layer is selectively deposited on the bottom surface of the feature while the sidewalls of the feature remain substantially free of the seed layer during a collimated physical vapor deposition process.
43. The method of claim 41 , wherein the barrier layer comprises a material selected from the group consisting of tantalum, tantalum nitride, tantalum silicon nitride, titanium, titanium nitride, titanium silicon nitride, ruthenium, tungsten, tungsten nitride, alloys thereof, derivatives thereof, and combinations thereof.
44. The method of claim 43, wherein the bottom surface of the feature is exposed to a plasma to remove a portion of the seed layer and the barrier layer and to expose a conductive underlayer prior to filling the feature by the electroless deposition process.
45. A method for forming a conductive material within a feature on a substrate, comprising: forming a ruthenium seed layer selectively onto a contact surface within a feature on a substrate during a vapor deposition process, wherein sidewalls of the feature remain substantially free of the ruthenium seed layer during the vapor deposition process; and depositing a copper-containing layer on the ruthenium seed layer while filling the feature during an electroless deposition process.
46. The method of claim 45, wherein the vapor deposition process comprises exposing the substrate to ruthenium tetroxide.
47. The method of claim 46, wherein a ruthenium oxide layer is deposited and chemically reduced to form the ruthenium seed layer.
48. The method of claim 47, wherein the ruthenium oxide layer is chemically reduced by exposing the substrate to a reductant selected from the group consisting of silane, disilane, diborane, borane compounds, hydrogen, atomic hydrogen, derivatives thereof, and combination thereof.
49. The method of claim 47, wherein the contact surface comprises a material selected from the group consisting of copper, tungsten, aluminum, alloys thereof, derivatives thereof, and combinations thereof.
50. The method of claim 46, wherein the electroless deposition process includes exposing the substrate to an electroless solution comprising a copper source and at least one additive selected from the group consisting of an accelerator, a suppressor, a leveler, and combinations thereof.
51. The method of claim 50, wherein the accelerator is a sulfur-based compound selected from the group consisting of bis(3-sulfopropyl) disulfide, 3-mercapto-1- propane sulfonic acid, derivatives thereof, and combinations thereof.
52. The method of claim 50, wherein the suppressor is polyethylene glycol, polypropylene glycol, polyoxyethylene-polyoxypropylene copolymer or derivatives thereof.
53. The method of claim 50, wherein a surface of the copper-containing layer adjoins the sidewall of the feature at an angle of less than 90° from the sidewall.
54. The method of claim 53, wherein the angle is within a range from about 5° to about 45°.
55. The method of claim 53, wherein a concentration of the leveler is adjusted to control the angle.
56. The method of claim 55, wherein the leveler is an alkylpolyimine compound or an organic sulfonate compound.
57. The method of claim 56, wherein the leveler is selected from the group consisting of 1-(2-hydroxyethyl)-2-imidazolidinethione, 4-mercaptopyridine, 2- mercaptothiazoline, ethylene thiourea, thiourea, derivatives thereof, and combinations thereof.
58. The method of claim 55, wherein the concentration of the leveler is within a range from about 20 ppb to about 600 ppm.
59. The method of claim 58, wherein the leveler is 1-(2-hydroxyethyl)-2- imidazolidinethione.
60. A method for forming a conductive material within a feature on a substrate, comprising: exposing a copper-containing surface within a feature on a substrate to a process gas comprising ruthenium tetroxide to form a ruthenium oxide layer thereon; and depositing a copper-containing layer to fill the feature during an electroless deposition process.
61. The method of claim 60, wherein the ruthenium oxide layer is exposed to a reductant to form the ruthenium seed layer prior to depositing the copper-containing layer.
62. The method of claim 61 , wherein the reductant is selected from the group consisting of silane, disilane, diborane, borane compounds, hydrogen, atomic hydrogen, derivatives thereof, and combination thereof.
63. The method of claim 60, wherein the electroless deposition process includes exposing the substrate to an electroless solution comprising a copper source and at least one additive selected from the group consisting of an accelerator, a suppressor, a leveler, and combinations thereof.
64. The method of claim 63, wherein the accelerator is a sulfur-based compound selected from the group consisting of bis(3-sulfopropyl) disulfide, 3-mercapto-1 - propane sulfonic acid, derivatives thereof, and combinations thereof.
65. The method of claim 63, wherein the suppressor is polyethylene glycol, polypropylene glycol, polyoxyethylene-polyoxypropylene copolymer or derivatives thereof.
66. The method of claim 63, wherein a surface of the copper-containing layer adjoins the sidewall of the feature at an angle of less than 90° from the sidewalk
67. The method of claim 66, wherein the angle is within a range from about 5° to about 45°.
68. The method of claim 66, wherein a concentration of the leveler is adjusted to control the angle.
69. The method of claim 68, wherein the leveler is an alkylpolyimine compound or an organic sulfonate compound.
70. The method of claim 69, wherein the leveler is selected from the group consisting of 1-(2-hydroxyethyl)-2-imidazolidinethione, 4-mercaptopyridine, 2- mercaptothiazoline, ethylene thiourea, thiourea, derivatives thereof, and combinations thereof.
71. The method of claim 68, wherein the concentration of the leveler is within a range from about 20 ppb to about 600 ppm.
72. The method of claim 71 , wherein the leveler is 1-(2-hydroxyethyl)-2- imidazolidinethione.
73. A method for forming a conductive material within a feature on a substrate, comprising: depositing a barrier layer onto a substrate containing a feature; etching a bottom surface of the feature with a plasma to expose a contact surface while removing a portion of the barrier layer; exposing a contact surface to a process gas comprising ruthenium tetroxide to form a ruthenium oxide layer thereon; exposing the ruthenium oxide layer to a reductant to form a ruthenium- containing layer; and depositing a copper-containing layer on the ruthenium-containing layer while filling the feature by an electroless deposition process.
74. The method of claim 73, wherein the reductant is selected from the group consisting of silane, disilane, diborane, borane compounds, hydrogen, atomic hydrogen, derivatives thereof, and combination thereof.
75. The method of claim 73, wherein the electroless deposition process includes exposing the substrate to an electroless solution comprising a copper source and at least a leveler.
76. The method of claim 75, wherein a surface of the copper-containing layer adjoins the sidewall of the feature at an angle of less than 90° from the sidewall.
77. The method of claim 76, wherein a concentration of the leveler is adjusted to control the angle.
78. The method of claim 77, wherein the angle is within a range from about 5° to about 45°.
79. The method of claim 77, wherein the leveler is an alkylpolyimine compound or an organic sulfonate compound.
80. The method of claim 79, wherein the leveler is selected from the group consisting of 1-(2-hydroxyethyl)-2-imidazolidinethione, 4-mercaptopyridine, 2- mercaptothiazoline, ethylene thiourea, thiourea, derivatives thereof, and combinations thereof.
81. The method of claim 77, wherein the concentration of the leveler is within a range from about 20 ppb to about 600 ppm.
82. The method of claim 81 , wherein the leveler is 1-(2-hydroxyethyl)-2- imidazolidinethione.
PCT/US2006/009920 2005-03-18 2006-03-20 Process for electroless copper deposition WO2006102182A2 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8247301B2 (en) 2007-12-17 2012-08-21 Nippon Mining & Metals Co., Ltd. Substrate and manufacturing method therefor
WO2014084791A1 (en) * 2012-12-02 2014-06-05 Weschke Carl Johan Walter A rotation detection device and a vehicle pedal comprising such a device
US20150159274A1 (en) * 2012-02-01 2015-06-11 Atotech Deutschland Gmbh Electroless nickel plating bath

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5654245A (en) * 1993-03-23 1997-08-05 Sharp Microelectronics Technology, Inc. Implantation of nucleating species for selective metallization and products thereof
US5702573A (en) * 1996-01-29 1997-12-30 Varian Associates, Inc. Method and apparatus for improved low pressure collimated magnetron sputter deposition of metal films
US5969422A (en) * 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US6046108A (en) * 1999-06-25 2000-04-04 Taiwan Semiconductor Manufacturing Company Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby
US6245655B1 (en) * 1999-04-01 2001-06-12 Cvc Products, Inc. Method for planarized deposition of a material
US6271135B1 (en) * 1998-07-07 2001-08-07 Imec Vzx Method for forming copper-containing metal studs
US6287968B1 (en) * 1999-01-04 2001-09-11 Advanced Micro Devices, Inc. Method of defining copper seed layer for selective electroless plating processing
US6596643B2 (en) * 2001-05-07 2003-07-22 Applied Materials, Inc. CVD TiSiN barrier for copper integration
US6867136B2 (en) * 2001-07-20 2005-03-15 Nutool, Inc. Method for electrochemically processing a workpiece
US20060084267A1 (en) * 2004-10-14 2006-04-20 Lsi Logic Corporation, A Delaware Corporation Method for fabricating planar semiconductor wafers

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5654245A (en) * 1993-03-23 1997-08-05 Sharp Microelectronics Technology, Inc. Implantation of nucleating species for selective metallization and products thereof
US5702573A (en) * 1996-01-29 1997-12-30 Varian Associates, Inc. Method and apparatus for improved low pressure collimated magnetron sputter deposition of metal films
US5969422A (en) * 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US6271135B1 (en) * 1998-07-07 2001-08-07 Imec Vzx Method for forming copper-containing metal studs
US6287968B1 (en) * 1999-01-04 2001-09-11 Advanced Micro Devices, Inc. Method of defining copper seed layer for selective electroless plating processing
US6245655B1 (en) * 1999-04-01 2001-06-12 Cvc Products, Inc. Method for planarized deposition of a material
US6046108A (en) * 1999-06-25 2000-04-04 Taiwan Semiconductor Manufacturing Company Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby
US6596643B2 (en) * 2001-05-07 2003-07-22 Applied Materials, Inc. CVD TiSiN barrier for copper integration
US6867136B2 (en) * 2001-07-20 2005-03-15 Nutool, Inc. Method for electrochemically processing a workpiece
US20060084267A1 (en) * 2004-10-14 2006-04-20 Lsi Logic Corporation, A Delaware Corporation Method for fabricating planar semiconductor wafers

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8247301B2 (en) 2007-12-17 2012-08-21 Nippon Mining & Metals Co., Ltd. Substrate and manufacturing method therefor
US20150159274A1 (en) * 2012-02-01 2015-06-11 Atotech Deutschland Gmbh Electroless nickel plating bath
US9399820B2 (en) * 2012-02-01 2016-07-26 Atotech Deutschland Gmbh Electroless nickel plating bath
WO2014084791A1 (en) * 2012-12-02 2014-06-05 Weschke Carl Johan Walter A rotation detection device and a vehicle pedal comprising such a device

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