WO2006104817A3 - Method for reducing dielectric overetch when making contact to conductive features - Google Patents

Method for reducing dielectric overetch when making contact to conductive features Download PDF

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Publication number
WO2006104817A3
WO2006104817A3 PCT/US2006/010520 US2006010520W WO2006104817A3 WO 2006104817 A3 WO2006104817 A3 WO 2006104817A3 US 2006010520 W US2006010520 W US 2006010520W WO 2006104817 A3 WO2006104817 A3 WO 2006104817A3
Authority
WO
WIPO (PCT)
Prior art keywords
dielectric
conductive features
etch
stop layer
etch stop
Prior art date
Application number
PCT/US2006/010520
Other languages
French (fr)
Other versions
WO2006104817A2 (en
Inventor
Christopher J Petti
Original Assignee
Sandisk 3D Llc
Christopher J Petti
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sandisk 3D Llc, Christopher J Petti filed Critical Sandisk 3D Llc
Priority to JP2008503170A priority Critical patent/JP2008536300A/en
Priority to EP06739347A priority patent/EP1861874A2/en
Priority to CN2006800155858A priority patent/CN101189714B/en
Publication of WO2006104817A2 publication Critical patent/WO2006104817A2/en
Publication of WO2006104817A3 publication Critical patent/WO2006104817A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In a first preferred embodiment of the present invention, conductive features (44) are formed on a first dielectric etch stop layer (40) , and a second dielectric material (48) is deposited over and between the conductive features. A via etch to the conductive features which is selective between the first and second dielectrics will stop on the dielectric etch stop layer, limiting overetch. In a second embodiment, a plurality of conductive features (64) is formed in a subtractive pattern and etch process, filled with a dielectric fill (68) , and then a surface formed coexposing the conductive features and dielectric fill. A dielectric etch stop layer (72) is deposited on the surface, then a third dielectric (74) covers the dielectric etch stop layer. When a contact (76) is etched through the third dielectric, this selective etch stops on the dielectric etch stop layer. A second etch makes contact to the conductive features .
PCT/US2006/010520 2005-03-25 2006-03-21 Method for reducing dielectric overetch when making contact to conductive features WO2006104817A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008503170A JP2008536300A (en) 2005-03-25 2006-03-21 Method for reducing dielectric overetching in making contacts to conductive features
EP06739347A EP1861874A2 (en) 2005-03-25 2006-03-21 Method for reducing dielectric overetch when making contact to conductive features
CN2006800155858A CN101189714B (en) 2005-03-25 2006-03-21 Method for reducing dielectric overetch when making contact to conductive features

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/089,771 US7521353B2 (en) 2005-03-25 2005-03-25 Method for reducing dielectric overetch when making contact to conductive features
US11/089,771 2005-03-25

Publications (2)

Publication Number Publication Date
WO2006104817A2 WO2006104817A2 (en) 2006-10-05
WO2006104817A3 true WO2006104817A3 (en) 2006-11-23

Family

ID=36808162

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/010520 WO2006104817A2 (en) 2005-03-25 2006-03-21 Method for reducing dielectric overetch when making contact to conductive features

Country Status (7)

Country Link
US (4) US7521353B2 (en)
EP (1) EP1861874A2 (en)
JP (1) JP2008536300A (en)
KR (1) KR20080005494A (en)
CN (2) CN102683267B (en)
TW (1) TWI329904B (en)
WO (1) WO2006104817A2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060249753A1 (en) * 2005-05-09 2006-11-09 Matrix Semiconductor, Inc. High-density nonvolatile memory array fabricated at low temperature comprising semiconductor diodes
US7422985B2 (en) * 2005-03-25 2008-09-09 Sandisk 3D Llc Method for reducing dielectric overetch using a dielectric etch stop at a planar surface
US7521353B2 (en) * 2005-03-25 2009-04-21 Sandisk 3D Llc Method for reducing dielectric overetch when making contact to conductive features
US7728390B2 (en) * 2005-05-06 2010-06-01 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-level interconnection memory device
KR100895853B1 (en) * 2006-09-14 2009-05-06 삼성전자주식회사 Stacked memory and method for forming the same
JP2010118530A (en) * 2008-11-13 2010-05-27 Toshiba Corp Nonvolatile semiconductor memory device
US8372743B2 (en) * 2011-03-02 2013-02-12 Texas Instruments Incorporated Hybrid pitch-split pattern-split lithography process
US8575020B2 (en) * 2011-03-02 2013-11-05 Texas Instruments Incorporated Pattern-split decomposition strategy for double-patterned lithography process
US8461038B2 (en) * 2011-03-02 2013-06-11 Texas Instruments Incorporated Two-track cross-connects in double-patterned metal layers using a forbidden zone
US8802561B1 (en) * 2013-04-12 2014-08-12 Sandisk 3D Llc Method of inhibiting wire collapse
US10546772B2 (en) 2016-03-30 2020-01-28 Intel Corporation Self-aligned via below subtractively patterned interconnect

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999016118A1 (en) * 1997-09-25 1999-04-01 Advanced Micro Devices, Inc. Process for fabricating semiconductor device including antireflective etch stop layer
US6072237A (en) * 1996-03-15 2000-06-06 Taiwan Semiconductor Manufacturing Company Borderless contact structure
US6162722A (en) * 1999-05-17 2000-12-19 United Microelectronics Corp. Unlanded via process
US6258712B1 (en) * 1998-12-31 2001-07-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a borderless contact
US6472308B1 (en) * 1996-11-21 2002-10-29 Advanced Micro Devices, Inc. Borderless vias on bottom metal
US20030109123A1 (en) * 2000-01-24 2003-06-12 Toshiyuki Orita Method of forming a via hole in a semiconductor device
US20050014322A1 (en) * 2002-12-19 2005-01-20 Matrix Semiconductor Method for making high density nonvolatile memory

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4499557A (en) 1980-10-28 1985-02-12 Energy Conversion Devices, Inc. Programmable cell for use in programmable electronic arrays
US4646266A (en) 1984-09-28 1987-02-24 Energy Conversion Devices, Inc. Programmable semiconductor structures and methods for using the same
JP2934353B2 (en) 1992-06-24 1999-08-16 三菱電機株式会社 Semiconductor device and manufacturing method thereof
US5612254A (en) 1992-06-29 1997-03-18 Intel Corporation Methods of forming an interconnect on a semiconductor substrate
US5244837A (en) 1993-03-19 1993-09-14 Micron Semiconductor, Inc. Semiconductor electrical interconnection methods
TW272310B (en) * 1994-11-09 1996-03-11 At & T Corp Process for producing multi-level metallization in an integrated circuit
US5915167A (en) 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US6008116A (en) * 1997-12-18 1999-12-28 Advanced Micro Devices, Inc. Selective etching for improved dielectric interlayer planarization
US6034882A (en) 1998-11-16 2000-03-07 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US6365453B1 (en) * 1999-06-16 2002-04-02 Micron Technology, Inc. Method and structure for reducing contact aspect ratios
US6329118B1 (en) * 1999-06-21 2001-12-11 Intel Corporation Method for patterning dual damascene interconnects using a sacrificial light absorbing material
US6395639B1 (en) 1999-09-16 2002-05-28 Agere Systems Guardian Corporation Process for improving line width variations between tightly spaced and isolated features in integrated circuits
US6544887B1 (en) * 2000-03-31 2003-04-08 Lam Research Corporation Polycide etch process
US6856572B2 (en) 2000-04-28 2005-02-15 Matrix Semiconductor, Inc. Multi-headed decoder structure utilizing memory array line driver with dual purpose driver device
KR100363091B1 (en) * 2000-06-27 2002-11-30 삼성전자 주식회사 Semiconductor memory device having self-aligned contacts and method of fabricating the same
CN101179079B (en) 2000-08-14 2010-11-03 矩阵半导体公司 Rail stack array of charge storage devices and method of making same
TW508860B (en) * 2000-08-30 2002-11-01 Mitsui & Amp Co Ltd Paste-like thin electrode for battery, its manufacturing method, and battery
JP2003100869A (en) * 2001-09-27 2003-04-04 Toshiba Corp Semiconductor device and its manufacturing method
TW511233B (en) 2001-11-01 2002-11-21 United Microelectronics Corp Oxygen-doped silicon carbide etch stop layer
US6975016B2 (en) * 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
KR100445638B1 (en) * 2002-07-26 2004-08-25 삼성전자주식회사 Interconnection structure connecting electrically isolated regions and method of fabricatinging the same
US7063597B2 (en) 2002-10-25 2006-06-20 Applied Materials Polishing processes for shallow trench isolation substrates
US6909152B2 (en) * 2002-11-14 2005-06-21 Infineon Technologies, Ag High density DRAM with reduced peripheral device area and method of manufacture
US7285464B2 (en) 2002-12-19 2007-10-23 Sandisk 3D Llc Nonvolatile memory cell comprising a reduced height vertical diode
US8637366B2 (en) 2002-12-19 2014-01-28 Sandisk 3D Llc Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states
US7176064B2 (en) 2003-12-03 2007-02-13 Sandisk 3D Llc Memory cell comprising a semiconductor junction diode crystallized adjacent to a silicide
US6946719B2 (en) 2003-12-03 2005-09-20 Matrix Semiconductor, Inc Semiconductor device including junction diode contacting contact-antifuse unit comprising silicide
US7005350B2 (en) 2002-12-31 2006-02-28 Matrix Semiconductor, Inc. Method for fabricating programmable memory array structures incorporating series-connected transistor strings
US7505321B2 (en) 2002-12-31 2009-03-17 Sandisk 3D Llc Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same
US7233024B2 (en) 2003-03-31 2007-06-19 Sandisk 3D Llc Three-dimensional memory device incorporating segmented bit line memory array
US6879505B2 (en) 2003-03-31 2005-04-12 Matrix Semiconductor, Inc. Word line arrangement having multi-layer word line segments for three-dimensional memory array
US7115517B2 (en) * 2003-04-07 2006-10-03 Applied Materials, Inc. Method of fabricating a dual damascene interconnect structure
US7202162B2 (en) 2003-04-22 2007-04-10 Taiwan Semiconductor Manufacturing Company, Ltd. Atomic layer deposition tantalum nitride layer to improve adhesion between a copper structure and overlying materials
US7511352B2 (en) 2003-05-19 2009-03-31 Sandisk 3D Llc Rail Schottky device and method of making
US7125792B2 (en) * 2003-10-14 2006-10-24 Infineon Technologies Ag Dual damascene structure and method
US6918821B2 (en) 2003-11-12 2005-07-19 Dow Global Technologies, Inc. Materials and methods for low pressure chemical-mechanical planarization
US7423304B2 (en) 2003-12-05 2008-09-09 Sandisck 3D Llc Optimization of critical dimensions and pitch of patterned features in and above a substrate
US7474000B2 (en) 2003-12-05 2009-01-06 Sandisk 3D Llc High density contact to relaxed geometry layers
US7172840B2 (en) 2003-12-05 2007-02-06 Sandisk Corporation Photomask features with interior nonprinting window using alternating phase shifting
US7050290B2 (en) * 2004-01-30 2006-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated capacitor
US20050221200A1 (en) 2004-04-01 2005-10-06 Matrix Semiconductor, Inc. Photomask features with chromeless nonprinting phase shifting window
US7224013B2 (en) 2004-09-29 2007-05-29 Sandisk 3D Llc Junction diode comprising varying semiconductor compositions
US20060067117A1 (en) 2004-09-29 2006-03-30 Matrix Semiconductor, Inc. Fuse memory cell comprising a diode, the diode serving as the fuse element
US7037774B1 (en) * 2004-10-21 2006-05-02 Integrated Device Technology, Inc. Self-aligned contact structure and process for forming self-aligned contact structure
US7300876B2 (en) * 2004-12-14 2007-11-27 Sandisk 3D Llc Method for cleaning slurry particles from a surface polished by chemical mechanical polishing
US7521353B2 (en) 2005-03-25 2009-04-21 Sandisk 3D Llc Method for reducing dielectric overetch when making contact to conductive features
US7422985B2 (en) * 2005-03-25 2008-09-09 Sandisk 3D Llc Method for reducing dielectric overetch using a dielectric etch stop at a planar surface

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6072237A (en) * 1996-03-15 2000-06-06 Taiwan Semiconductor Manufacturing Company Borderless contact structure
US6472308B1 (en) * 1996-11-21 2002-10-29 Advanced Micro Devices, Inc. Borderless vias on bottom metal
WO1999016118A1 (en) * 1997-09-25 1999-04-01 Advanced Micro Devices, Inc. Process for fabricating semiconductor device including antireflective etch stop layer
US6258712B1 (en) * 1998-12-31 2001-07-10 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a borderless contact
US6162722A (en) * 1999-05-17 2000-12-19 United Microelectronics Corp. Unlanded via process
US20030109123A1 (en) * 2000-01-24 2003-06-12 Toshiyuki Orita Method of forming a via hole in a semiconductor device
US20050014322A1 (en) * 2002-12-19 2005-01-20 Matrix Semiconductor Method for making high density nonvolatile memory

Also Published As

Publication number Publication date
CN101189714B (en) 2012-03-28
US8741768B2 (en) 2014-06-03
KR20080005494A (en) 2008-01-14
US20130295764A1 (en) 2013-11-07
TWI329904B (en) 2010-09-01
US20090142921A1 (en) 2009-06-04
CN101189714A (en) 2008-05-28
JP2008536300A (en) 2008-09-04
US20110189840A1 (en) 2011-08-04
CN102683267B (en) 2015-04-08
US7928007B2 (en) 2011-04-19
CN102683267A (en) 2012-09-19
WO2006104817A2 (en) 2006-10-05
US8497204B2 (en) 2013-07-30
TW200703559A (en) 2007-01-16
US20060216931A1 (en) 2006-09-28
US7521353B2 (en) 2009-04-21
EP1861874A2 (en) 2007-12-05

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