WO2006107897A3 - Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction - Google Patents

Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction Download PDF

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Publication number
WO2006107897A3
WO2006107897A3 PCT/US2006/012364 US2006012364W WO2006107897A3 WO 2006107897 A3 WO2006107897 A3 WO 2006107897A3 US 2006012364 W US2006012364 W US 2006012364W WO 2006107897 A3 WO2006107897 A3 WO 2006107897A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor
superlattice
semiconductor device
adjacent
device including
Prior art date
Application number
PCT/US2006/012364
Other languages
French (fr)
Other versions
WO2006107897A2 (en
Inventor
Robert J Mears
Robert John Stephenson
Original Assignee
Rj Mears Llc
Robert J Mears
Robert John Stephenson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rj Mears Llc, Robert J Mears, Robert John Stephenson filed Critical Rj Mears Llc
Priority to CA002603407A priority Critical patent/CA2603407A1/en
Priority to AU2006232554A priority patent/AU2006232554A1/en
Priority to EP06749182A priority patent/EP1875511A2/en
Priority to JP2008504510A priority patent/JP2008538052A/en
Publication of WO2006107897A2 publication Critical patent/WO2006107897A2/en
Publication of WO2006107897A3 publication Critical patent/WO2006107897A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
    • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • H01L29/155—Comprising only semiconductor materials
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
    • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes

Abstract

A semiconductor device may include a superlattice comprising a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base silicon monolayers defining a base silicon portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The semiconductor device may further include a semiconductor layer adjacent the superlattice and comprising at least one first region therein including a first conductivity type dopant. The superlattice may also include at least one second region therein including a second conductivity type dopant to define, with the at least one first region, at least one semiconductor junction.
PCT/US2006/012364 2005-04-01 2006-03-30 Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction WO2006107897A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CA002603407A CA2603407A1 (en) 2005-04-01 2006-03-30 Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
AU2006232554A AU2006232554A1 (en) 2005-04-01 2006-03-30 Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
EP06749182A EP1875511A2 (en) 2005-04-01 2006-03-30 Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
JP2008504510A JP2008538052A (en) 2005-04-01 2006-03-30 Semiconductor device having a superlattice having a doped region defining a semiconductor junction and an adjacent semiconductor layer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/097,588 2005-04-01
US11/097,588 US7227174B2 (en) 2003-06-26 2005-04-01 Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction

Publications (2)

Publication Number Publication Date
WO2006107897A2 WO2006107897A2 (en) 2006-10-12
WO2006107897A3 true WO2006107897A3 (en) 2007-03-15

Family

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Family Applications (1)

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PCT/US2006/012364 WO2006107897A2 (en) 2005-04-01 2006-03-30 Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction

Country Status (8)

Country Link
US (1) US7227174B2 (en)
EP (1) EP1875511A2 (en)
JP (1) JP2008538052A (en)
CN (1) CN101194364A (en)
AU (1) AU2006232554A1 (en)
CA (1) CA2603407A1 (en)
TW (1) TWI303485B (en)
WO (1) WO2006107897A2 (en)

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