WO2006109201A3 - Memory interface for volatile and non-volatile memory devices - Google Patents

Memory interface for volatile and non-volatile memory devices Download PDF

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Publication number
WO2006109201A3
WO2006109201A3 PCT/IB2006/050738 IB2006050738W WO2006109201A3 WO 2006109201 A3 WO2006109201 A3 WO 2006109201A3 IB 2006050738 W IB2006050738 W IB 2006050738W WO 2006109201 A3 WO2006109201 A3 WO 2006109201A3
Authority
WO
WIPO (PCT)
Prior art keywords
volatile
memory
interface
data
memory device
Prior art date
Application number
PCT/IB2006/050738
Other languages
French (fr)
Other versions
WO2006109201A2 (en
Inventor
Jani Klint
Sakari Sippola
Matti Floman
Jukka-Pekka Vihmalo
Original Assignee
Nokia Corp
Jani Klint
Sakari Sippola
Matti Floman
Jukka-Pekka Vihmalo
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Corp, Jani Klint, Sakari Sippola, Matti Floman, Jukka-Pekka Vihmalo filed Critical Nokia Corp
Priority to EP06711061A priority Critical patent/EP1869560B1/en
Priority to CN200680017821XA priority patent/CN101180617B/en
Priority to JP2008506001A priority patent/JP2008536230A/en
Priority to DE602006019571T priority patent/DE602006019571D1/en
Priority to KR1020097022539A priority patent/KR101140723B1/en
Priority to AT06711061T priority patent/ATE495494T1/en
Publication of WO2006109201A2 publication Critical patent/WO2006109201A2/en
Publication of WO2006109201A3 publication Critical patent/WO2006109201A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Abstract

Accessing data stored in a memory device through an interface, with addressing data on the memory device through at least one address bus, controlling at least data flow to and from the memory device through at least one command bus, and transferring data to and from the memory through at least one data bus wherein commands on the command bus are adjusted depending on the type of memory connected to the interface.
PCT/IB2006/050738 2005-04-12 2006-03-09 Memory interface for volatile and non-volatile memory devices WO2006109201A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP06711061A EP1869560B1 (en) 2005-04-12 2006-03-09 Memory interface for volatile and non-volatile memory devices
CN200680017821XA CN101180617B (en) 2005-04-12 2006-03-09 Memory interface for volatile and non-volatile memory devices
JP2008506001A JP2008536230A (en) 2005-04-12 2006-03-09 Memory interface for volatile and non-volatile memory devices
DE602006019571T DE602006019571D1 (en) 2005-04-12 2006-03-09 MEMORY INTERFACE FOR VOLATILE AND NON-VOLATILE MEMORY BLOCKS
KR1020097022539A KR101140723B1 (en) 2005-04-12 2006-03-09 Memory interface for volatile and non-volatile memory devices
AT06711061T ATE495494T1 (en) 2005-04-12 2006-03-09 MEMORY INTERFACE FOR VOLATILE AND NON-VOLATILE MEMORY DEVICES

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/105,324 US7702839B2 (en) 2005-04-12 2005-04-12 Memory interface for volatile and non-volatile memory devices
US11/105,324 2005-04-12

Publications (2)

Publication Number Publication Date
WO2006109201A2 WO2006109201A2 (en) 2006-10-19
WO2006109201A3 true WO2006109201A3 (en) 2007-02-08

Family

ID=37084415

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2006/050738 WO2006109201A2 (en) 2005-04-12 2006-03-09 Memory interface for volatile and non-volatile memory devices

Country Status (10)

Country Link
US (2) US7702839B2 (en)
EP (1) EP1869560B1 (en)
JP (1) JP2008536230A (en)
KR (2) KR101140723B1 (en)
CN (1) CN101180617B (en)
AT (1) ATE495494T1 (en)
DE (1) DE602006019571D1 (en)
MY (1) MY143636A (en)
TW (1) TWI435334B (en)
WO (1) WO2006109201A2 (en)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7702839B2 (en) * 2005-04-12 2010-04-20 Nokia Corporation Memory interface for volatile and non-volatile memory devices
JP2007053691A (en) * 2005-08-19 2007-03-01 Micron Technol Inc Extended digital data route structure using sub-lsb
US8074022B2 (en) * 2006-09-28 2011-12-06 Virident Systems, Inc. Programmable heterogeneous memory controllers for main memory with different memory modules
US7761625B2 (en) * 2006-09-28 2010-07-20 Virident Systems, Inc. Methods for main memory with non-volatile type memory modules, and related technologies
WO2008040028A2 (en) * 2006-09-28 2008-04-03 Virident Systems, Inc. Systems, methods, and apparatus with programmable memory control for heterogeneous main memory
US7761623B2 (en) * 2006-09-28 2010-07-20 Virident Systems, Inc. Main memory in a system with a memory controller configured to control access to non-volatile memory, and related technologies
US8949555B1 (en) 2007-08-30 2015-02-03 Virident Systems, Inc. Methods for sustained read and write performance with non-volatile memory
US9984012B2 (en) 2006-09-28 2018-05-29 Virident Systems, Llc Read writeable randomly accessible non-volatile memory modules
US7761624B2 (en) * 2006-09-28 2010-07-20 Virident Systems, Inc. Systems and apparatus for main memory with non-volatile type memory modules, and related technologies
US20080082750A1 (en) * 2006-09-28 2008-04-03 Okin Kenneth A Methods of communicating to, memory modules in a memory channel
US7761626B2 (en) * 2006-09-28 2010-07-20 Virident Systems, Inc. Methods for main memory in a system with a memory controller configured to control access to non-volatile memory, and related technologies
US20090276556A1 (en) * 2006-10-04 2009-11-05 Mediatek Inc. Memory controller and method for writing a data packet to or reading a data packet from a memory
US7739539B2 (en) * 2006-10-13 2010-06-15 Atmel Corporation Read-data stage circuitry for DDR-SDRAM memory controller
WO2008051940A2 (en) 2006-10-23 2008-05-02 Virident Systems, Inc. Methods and apparatus of dual inline memory modules for flash memory
US7913055B2 (en) * 2006-11-04 2011-03-22 Virident Systems Inc. Seamless application access to hybrid main memory
WO2008154625A2 (en) * 2007-06-12 2008-12-18 Rambus Inc. In-dram cycle-based levelization
US9921896B2 (en) 2007-08-30 2018-03-20 Virident Systems, Llc Shutdowns and data recovery to avoid read errors weak pages in a non-volatile memory system
JP2009176136A (en) 2008-01-25 2009-08-06 Toshiba Corp Semiconductor storage device
WO2009102821A2 (en) * 2008-02-12 2009-08-20 Virident Systems, Inc. Methods and apparatus for two-dimensional main memory
US8856464B2 (en) * 2008-02-12 2014-10-07 Virident Systems, Inc. Systems for two-dimensional main memory including memory modules with read-writeable non-volatile memory devices
US8359423B2 (en) * 2008-03-14 2013-01-22 Spansion Llc Using LPDDR1 bus as transport layer to communicate to flash
US8745314B1 (en) 2008-06-24 2014-06-03 Virident Systems, Inc. Methods for a random read and read/write block accessible memory
US9513695B2 (en) 2008-06-24 2016-12-06 Virident Systems, Inc. Methods of managing power in network computer systems
EP2652741B1 (en) * 2010-12-17 2019-02-20 Everspin Technologies, Inc. Memory controller and method for interleaving dram and mram accesses
US8607089B2 (en) * 2011-05-19 2013-12-10 Intel Corporation Interface for storage device access over memory bus
US8738852B2 (en) * 2011-08-31 2014-05-27 Nvidia Corporation Memory controller and a dynamic random access memory interface
KR101959853B1 (en) * 2012-04-09 2019-03-19 삼성전자주식회사 MRAM : Magnetic random access memory device having division addressing type
US10089224B2 (en) * 2013-03-15 2018-10-02 The Boeing Company Write caching using volatile shadow memory
KR20170059239A (en) * 2015-11-20 2017-05-30 삼성전자주식회사 Memory device and memory system having heterogeneous memories
CN108139994B (en) * 2016-05-28 2020-03-20 华为技术有限公司 Memory access method and memory controller
US10380060B2 (en) 2016-06-17 2019-08-13 Etron Technology, Inc. Low-pincount high-bandwidth memory and memory bus
US10789010B2 (en) * 2016-08-26 2020-09-29 Intel Corporation Double data rate command bus
US11586565B2 (en) * 2016-10-03 2023-02-21 Samsung Electronics Co., Ltd. Non-volatile storage system and data storage access protocol for non-volatile storage devices
US10332582B2 (en) 2017-08-02 2019-06-25 Qualcomm Incorporated Partial refresh technique to save memory refresh power
US10579578B2 (en) * 2017-10-24 2020-03-03 Micron Technology, Inc. Frame protocol of memory device
CN117067721A (en) * 2017-12-15 2023-11-17 康宁股份有限公司 Laminated glass ceramic article with UV and NIR blocking properties and method of making same
KR102646630B1 (en) 2018-10-01 2024-03-11 삼성전자주식회사 Method to issue write protect commands on dynamic random-access memory(dram) cells in a system run-time environment
CN109460665B (en) * 2018-10-25 2022-08-16 石生花微电子(南京)有限公司 Device and method for protecting sensitive information in chip
US10797700B2 (en) 2018-12-21 2020-10-06 Samsung Electronics Co., Ltd. Apparatus for transmitting and receiving a signal, a method of operating the same, a memory device, and a method of operating the memory device
JP6970244B1 (en) * 2020-06-23 2021-11-24 華邦電子股▲ふん▼有限公司Winbond Electronics Corp. Memory controller
JP2022049552A (en) 2020-09-16 2022-03-29 キオクシア株式会社 Semiconductor device and method
JP2022049553A (en) 2020-09-16 2022-03-29 キオクシア株式会社 Semiconductor device and method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5872940A (en) * 1996-04-01 1999-02-16 Motorola, Inc. Programmable read/write access signal and method therefor
WO2001042929A1 (en) * 1999-12-08 2001-06-14 Rambus Inc Memory system with channel multiplexing of multiple memory devices

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL96808A (en) 1990-04-18 1996-03-31 Rambus Inc Integrated circuit i/o using a high performance bus interface
US5377264A (en) * 1993-12-09 1994-12-27 Pitney Bowes Inc. Memory access protection circuit with encryption key
US5826068A (en) * 1994-11-09 1998-10-20 Adaptec, Inc. Integrated circuit with a serial port having only one pin
JP3626258B2 (en) * 1995-08-25 2005-03-02 株式会社東芝 Computer system
US6185637B1 (en) * 1998-04-15 2001-02-06 Advanced Micro Devices, Inc. System for implementing an adaptive burst length for burst mode transactions of a memory by monitoring response times for different memory regions
DE19819531C1 (en) * 1998-04-30 1999-12-02 Siemens Ag RISC processor with a debug interface unit
US6154819A (en) * 1998-05-11 2000-11-28 Intel Corporation Apparatus and method using volatile lock and lock-down registers and for protecting memory blocks
US6260127B1 (en) * 1998-07-13 2001-07-10 Compaq Computer Corporation Method and apparatus for supporting heterogeneous memory in computer systems
US6467009B1 (en) * 1998-10-14 2002-10-15 Triscend Corporation Configurable processor system unit
JP2000172554A (en) * 1998-12-01 2000-06-23 Ricoh Co Ltd Image formation device using sdram
US6732208B1 (en) * 1999-02-25 2004-05-04 Mips Technologies, Inc. Low latency system bus interface for multi-master processing environments
JP2000250661A (en) * 1999-02-26 2000-09-14 Hitachi Ltd Semiconductor integrated circuit and memory card
US6603752B1 (en) * 1999-07-29 2003-08-05 Ahmed Saifuddin Method and system for controlling transmission energy in a variable rate gated communication system
US6490638B1 (en) * 1999-08-23 2002-12-03 Advanced Micro Devices, Inc. General purpose bus with programmable timing
US6240042B1 (en) * 1999-09-02 2001-05-29 Micron Technology, Inc. Output circuit for a double data rate dynamic random access memory, double data rate dynamic random access memory, method of clocking data out from a double data rate dynamic random access memory and method of providing a data strobe signal
US6526469B1 (en) * 1999-11-12 2003-02-25 International Business Machines Corporation Bus architecture employing varying width uni-directional command bus
JP4299428B2 (en) * 2000-01-19 2009-07-22 三星電子株式会社 Variable capacity semiconductor memory device
AU2001249686A1 (en) * 2000-03-30 2001-10-15 Micron Technology, Inc. Interface command architecture for synchronous flash memory
US20020010007A1 (en) * 2000-06-16 2002-01-24 Telefonaktiebolaget L M Ericsson (Publ) Method and means for a portable device in a wireless communication system
US20050135180A1 (en) * 2000-06-30 2005-06-23 Micron Technology, Inc. Interface command architecture for synchronous flash memory
KR100652362B1 (en) * 2000-09-20 2006-11-30 삼성전자주식회사 Semiconductor memory device having fixed cas latency at normal operation and various cas latency at test mode
JP2002107240A (en) 2000-09-28 2002-04-10 Hitachi Metals Ltd Torque transmission shaft and torque sensor using it
JP4722305B2 (en) * 2001-02-27 2011-07-13 富士通セミコンダクター株式会社 Memory system
GB2373595B (en) * 2001-03-15 2005-09-07 Italtel Spa A system of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol
JP4049297B2 (en) * 2001-06-11 2008-02-20 株式会社ルネサステクノロジ Semiconductor memory device
US6754119B2 (en) * 2001-07-26 2004-06-22 Samsung Electronics Co., Ltd. Sense amplifier for memory device
JP3799251B2 (en) * 2001-08-24 2006-07-19 エルピーダメモリ株式会社 Memory device and memory system
US6846738B2 (en) * 2002-03-13 2005-01-25 Micron Technology, Inc. High permeability composite films to reduce noise in high speed interconnects
US7039734B2 (en) * 2002-09-24 2006-05-02 Hewlett-Packard Development Company, L.P. System and method of mastering a serial bus
US6954809B2 (en) * 2002-09-27 2005-10-11 Via Technologies, Inc. Apparatus and method for accessing computer system resources via serial bus
US7142461B2 (en) * 2002-11-20 2006-11-28 Micron Technology, Inc. Active termination control though on module register
US7308524B2 (en) * 2003-01-13 2007-12-11 Silicon Pipe, Inc Memory chain
US6982671B2 (en) * 2003-02-25 2006-01-03 Harris Corporation Slot fed microstrip antenna having enhanced slot electromagnetic coupling
KR100555498B1 (en) * 2003-04-18 2006-03-03 삼성전자주식회사 Transmitter, receiver and data interface system for improving data transmission speed
US6922770B2 (en) * 2003-05-27 2005-07-26 Sony Corporation Memory controller providing dynamic arbitration of memory commands
DE102004003323A1 (en) * 2004-01-22 2005-08-18 Infineon Technologies Ag Semiconductor memory device and circuit arrangement
JP2006058831A (en) 2004-03-29 2006-03-02 Jsr Corp Photosensitive resin composition for optical waveguide and optical waveguide
US7803262B2 (en) * 2004-04-23 2010-09-28 Florida State University Research Foundation Alignment of carbon nanotubes using magnetic particles
DE102004023315A1 (en) * 2004-05-07 2005-12-15 Carl Freudenberg Kg Sealing arrangement with sensor
US7702839B2 (en) * 2005-04-12 2010-04-20 Nokia Corporation Memory interface for volatile and non-volatile memory devices
CN101253700A (en) * 2005-08-05 2008-08-27 诺基亚公司 Power control for gated uplink control channel

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5872940A (en) * 1996-04-01 1999-02-16 Motorola, Inc. Programmable read/write access signal and method therefor
WO2001042929A1 (en) * 1999-12-08 2001-06-14 Rambus Inc Memory system with channel multiplexing of multiple memory devices

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"DIRECT RAMBUS RIMM MODULE", DIRECT RAMBUS RIMM MODULE, August 1998 (1998-08-01), pages 1 - 16, XP002926177 *

Also Published As

Publication number Publication date
US20080162768A1 (en) 2008-07-03
KR100948090B1 (en) 2010-03-16
KR101140723B1 (en) 2012-05-24
DE602006019571D1 (en) 2011-02-24
US7702839B2 (en) 2010-04-20
CN101180617B (en) 2010-05-19
ATE495494T1 (en) 2011-01-15
US20060230250A1 (en) 2006-10-12
KR20070120596A (en) 2007-12-24
TWI435334B (en) 2014-04-21
EP1869560B1 (en) 2011-01-12
WO2006109201A2 (en) 2006-10-19
CN101180617A (en) 2008-05-14
US8635394B2 (en) 2014-01-21
KR20090125847A (en) 2009-12-07
TW200643970A (en) 2006-12-16
MY143636A (en) 2011-06-15
JP2008536230A (en) 2008-09-04
EP1869560A2 (en) 2007-12-26

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