WO2006136986A2

WO2006136986A2 - Device and a method for embedding a secondary information signal in the channel data stream of a primary information signal using scrambling

Info

Publication number: WO2006136986A2
Application number: PCT/IB2006/051923
Authority: WO
Inventors: Peter Bentvelsen; Jo Frisson; Engelbertus P. G. M. Kramer
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2005-06-21
Filing date: 2006-06-15
Publication date: 2006-12-28
Also published as: TW200705393A; WO2006136986A3

Abstract

The present invention relates to a device and a corresponding method for embedding a secondary information signal (S) in the channel data stream (Cl) of a primary information signal (P) to obtain a modulation stream (M). In order to avoid the formation of regular modulation patterns which might lead to unwanted frequency peaks in the power spectrum of the modulation signal, a device is proposed comprising: a scrambling unit (11) for scrambling the secondary channel bits of said secondary information signal (S) according to a scrambling rule, and a setting unit (12) for setting the polarity of said channel data stream (Cl) at predetermined positions based on the binary value of the scrambled secondary channel bits (C2). The present invention relates also to a device and a corresponding method for extracting from a modulation stream (M) a secondary information signal (S) embedded in scrambled form in the channel data stream (Cl) of a primary information signal (P), and to a record carrier and a signal carrying such a modulation stream.

Description

Device and a method for embedding a secondary information signal in the channel data stream of a primary information signal using scrambling

The present invention relates to a device and a method for embedding a secondary information signal in the channel data stream of a primary information signal to obtain a modulation stream. Further, the present invention relates to a device and a method for extracting from a modulation stream a secondary information signal embedded in scrambled form in the channel data stream of a primary information signal. Still further, the present invention relates to a record carrier and a signal carrying a modulation stream storing a secondary information signal embedded in scrambled form in the channel data stream of a primary information signal. Finally, the present invention relates to a computer program for implementing said methods on a computer.

For copy protection and digital rights management it is often necessary to store a key on the disc. WO 02/15185 Al (PHNL000451) discloses how to encode and decode a secondary signal in a RLL code. The secondary signal is stored in the absolute polarity at a predetermined position in the NRZI channel bit stream; this polarity is set using a degree of freedom existing in the operation of the DC-control means (for CD: merging bits; for DVD: primary/secondary syncs, main/substitution table, state flip; for BD: DC-control bits). This is, for instance, done as follows: a secondary channel bit with value zero is encoded as polarity low (low reflectance, as pit or written mark), while a secondary channel bit with value one is encoded as polarity high (high reflectance, as land between pits or written marks).

The accumulated digital sum value (DSV) shall be minimized to keep the low frequency content of the modulated signal as small as possible. If at a predetermined position a degree of freedom in the DC-control is used to encode a secondary channel bit instead of minimization of the DSV, the low frequency content will generally increase.

If the secondary channel bits as described above are encoded into polarity settings, in particular at regular intervals in the bit stream, then in the case that the secondary channel data has a constant value or is a repetitive or otherwise regular pattern, the power spectrum will have spikes at the repetition frequencies of the secondary channel bit positions. Such spikes are undesired since they might disturb, for instance, the servo control.

It is an object of the present invention to provide devices and methods as well as a record carrier and a signal as described above, by which the formation of regular modulation patterns which might lead to unwanted frequency peaks in the power spectrum of the modulation signal are avoided.

The object is achieved according to the present invention by an embedding device as claimed in claim 1 comprising: a scrambling unit for scrambling the secondary channel bits of said secondary information signal according to a scrambling rule, and a setting unit for setting the polarity of said channel data stream at predetermined positions based on the binary value of the scrambled secondary channel bits The object is further achieved according to the present invention by an extracting device as claimed in claim 13 comprising: a detection unit for detecting the polarity of said modulation stream at predetermined positions to obtain scrambled secondary channel bits of said secondary information signal, and - a descrambling unit for descrambling said scrambled secondary channel bits according to a descrambling rule corresponding to a scrambling rule used for scrambling the secondary channel bits to obtain said scrambled secondary channel bits during embedding of said secondary information signal in the channel data stream of said primary information signal. The object is still further achieved according to the present invention by a record carrier and a corresponding signal as claimed in claims 15 and 16 wherein the polarity of said channel data stream is set at predetermined positions based on the binary value of scrambled secondary channel bits, said secondary channel bits of said secondary information signal being scrambled according to a scrambling rule. A computer program proposed according to the present invention for implementing the methods as claimed in claims 12 and 14 on a computer is defined in claim

17.

The present invention is based on the idea, to generally use the known concept for embedding the secondary information signal into the channel data stream of the primary information signal, but to scramble the secondary channel bits beforehand in order to minimize unwanted frequency components in the signal spectrum. By randomizing the input information bits of the secondary signal, the polarity setting at the secondary channel bit location is randomized. In this way it is avoided that regular modulation patterns are formed so that unwanted frequency peaks in the power spectrum of the modulation signal are efficiently avoided according to the present invention.

According to a preferred embodiment of the invention is proposed to use scrambling bits for scrambling the secondary channel bits derived from channel bits of the channel data stream of the primary information signal. This has the advantage that the device for extracting the secondary information signal from a modulation stream can easily descramble the scrambled secondary channel bits since it will also be provided with the channel bits of the channel data stream of the primary information signal enabling it to reconstruct the scrambling bits. Thus, no additional information needs to be transmitted from an encoder to a decoder, but just the way in which such scrambling bits are formed has to be known to both, the encoder and the decoder, i.e. the decoder has to use a descrambling rule that corresponds and is complementary to the scrambling rule during by the encoder. These rules are preferably predetermined and reconstructable.

Preferably such scrambling bits are derived from address information bits of the channel data stream. Such address information bits can, for instance, be the physical sector number. This has the advantage that the secondary channel information is linked to a specific location within the primary channel. This has two advantages: a) to decode the secondary channel information it is not sufficient to retrieve the secondary channel bits at the predetermined locations, but also the primary channel has to be decoded; b) if the secondary channel user data is repeated several times, e.g. over several ECC-blocks, the corresponding secondary channelbit data is different for each repetition as a result of differences in the scrambling preset for each ECC-block.

Both advantages pose an increased difficulty for unauthorized decoding attempts.

Generally, any kind of scrambling can be applied for the purpose of the invention as long as both the device for embedding and the device for extracting know the particular scrambling/descrambling rule so that both apply the same scrambling/descrambling scheme. This means further that generally any kind of means for determining scrambling bits can be used. In a preferred embodiment a shift register, in particular a linear feedback shift register, is used for this purpose as it is generally known and used for a scrambling of the main channel data bits in BD. Such a shift register can be easily implemented and requires only a limited number of calculations.

Said shift register is preferably loaded with an initial information from which an initial scrambling word is taken for scrambling a first secondary information word, a word meaning preferably one byte of 8 bits. Subsequently, one or more predetermined shifts are performed to obtain further scrambling words for scrambling further secondary information words.

For instance, as proposed according to a further embodiment, all secondary information words to be embedded in one ECC cluster of the channel data stream are scrambled using the scrambling words which are obtained starting from the same initial information loaded into this shift register. Thus, for each new ECC cluster a new start is made by loading a new information into the shift register leading to the advantages described above when using address information for deriving the scrambling bits.

Preferably, the initial information is a number of predetermined address information bits of the physical sector number of an ECC cluster into which said scrambled secondary channel bits shall be embedded for deriving said scrambling bits. Thus, the scrambling rule determines which bits of the physical sector number are to be loaded into the shift register and how the shift register shall be shifted. In addition, contents of the shift register can also be subjected to another operation, for instance one or more predetermined logic operations for forming said scrambling bits.

For embedding of the scrambled secondary channel bits in the channel data stream of the primary information signal the polarity of the channel data stream is preferably set in the frame sync, in particular in a long run length in the frame sync, preferably in the first long run length thereof. Thus, in this embodiment one secondary channel bit can be embedded in each frame sync.

For setting the polarity at a predetermined position many different possibilities are available as described in the prior art. According to an advantageous embodiment one or more DC-control bits are set in front of the predetermined position to control the polarity of the subsequent frame sync. However, other possibilities exist, in particular for other optical storage systems than BD.

The present invention will now be explained in more detail with reference to the drawings in which Fig. 1 shows different DSV power spectra illustrating the effect of the invention,

Fig. 2 illustrates how a polarity can be set in a modulation stream,

Fig. 3 shows polarity control using DC-control bits,

Fig. 4 shows the data format of one ECC cluster of secondary channel bits,

Fig. 5 shows an embodiment of a scrambling circuit according to the present invention,

Fig. 6 shows a block diagram of an encoder according to the present invention, and Fig. 7 shows a block diagram of a decoder according to the present invention.

In Fig. 1 the low frequency part of the power spectrum is shown for three modulation streams in DVD. Spectrum A is from a normal DVD modulation stream that is encoded using the DC-control strategy as described in annex J.I of the DVD Specification for Read-only disc, part 1 Physical Specifications. Spectrum B shows an example of a DVD modulation stream that contains one secondary channel bit in each main channel sync frame (encoded as described in WO 02/15185 Al), where the secondary channel bits consist of a regular data pattern. Spectrum C shows an example of a DVD modulation stream that contains one secondary channel bit in each main channel sync frame (encoded as described in WO 02/15185 Al), but where the secondary channel bits are essentially random as proposed according to the present invention. It will be explained in detail in the following how this can be obtained based on an example for BD rewritable format.

According to this example a secondary channel bit (obtained from the secondary information signal by secondary channel preprocessing, such as adding of CRC and/or ECC bits), is stored in the first 9T runlength of a recording frame sync. An ECC cluster in BD contains 496 frame syncs of which all or a limited number can be used for storing the secondary channel bits. The 17PP modulation stream in BD can result in two signal polarities in the NRZI modulation stream as shown in Fig. 2. The correspondence between the secondary channel bit value and the modulation signal polarity can be defined as follows. The secondary channel bit is '0' if the polarity of the modulation signal is low, corresponding to a written mark on the disc. The secondary channel bit is '1' if the polarity of the modulation signal is high, corresponding to a land between written marks on the disc. However, the definition can also be made vice versa.

In the BD format, DC-control bits inserted in the data bit stream are used to minimize the accumulated DSV of the modulation bit stream. If a DC-control bit is set to ' 1 ', the polarity of the recorded signal is inverted. For the encoding of the secondary channel data bits, the polarity of the sync of recording frame N+l is controlled by setting one or more DC- control bits of recording frame N to such a value that the secondary channel bit in the sync of the next recording frame has the desired polarity as shown in Fig. 3. As a result of this way of encoding the low frequency spectrum of the modulated signal will increase, and locally the accumulated DSV will not be minimized. Some examples how the polarity can be controlled by setting the DC-control bits are described in European patent application EP 04105194 (PHNL 041167) to which reference is herewith made.

In a preferred embodiment for BD, as shown in Fig. 4, the secondary channel bits are organized, for instance, as 400 secondary information bits, 16 bits CRC and 80 bits of ECC protecting the secondary information bits and the CRC, in total 496 bits. Preferably, the most significant bit is written first.

As mentioned above, it is preferred that for error detection a 16-bit Cyclic Redundancy Check (CRC) is added to the 400 secondary information bits. The initial value for the calculation of the CRC is zero. The CRC-field contains the inverted parity bits. The resulting 18 bytes are numbered A₂₇ to A₁₀.

The 18 bytes A₂₇ to A₁₀ containing the secondary information bits and inverted CRC are now scrambled. In a preferred embodiment the output of the scrambling circuit shown in Fig. 5 is used for this purpose, in which bits S₇ (msb) to S₀ (lsb) represent a scrambling byte at each 8-bit shift. This scrambling circuit comprises a Linear Feedback Shift Register (LFSR) based on the polynomial Φ(x) = x¹⁶ + x¹⁵ + x¹³ + x⁴ + 1. The positions S₀ to S₁₅ form a 16-bit shift register. At each shift clock the content of S_n is shifted to s_n+i (n = 0...14), while S₀ is set to S₁₅ ® S₁₄ ® S₁₂ ® S₃, where ® stands for a logic Exclusive-OR operation.

At the beginning of the scrambling procedure of each secondary channel bits frame, the shift register is, according to this preferred embodiment, preset with a value derived from the first (virtual) Physical Sector Number (PSN) of the ECC cluster where the secondary channel bits frames are located. The way the presets are derived from the PSN is also shown in Fig. 5. After loading the preset value, S₇ ...S₀ are taken out as scrambling byte S₂₇. Then an 8-bit shift is repeated 17 times and the following 17 bytes are taken from s₇ ... S₀ as the scrambling bytes S₂₆ to S₁₀. The 18 bytes Ak of secondary channel bits thus become scrambled secondary channel bytes Bk where Bk = Ak θ Sk for k = 27 to 10, where ® stands for Exclusive-Or.

Thereafter, the scrambled channel bytes are preferably extended with error correction information.

The secondary channel user data and CRC can optionally be protected by an Error Correction Code, e.g. a Reed-Solomon code, in this example a [62, 52, 11]-RS code. Of course, other scrambling schemes than that shown in Fig. 5, e.g. using other preset values, other logical operations and/or other shifts can be applied as well. The embodiment shown in Fig. 5 just shall illustrate one non-binding example.

Fig. 6 shows a simple block diagram of an encoder according to the present invention. It comprises a first preprocessing unit 10 for channel preprocessing of the primary channel user data P, for instance for adding a CRC, interleaving and/or error correction. Further, it comprises a second preprocessing unit 11 for channel preprocessing of the secondary channel user data S. Said preprocessing comprises, more or less, the same or similar steps as the preprocessing of the primary channel user data P performed in the first preprocessing unit 10. However, as proposed according to the present invention, said second preprocessing unit 11 is further adapted for a scrambling of the secondary channel user data as described above. For this purpose the physical sector number PSN of the current ECC cluster into which one secondary channel information bit shall be embedded is provided as input to the second preprocessing unit 11 from the output of the first preprocessing unit 10.

The encoder shown in Fig. 6 further comprises a modulation encoding and embedding unit 12 for modulation encoding of the primary channel bit stream 1 outputted from the first preprocessing unit 10 and for embedding therein the preprocessed and scrambled secondary channel bit stream C2 outputted from the second preprocessing unit 11. This embedding is done, according to this preferred embodiment for BD, by setting the polarity in one, e.g. the first, of the long run lengths of the frame sync such that the polarity at this location of the modulation bit stream M represents the bit value of the secondary channel bit stream C2 to be embedded at this location (see Fig. 2). This polarity setting can be done by setting one or more DC control bits of the previous recording frame to appropriate values which is possible due to the degree of freedom available in the DC control. The finally outputted modulation bit stream M can be stored on a record carrier or transmitted as a signal, for instance via a transmission line. Due to this scrambling of the secondary channel user data S it is achieved that the spectrum of the modulation bit stream M does not show undesired spikes which could disturb the servo control. A block diagram of an embodiment of a decoder according to the present invention is shown in Fig. 7. It comprises a modulation decoding and extracting unit 20 for modulation decoding of the inputted modulation stream M and for extracting therefrom the secondary channel bit stream C2 which has been embedded therein as described above. In a first processing unit 21 the primary channel bit stream Cl is processed in the usual way (corresponding to the processing performed in the first preprocessing unit 10 of the encoder). In a second processing unit 22 the secondary channel bit stream C2 extracted from the modulation stream M is processed including descrambling consistent with the preprocessing and scrambling performed in the second preprocessing unit 11 during encoding. For enabling this descrambling, the physical sector number PSN is again provided from the first processing unit 21 to the second processing unit 22 to use the same scrambling method (inversely) as has been applied during encoding. Thus, the primary and secondary channel user data streams P, S are obtained.

In the above a very detailed embodiment has been described for use in BD. However, it is to be noted that the present invention is not limited to this very detailed embodiment, neither to the use in BD and the way of setting polarities therein, nor to the use of the particular scrambling method explained above. Generally, the invention can be applied in any optical storage system, such as CD, DVD, BD or any future system, where a secondary information signal can be embedded in the primary channel bit stream of a primary information signal by setting the polarity at a predetermined location to represent one bit value of a secondary information bit.

Furthermore, any other scrambling method can be used as well as long as it is ensured that during encoding and decoding the same scrambling method is used. For instance, the scrambling method can be fixed in advance and pre-stored in the encoder and decoder. As an alternative, the scrambling method could also be stored in the modulation stream itself so that information about the scrambling method applied during encoding is carried along with the modulation stream from the encoder to the decoder. For instance, this information could be stored on a record carrier together with the modulation stream.

As it has been shown above it is preferred that information from the primary channel bit stream is used for scrambling of the secondary channel bit stream. In the above described embodiment the PSN has been used for this purpose which is loaded to a linear feedback shift register in which subsequently further scrambling words are calculated. However, it is well possible to use other information from the primary channel bit stream for this purpose and/or to use other calculation means for determining such scrambling words, also without using any information from the primary channel bit stream.

Claims

CLAIMS:

1. Device for embedding a secondary information signal (S) in the channel data stream (Cl) of a primary information signal (P) to obtain a modulation stream (M) comprising: a scrambling unit (11) for scrambling the secondary channel bits of said secondary information signal (S) according to a scrambling rule, and a setting unit (12) for setting the polarity of said channel data stream (Cl) at predetermined positions based on the binary value of the scrambled secondary channel bits (C2).

2. Device as claimed in claim 1, wherein said scrambling unit (11) is adapted for using scrambling bits for scrambling said secondary channel bits derived from channel bits of said channel data stream (Cl) of said primary information signal (P).

3. Device as claimed in claim 1, wherein said scrambling unit (11) is adapted for using scrambling bits for scrambling said secondary channel bits derived from address information bits of said channel data stream (Cl).

4. Device as claimed in claim 3, wherein said scrambling unit (11) is adapted for using address information bits of the location in said channel data stream (Cl) at which said scrambled secondary channel bits (C2) shall be embedded for deriving said scrambling bits.

5. Device as claimed in claim 4, wherein said scrambling unit (11) is adapted for using the physical sector number (PSN) of an ECC cluster into which said scrambled secondary channel bits (2) shall be embedded for deriving said scrambling bits.

6. Device as claimed in claim 1, wherein said scrambling unit (11) comprises a shift register, in particular a linear feedback shift register, for determining scrambling bits for scrambling said secondary channel bits.

7. Device as claimed in claim 6, wherein said scrambling unit (11) is adapted for loading said shift register with an initial information from which an initial scrambling word is taken for scrambling a first secondary information word, and wherein said shift register is adapted for subsequently performing one or more predetermined shifts to obtain further scrambling words for scrambling further secondary information words.

8. Device as claimed in claim 7, wherein for all secondary information words to be embedded in one ECC cluster of said channel data stream (Cl) scrambling words starting from the same initial information loaded into said shift register are taken for scrambling.

9. Device as claimed in claim 7, wherein said initial information is a number of predetermined address information bits of the physical sector number of an ECC cluster into which said scrambled secondary channel bits (C2) shall be embedded for deriving said scrambling bits.

10. Device as claimed in claim 1, wherein said setting unit is adapted for setting the polarity of said channel data stream (Cl) in the frame sync, in particular in a long runlength in the frame sync.

11. Device as claimed in claim 1, wherein said setting unit (12) is adapted for setting the polarity at said predetermined position by setting one or more DC-control bits before said predetermined position in said channel data stream (Cl) to such a value that the polarity at said predetermined position has the desired polarity.

12. Method of embedding a secondary information signal (S) in the channel data stream (Cl) of a primary information signal (P) to obtain a modulation stream (M) comprising the steps of: scrambling the secondary channel bits of said secondary information signal (S) according to a scrambling rule, and - setting the polarity of said channel data stream (Cl) at predetermined positions based on the binary value of the scrambled secondary channel bits (C2).

13. Device for extracting from a modulation stream (M) a secondary information signal (S) embedded in scrambled form in the channel data stream (Cl) of a primary information signal (P) comprising: a detection unit (20) for detecting the polarity of said modulation stream (M) at predetermined positions to obtain scrambled secondary channel bits (C2) of said secondary information signal (S), and - a descrambling unit (21) for descrambling said scrambled secondary channel bits (C2) according to a descrambling rule corresponding to a scrambling rule used for scrambling the secondary channel bits of said secondary information signal (S) to obtain said scrambled secondary channel bits (C2) during embedding of said secondary information signal (S) in the channel data stream (Cl) of said primary information signal (P).

14. Method of extracting from a modulation stream (M) a secondary information signal (S) embedded in scrambled form in the channel data stream (Cl) of a primary information signal (P) comprising the steps of: detecting the polarity of said modulation stream (M) at predetermined positions to obtain scrambled secondary channel bits (C2) of said secondary information signal (S), and descrambling said scrambled secondary channel bits (C2) according to a descrambling rule corresponding to a scrambling rule used for scrambling the secondary channel bits (Cl) to obtain said scrambled secondary channel bits of said secondary information signal (S) during embedding of said secondary information signal (S) in the channel data stream (Cl) of said primary information signal (P).

15. Record carrier carrying a modulation stream (M) storing a secondary information signal (S) embedded in scrambled form in the channel data stream (Cl) of a primary information signal (P), wherein the polarity of said channel data stream (Cl) is set at predetermined positions based on the binary value of scrambled secondary channel bits (C2), said secondary channel bits (C2) of said secondary information signal (S) being scrambled according to a scrambling rule.

16. Binary signal carrying a modulation stream (M) storing a secondary information signal (S) embedded in scrambled form in the channel data stream (Cl) of a primary information signal (P), wherein the polarity of said channel data stream (Cl) is set at predetermined positions based on the binary value of scrambled secondary channel bits (C2), said secondary channel bits (C2) of said secondary information signal (S) being scrambled according to a scrambling rule.

17. Computer program comprising program code means for causing a computer to carry out the steps of the method as claimed in claims 12 or 14 when said program is executed on a computer.