WO2007002445A3 - Memory micro-tiling speculative returns - Google Patents

Memory micro-tiling speculative returns Download PDF

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Publication number
WO2007002445A3
WO2007002445A3 PCT/US2006/024546 US2006024546W WO2007002445A3 WO 2007002445 A3 WO2007002445 A3 WO 2007002445A3 US 2006024546 W US2006024546 W US 2006024546W WO 2007002445 A3 WO2007002445 A3 WO 2007002445A3
Authority
WO
WIPO (PCT)
Prior art keywords
request
speculative
tiling
returns
access
Prior art date
Application number
PCT/US2006/024546
Other languages
French (fr)
Other versions
WO2007002445A2 (en
Inventor
James Akiyama
William Clifford
Original Assignee
Intel Corp
James Akiyama
William Clifford
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, James Akiyama, William Clifford filed Critical Intel Corp
Priority to EP06785466A priority Critical patent/EP1894112B1/en
Priority to JP2008518454A priority patent/JP4879981B2/en
Priority to AT06785466T priority patent/ATE464605T1/en
Priority to CN2006800203777A priority patent/CN101208672B/en
Priority to DE602006013627T priority patent/DE602006013627D1/en
Publication of WO2007002445A2 publication Critical patent/WO2007002445A2/en
Publication of WO2007002445A3 publication Critical patent/WO2007002445A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests

Abstract

According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic and a transaction assembler. The assignment logic receives a request to access a memory channel and assigns the request to access one of two or more independently addressable subchannels within the channel. The transaction assembler combines the request with one or more additional requests to access the two or more independently addressable subchannels within the channel and facilitates a speculative return of data from a subchannel for which a subchannel request is not available.
PCT/US2006/024546 2005-06-23 2006-06-23 Memory micro-tiling speculative returns WO2007002445A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP06785466A EP1894112B1 (en) 2005-06-23 2006-06-23 Memory micro-tiling speculative returns
JP2008518454A JP4879981B2 (en) 2005-06-23 2006-06-23 Speculative return by micro tiling of memory
AT06785466T ATE464605T1 (en) 2005-06-23 2006-06-23 SPECULATIVE MICRO-TILING RETURNS OF A MEMORY
CN2006800203777A CN101208672B (en) 2005-06-23 2006-06-23 Memory micro-tiling speculative returns
DE602006013627T DE602006013627D1 (en) 2005-06-23 2006-06-23 SPECULATIVE MICRO-TILING RETURNS OF A MEMORY

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/165,390 2005-06-23
US11/165,390 US7587521B2 (en) 2005-06-23 2005-06-23 Mechanism for assembling memory access requests while speculatively returning data

Publications (2)

Publication Number Publication Date
WO2007002445A2 WO2007002445A2 (en) 2007-01-04
WO2007002445A3 true WO2007002445A3 (en) 2007-06-28

Family

ID=37545366

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/024546 WO2007002445A2 (en) 2005-06-23 2006-06-23 Memory micro-tiling speculative returns

Country Status (9)

Country Link
US (1) US7587521B2 (en)
EP (1) EP1894112B1 (en)
JP (1) JP4879981B2 (en)
KR (1) KR100958264B1 (en)
CN (1) CN101208672B (en)
AT (1) ATE464605T1 (en)
DE (1) DE602006013627D1 (en)
TW (1) TWI328169B (en)
WO (1) WO2007002445A2 (en)

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Also Published As

Publication number Publication date
TW200712886A (en) 2007-04-01
EP1894112A2 (en) 2008-03-05
ATE464605T1 (en) 2010-04-15
US20060294264A1 (en) 2006-12-28
KR100958264B1 (en) 2010-05-19
JP4879981B2 (en) 2012-02-22
DE602006013627D1 (en) 2010-05-27
KR20080014063A (en) 2008-02-13
CN101208672B (en) 2010-05-19
EP1894112B1 (en) 2010-04-14
WO2007002445A2 (en) 2007-01-04
CN101208672A (en) 2008-06-25
JP2008544411A (en) 2008-12-04
US7587521B2 (en) 2009-09-08
TWI328169B (en) 2010-08-01

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