WO2007009042A1 - Laser lift-off led with improved light extraction - Google Patents
Laser lift-off led with improved light extraction Download PDFInfo
- Publication number
- WO2007009042A1 WO2007009042A1 PCT/US2006/027205 US2006027205W WO2007009042A1 WO 2007009042 A1 WO2007009042 A1 WO 2007009042A1 US 2006027205 W US2006027205 W US 2006027205W WO 2007009042 A1 WO2007009042 A1 WO 2007009042A1
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- WIPO (PCT)
- Prior art keywords
- stack
- semiconductor layers
- set forth
- principal surface
- dielectric layer
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0091—Scattering means in or on the semiconductor body or semiconductor body package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
Definitions
- the following relates to the lighting arts. It especially relates to light emitting devices including group ffl-nitride based light emitting diodes (LEDs) transferred from a deposition substrate to a host substrate or sub-mount using a laser lift-off process, and to methods for fabricating same, and will be described with particular reference thereto. However, the following will also find application in conjunction with other light emitting semiconductor devices that include semiconductor layers transferred from a deposition substrate to a host substrate or sub-mount.
- LEDs group ffl-nitride based light emitting diodes
- Group Ill-nitride based LEDs are used for generating green, blue, violet, and ultraviolet light emission. These LEDs include a stack of layers typically including layers of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and ternary or quaternary alloys thereof, which define a pn diode. By coupling such an LED with suitable phosphors, a white LED can be fabricated.
- GaN gallium nitride
- AlN aluminum nitride
- InN indium nitride
- ternary or quaternary alloys thereof which define a pn diode.
- the LED die can be coated with a phosphor-containing encapsulant, an array of group ⁇ i-nitride based LEDs can be arranged to irradiate a phosphor-containing or phosphor-coated optic, or so forth.
- the deposition substrate for epitaxially growing the group Ill-nitride layers should substantially comport with the lattice constant, growth temperature, and chemistry of the epitaxially deposited group Ill-nitride layers.
- the ideal substrate is a group Ill-nitride substrate such as a GaN substrate; however, difficulties have been encountered in generating large-area group Ill-nitride wafers.
- Most group Ill-nitride LEDs are presently grown on deposition substrates made of sapphire (Al 2 O 3 ) or silicon carbide (SiC).
- Sapphire and SiC have characteristics that may not be advantageous in the finished device, such as being electrically insulating, exhibiting limited thermal conductivity, or so forth. Accordingly, there is interest in transferring the epitaxially grown group El-nitride pn diode stack from the deposition substrate to a more advantageous host substrate or sub-mount, which provides structural support (and optionally also electrical connectivity) for the final fabricated LED device.
- Suitable host substrates or sub-mounts can include, for example, silicon or gallium arsenide (GaAs) substrates or sub-mounts, a dielectric-coated metal substrate or sub-mount, or so forth.
- GaAs gallium arsenide
- the surface of the epitaxially grown group Ill-nitride stack is attached to the host substrate or sub-mount and detached from the sapphire, SiC, or other deposition substrate.
- One approach for detaching the stack of group Ill-nitride semiconductor layers is application of a laser lift-off process.
- Laser lift-off detachment processes employ a laser whose energy is absorbed near the interface between the group Ill-nitride stack and the deposition substrate.
- some excimer lasers produce laser beams that are highly transparent in sapphire but strongly absorbed by GaN.
- the excimer laser impinges upon the sapphire substrate. Because the sapphire is transparent to the laser beam, it passes through the sapphire substrate substantially without attenuation, and is absorbed at the GaN/sapphire interface, causing detachment of the sapphire substrate.
- laser lift-off provides a host substrate or sub-mount having advantageous characteristics
- light extraction from the detached stack of group m-nitride layers is degraded by the lift-off.
- the lifted-off stack of group m-nitride layers is thin (typical thicknesses for the stack are around a few microns to around a few tens of microns) with substantially larger lateral dimensions (typically hundreds of microns to a centimeter or larger).
- the new surface created by the laser lift-off is smooth.
- the refractive index of group M-nitride materials is high. The high aspect ratio dimensions, smooth surface, and high refractive index cooperate to cause substantial total internal reflection and waveguiding of light generated in the lifted-off stack of group m-nitride layers, which substantially reduces light extraction.
- a light emitting device including a stack of semiconductor layers defining a light emitting pn junction and a dielectric layer disposed over the stack of semiconductor layers.
- the dielectric layer has a refractive index substantially matching a refractive index of the stack of semiconductor layers.
- the dielectric layer has a principal surface distal from the stack of semiconductor layers. The distal principal surface includes patterning, roughening, or texturing configured to promote extraction of light generated in the stack of semiconductor layers.
- a method for fabricating a light emitting device.
- a stack of semiconductor layers is formed defining a light emitting pn junction.
- a dielectric layer is disposed over the stack of semiconductor layers.
- the dielectric layer has a refractive index substantially matching a refractive index of the stack of semiconductor layers.
- the dielectric layer has a principal surface distal from the stack of semiconductor layers. The distal principal surface includes patterning, roughening, or texturing configured to promote extraction of light generated in the stack of semiconductor layers.
- a light emitting device including a stack of semiconductor layers defining a light emitting pn junction and a host substrate or sub-mount on which is disposed the stack of semiconductor layers.
- the host substrate or sub-mount is different from a deposition substrate on which the stack of semiconductor layers was formed.
- Patterning, roughening, or texturing configured to promote extraction of light generated in the stack of semiconductor layers is formed on a distal principal surface of the stack of semiconductor layers that is distal from the host substrate or sub-mount.
- a method for fabricating a light emitting device.
- a stack of semiconductor layers defining a light emitting pn junction is formed on a deposition substrate.
- the formed stack of semiconductor layers is transferred from the deposition substrate to a host substrate or sub-mount.
- the transferring exposes a new principal surface of the stack of semiconductor layers that was not exposed when the stack of semiconductor layers was formed on the deposition substrate.
- Patterning, roughening, or texturing configured to promote extraction of light generated in the stack of semiconductor layers is generated on the new principal surface of the stack of semiconductor layers.
- FIGURES 1A-1D diagrammatically show a suitable group Ill-nitride LED fabrication process including laser lift-off processing.
- FIGURE IA diagrammatically shows a stack of semiconductor layers deposited on a deposition substrate.
- FIGURE IB diagrammatically shows the stack of semiconductor layers attached to a host substrate or sub-mount during laser lift-off of the deposition substrate.
- FIGURE 1C diagrammatically shows the stack of semiconductor layers attached to the host substrate or sub-mount after detachment of the deposition substrate.
- FIGURE ID diagrammatically shows the fabricated light emitting device, including a dielectric layer disposed over the stack of semiconductor layers having a distal principal surface including patterning, roughening, or texturing configured to promote extraction of light generated in the stack of semiconductor layers.
- FIGURE 2 diagrammatically shows another embodiment of the fabricated light emitting device, in which the dielectric layer includes openings extending through to expose portions of the stack of semiconductor layers, the openings defining the patterning, roughening, or texturing of the distal principal surface.
- an LED is fabricated as follows.
- a stack of group EH-nitride semiconductor layers 10 defini ⁇ g a light-emitting pn junction is deposited on a deposition substrate 12.
- the stack of group IH-nitride semiconductor layers 10 defining a light-emitting pn junction include semiconductor layers selected from a group consisting of: a gallium nitride (GaN) layer, an aluminum nitride (AlN) layer, an indium nitride (InN) layer, layers comprising ternary alloys of GaN, AlN, or InN, and layers comprising quaternary alloys of GaN, AlN, and InN.
- the stack of group m-nitride layers can include group Ill-phosphide layers, group IH-arsenide layers, group IV semiconductor layers, or so forth.
- the pn junction can be an interface, or can include layers defining an active region.
- ⁇ aepn junction can include a multi-quantum well region including a plurality of layers containing InN or alloys thereof.
- the depositing can be done using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or so forth.
- the deposition substrate 12 is sapphire or SiC, which are advantageously closely lattice-matched to GaN.
- deposition substrates can be used.
- the deposition substrate should be closely lattice-matched to the stack of group m-nitride semiconductor layers. However, some lattice mismatch therebetween can be tolerated.
- techniques such as graded epitaxial semiconductor buffers or use of thin, compliant deposition substrates can be employed to accommodate lattice mismatch between the deposited stack and the deposition substrate.
- FIGURE IA shows the stack of group m-nitride semiconductor layers 10 formed on the deposition substrate 12.
- the formed stack of group m-nitride semiconductor layers 10 includes a first principal surface 14 by which the stack 10 is secured to the deposition substrate 12 during deposition, and a second principal surface 16 which is distal from the deposition substrate 12.
- the second principal surface 16 of the stack of group Ill-nitride semiconductor layers 10 is attached to a host substrate or sub-mount 20, such as a silicon sub-mount.
- the illustrated host substrate or sub-mount 20 includes bonding bumps 22 electrically connecting with the stack of semiconductor layers 10 to enable electrical energizing of the light-emitting pn junction.
- the bonding bumps 22 electrically contact metallic or other highly conductive electrode layers (not shown) which were deposited on the second principal surface 16 of the stack of semiconductor layers 10 prior to the attachment.
- the illustrated host substrate or sub-mount 20 further includes conductive vias 24 electrically connected with the bonding bumps 22 by front-side conductive traces 26 so as to provide back-side electrical contact for the device.
- an underfill material 28 is disposed between the attached stack of semiconductor layers 10 and the host substrate or sub-mount 20 in-between the bonding bumps 22.
- the underfill material can provide benefits such as improved attachment, thermal conduction from the stack of semiconductor layers 10 to the host substrate or sub-mount 20, or so forth.
- the underfill material 28 should be electrically insulating, and can be either thermally insulating, or thermally conductive to promote heat transfer from the stack of semiconductor layers 10 to the host substrate or sub-mount 20.
- the stack of group IE-nitride semiconductor layers 10 is detached from the deposition substrate 12.
- laser lift-off is used to effectuate this detachment.
- a laser beam 30 (diagrammatically indicated by block arrows in FIGURE IB) is applied to the deposition substrate 12.
- laser While the conventional term "laser” is used herein in referencing the laser lift-off process, it is intended that the term “laser” as used herein encompasses both a conventional laser light source such as an excimer laser, or a focused high-intensity arc lamp light source, a focused high-intensity incandescent light source, or other high-intensity light source.
- the wavelength or photon energy of the laser beam 30 is selected to be substantially transparent for the deposition substrate 12 such that the laser beam 30 passes through the deposition substrate 12 substantially unattenuated.
- the wavelength or photon energy of the laser beam 30 is further selected to be strongly absorbed by one or more materials of the stack of group ⁇ i-nitride semiconductor layers 10, so that the laser beam 30 is absorbed proximate to the first principal surface 14 of the stack of semiconductor layers 10 to cause detachment of the deposition substrate 12 from the stack of semiconductor layers 10.
- FIGURE IB diagrammatically illustrates the application of the laser beam 30 during the laser lift-off process.
- FIGURE 1C diagrammatically illustrates the light emitting device after the laser lift-off.
- the second principal surface 16 of the stack of semiconductor layers 10 is attached to the host substrate or sub-mount 20, while the first principal surface 14 is exposed by the detachment of the deposition substrate 12.
- the exposed first principal surface 14 is relatively smooth.
- the exposed first principal surface 14 has an RMS roughness of a few nanometers to a few microns. This relatively smooth exposed first principal surface 14 promotes total internal reflection of light generated in the stack of semiconductor layers 10 at the first principal surface 14, and promotes waveguiding that traps light within the stack of semiconductor layers 10. These effects degrade the light extraction efficiency.
- a dielectric layer 40 is disposed over the stack of semiconductor layers 10.
- the dielectric layer 40 is substantially transparent to light emitted by the stack of semiconductor layers 10, and has a refractive index that substantially matches a refractive index of the stack of semiconductor layers 10.
- the dielectric layer 40 includes a proximate principal surface 42 that is in contact with the stack of semiconductor layers 10, and a distal principal surface 44 distal from the stack of semiconductor layers 10.
- the distal principal surface 44 includes patterning, roughening, or texturing 50 configured to promote extraction of light generated in the stack of semiconductor layers.
- the patterning, roughening, or texturing 50 extends only partway through the dielectric layer 40. Accordingly, the proximate principal surface 42 does not include the patterning, roughening, or texturing 50 of the distal principal surface 44. Rather, the proximate principal surface 42 is continuous and covers the first principal surface 14 of the stack of semiconductor layers 10.
- a dielectric layer 40' is disposed over the stack of semiconductor layers 10.
- the dielectric layer 40' is substantially transparent to light emitted by the stack of semiconductor layers 10, and has a refractive index that substantially matches a refractive index of the stack of semiconductor layers 10.
- the dielectric layer 40' includes a proximate principal surface 42' that is in contact with the stack of semiconductor la ⁇ ? ers 10, and a distal principal surface 44' distal from the stack of semiconductor layers 10.
- the distal principal surface 44' includes patterning, roughening, or texturing 50' configured to promote extraction of light generated in the stack of semiconductor layers.
- FIGURE 2 differ from those of FIGURE ID in that the patterning, roughening, or texturing 50' extends through to the proximate principal surface 42' so that the proximate principal surface 42' includes the patterning, roughening, or texturing 50'.
- the patterning, roughening, or texturing 50' of the distal principal surface 44' is defined by the incomplete coverage of the stack of semiconductor layers by the dielectric layer 40'. The openings in the incomplete coverage define the patterning, roughening, or texturing 50' of the distal principal surface.
- the patterning, roughening, or texturing 50, 50' is substantially random and non-periodic. In other embodiments, the patterning, roughening, or texturing 50, 50' defines microlenses. In yet other embodiments, the patterning, roughening, or texturing 50, 50' has slanted surfaces or other structure that biases extracted light toward a selected viewing angle. The patterning, roughening, or texturing 50, 50' reduces the planarity of the distal principal surface 44, 44' to enhance light extraction by reducing total internal reflection and waveguiding effects. The patterning, roughening, or texturing 50, 50' includes feature sizes that enhance light extraction based on the wavelength of light emitted by the stack of semiconductor layers 10 defining the light emitting pn junction.
- the dielectric layer 40, 40' can be substantially any transparent dielectric material with a refractive index comparable with that of the semiconductor material.
- One suitable dielectric material is silicon nitride (SiN x ).
- the refractive index of SiN x depends upon the stoichiometry, and tends to increase with increasing Si/N ratio.
- the inventors have deposited SiNx by plasma-enhanced chemical vapor deposition (PECVD), and have measured a refractive index of greater than 2.4 at 680 nm. This refractive index is sufficiently high to substantially match the refractive index of GaN at 680 nm, which has been reported to be about 2.3. See Zauner et al., MRS Internet J. Nitride Semicond. Res. 3, 17 (1998), pp. 1-4.
- Other suitable dielectric materials include, for example, silicon oxides (SiO x ) and silicon oxynitrides (Si x Ny),
- the refractive index of the dielectric layer 40, 40' should substantially match the refractive index of the stack of semiconductor layers 10 so as to reduce reflections as light passes from the semiconductor material into the dielectric material.
- any dielectric material having a refractive index about the same as, or greater than, the refractive index of the semiconductor material is considered to substantially match the refractive index of the semiconductor material. That is, the condition for the refractive index of the dielectric layer 40, 40' to substantially match the refractive index of the stack of semiconductor layers 10 is either or n d >n s .
- the dielectric layer 40, 40' including the distal principal surface 44, 44' having the patterning, roughening, or texturing 50, 50' can be produced in various ways, hi one approach, the dielectric layer is deposited substantially uniformly across the first principal surface 14 of the stack of semiconductor layers 10. An etch down process, such as a plasma etch, is then applied using a mask to form the patterning, roughening, or texturing 50, 50'.
- the mask can be a non-contact mask suitable for patterning devices after attachment to the host substrate or sub-mount 20.
- a non-contact mask suitable for photolithography, x-ray lithography, or e-beam lithography can be used.
- the mask can be used to form a resist pattern (such as a photoresist pattern) on the deposited dielectric layer; the resist pattern serves to define the etched and unetched regions.
- the mask can be used as a shadow mask in a directional dry etching process.
- Another approach is to deposit small polystyrene members, such as polystyrene spheres, on the surface of the deposited dielectric layer, and using those members or spheres as a plasma etch mask.
- This approach typically provides a random or non-periodic patterning, roughening, or texturing.
- Yet another approach for generating the patterning, roughening, or texturing 50 is to use grating lithography. This approach typically provides a periodic roughening.
- etch-down approaches can produce either the patterning, roughening, or texturing 50 which does not pass entirely through the dielectric layer 40, or the patterning, roughening, or texturing 50' which does pass entirely through the dielectric layer 40' so as to define openings in the dielectric layer 40'. The difference is merely in how deep the etch-down process penetrates. If etch-down processing is used to produce the dielectric layer 40' including openings, then an etching is preferably selected that does not attack the semiconductor material making up the stack of semiconductor layers 10.
- a lift-off process can also be used to define the patterning, roughening, or texturing SO.
- the mask is used first to define a resist pattern (such as a photoresist pattern) on the first principal surface 14 of the stack of semiconductor layers 10.
- the dielectric layer with index of refraction matched to the semiconductor material is then deposited on top of the first principal surface 14 and me resist pattern, followed by a liftoff process that removes the resist pattern along with those portions of the deposited dielectric layer disposed on the resist.
- the lift-off process can be readily performed in a manner which does not damage the stack of semiconductor layers 10, so as to produce the dielectric layer 40' including openings.
- the resist pattern can be a photoresist pattern produced by light exposure that does not damage the semiconductor material.
- a continuous layer of dielectric material can be first deposited, followed by masked resist pattern definition on top of the continuous dielectric layer, followed by a second dielectric layer deposition and lift-off of the selected portions of the second dielectric layer.
- the mask is used first to define the resist pattern, and then an etch-down process is used to form pattern directly on the semiconductor material.
- this approach has • the disadvantage that the etching of .the semiconductor material can damage the stack of semiconductor layers 10, leading to degraded LED performance.
- Patterns with desired shapes may be created after patterning.
- the shapes of the dielectric (or semiconductor) islands and the island array may effectively form microlenses to optimize optical output power.
- selected island shapes and pattern sidewall angles can be formed to engineer viewing angles.
- the distal principal surface 44, 44' is coated with an anti-reflection coating after patterning to further enhance light extraction efficiency.
- An anti-reflection coating is particularly useful when the semiconductor refractive index n s is high and the dielectric material accordingly has a high refractive index r ⁇ substantially matching the high refractive index n s of the stack of semiconductor layers.
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2006800254726A CN101438422B (en) | 2005-07-11 | 2006-07-11 | Laser lift-off led with improved light extraction |
DE112006001835T DE112006001835T5 (en) | 2005-07-11 | 2006-07-11 | Laser-raised LED with improved light output |
EP06787150A EP1905104A1 (en) | 2005-07-11 | 2006-07-11 | Laser lift-off led with improved light extraction |
JP2008521608A JP2009500872A (en) | 2005-07-11 | 2006-07-11 | Laser lift-off LED with improved light extraction |
US12/304,533 US20100181584A1 (en) | 2005-07-11 | 2006-07-11 | Laser lift-off with improved light extraction |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US69803205P | 2005-07-11 | 2005-07-11 | |
US60/698,032 | 2005-07-11 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2007009042A1 true WO2007009042A1 (en) | 2007-01-18 |
Family
ID=37327668
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2006/027205 WO2007009042A1 (en) | 2005-07-11 | 2006-07-11 | Laser lift-off led with improved light extraction |
Country Status (7)
Country | Link |
---|---|
US (1) | US20100181584A1 (en) |
EP (1) | EP1905104A1 (en) |
JP (1) | JP2009500872A (en) |
KR (1) | KR20090016438A (en) |
CN (1) | CN101438422B (en) |
DE (1) | DE112006001835T5 (en) |
WO (1) | WO2007009042A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009007886A1 (en) * | 2007-07-09 | 2009-01-15 | Koninklijke Philips Electronics N.V. | Substrate removal during led formation |
EP1855327A3 (en) * | 2006-05-08 | 2009-08-05 | Lg Electronics Inc. | Semiconductor light emitting device and method for manufacturing the same |
WO2009115968A1 (en) * | 2008-03-17 | 2009-09-24 | Koninklijke Philips Electronics N.V. | Underfill process for flip-chip leds |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9293653B2 (en) * | 2010-10-08 | 2016-03-22 | Guardian Industries Corp. | Light source with light scattering features, device including light source with light scattering features, and/or methods of making the same |
CN112042272A (en) * | 2018-05-09 | 2020-12-04 | 堺显示器制品株式会社 | Method and apparatus for manufacturing flexible light emitting device |
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2006
- 2006-07-11 CN CN2006800254726A patent/CN101438422B/en not_active Expired - Fee Related
- 2006-07-11 US US12/304,533 patent/US20100181584A1/en not_active Abandoned
- 2006-07-11 DE DE112006001835T patent/DE112006001835T5/en not_active Withdrawn
- 2006-07-11 WO PCT/US2006/027205 patent/WO2007009042A1/en active Application Filing
- 2006-07-11 JP JP2008521608A patent/JP2009500872A/en active Pending
- 2006-07-11 EP EP06787150A patent/EP1905104A1/en not_active Withdrawn
- 2006-07-11 KR KR1020087002606A patent/KR20090016438A/en active Search and Examination
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US20040012958A1 (en) * | 2001-04-23 | 2004-01-22 | Takuma Hashimoto | Light emitting device comprising led chip |
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EP1855327A3 (en) * | 2006-05-08 | 2009-08-05 | Lg Electronics Inc. | Semiconductor light emitting device and method for manufacturing the same |
US7893451B2 (en) | 2006-05-08 | 2011-02-22 | Lg Innotek Co., Ltd. | Light emitting device having light extraction structure and method for manufacturing the same |
US7939840B2 (en) | 2006-05-08 | 2011-05-10 | Lg Innotek Co., Ltd. | Light emitting device having light extraction structure and method for manufacturing the same |
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US8008103B2 (en) | 2006-05-08 | 2011-08-30 | Lg Innotek Co., Ltd. | Light emitting device having light extraction structure and method for manufacturing the same |
US8648376B2 (en) | 2006-05-08 | 2014-02-11 | Lg Electronics Inc. | Light emitting device having light extraction structure and method for manufacturing the same |
US9246054B2 (en) | 2006-05-08 | 2016-01-26 | Lg Innotek Co., Ltd. | Light emitting device having light extraction structure and method for manufacturing the same |
US9837578B2 (en) | 2006-05-08 | 2017-12-05 | Lg Innotek Co., Ltd. | Light emitting device having light extraction structure and method for manufacturing the same |
WO2009007886A1 (en) * | 2007-07-09 | 2009-01-15 | Koninklijke Philips Electronics N.V. | Substrate removal during led formation |
US7867793B2 (en) | 2007-07-09 | 2011-01-11 | Koninklijke Philips Electronics N.V. | Substrate removal during LED formation |
WO2009115968A1 (en) * | 2008-03-17 | 2009-09-24 | Koninklijke Philips Electronics N.V. | Underfill process for flip-chip leds |
US8273587B2 (en) | 2008-03-17 | 2012-09-25 | Lumileds Lighting Company Llc | Underfill process for flip-chip LEDs |
Also Published As
Publication number | Publication date |
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DE112006001835T5 (en) | 2008-05-15 |
CN101438422B (en) | 2011-04-20 |
JP2009500872A (en) | 2009-01-08 |
US20100181584A1 (en) | 2010-07-22 |
EP1905104A1 (en) | 2008-04-02 |
CN101438422A (en) | 2009-05-20 |
KR20090016438A (en) | 2009-02-13 |
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