WO2007019455A3 - Copper barrier reflow process employing high speed optical annealing - Google Patents

Copper barrier reflow process employing high speed optical annealing Download PDF

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Publication number
WO2007019455A3
WO2007019455A3 PCT/US2006/030746 US2006030746W WO2007019455A3 WO 2007019455 A3 WO2007019455 A3 WO 2007019455A3 US 2006030746 W US2006030746 W US 2006030746W WO 2007019455 A3 WO2007019455 A3 WO 2007019455A3
Authority
WO
WIPO (PCT)
Prior art keywords
barrier layer
metal
high speed
light
thin film
Prior art date
Application number
PCT/US2006/030746
Other languages
French (fr)
Other versions
WO2007019455A2 (en
Inventor
Kartik Ramaswamy
Hiroji Hanawa
Biagio Gallo
Kenneth S Collins
Kai Ma
Vijay Parihar
Dean Jennings
Abhilash J Mayur
Amir Al-Bayati
Andrew Nguyen
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of WO2007019455A2 publication Critical patent/WO2007019455A2/en
Publication of WO2007019455A3 publication Critical patent/WO2007019455A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating

Abstract

A method of forming a barrier layer for a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on the surfaces of the high aspect ratio openings including the vertical side walls and depositing a metal barrier layer comprising the barrier metal on the first barrier layer. The method further includes reflowing the metal barrier layer by (a) directing light from an array of continuous wave lasers into a line of light extending at least partially across the thin film structure, and (b) translating the Line of light relative to the thin film structure in a direction transverse to the line of light.
PCT/US2006/030746 2005-08-08 2006-08-07 Copper barrier reflow process employing high speed optical annealing WO2007019455A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/199,570 2005-08-08
US11/199,570 US7312148B2 (en) 2005-08-08 2005-08-08 Copper barrier reflow process employing high speed optical annealing

Publications (2)

Publication Number Publication Date
WO2007019455A2 WO2007019455A2 (en) 2007-02-15
WO2007019455A3 true WO2007019455A3 (en) 2007-06-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/030746 WO2007019455A2 (en) 2005-08-08 2006-08-07 Copper barrier reflow process employing high speed optical annealing

Country Status (3)

Country Link
US (1) US7312148B2 (en)
TW (1) TW200710975A (en)
WO (1) WO2007019455A2 (en)

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