WO2007028026B1 - Flash drive fast wear leveling - Google Patents

Flash drive fast wear leveling

Info

Publication number
WO2007028026B1
WO2007028026B1 PCT/US2006/034243 US2006034243W WO2007028026B1 WO 2007028026 B1 WO2007028026 B1 WO 2007028026B1 US 2006034243 W US2006034243 W US 2006034243W WO 2007028026 B1 WO2007028026 B1 WO 2007028026B1
Authority
WO
WIPO (PCT)
Prior art keywords
memory blocks
pointers
memory
wear
leveling table
Prior art date
Application number
PCT/US2006/034243
Other languages
French (fr)
Other versions
WO2007028026A2 (en
WO2007028026A3 (en
Inventor
Steve Kolokowsky
Original Assignee
Cypress Semiconductor Corp
Steve Kolokowsky
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cypress Semiconductor Corp, Steve Kolokowsky filed Critical Cypress Semiconductor Corp
Priority to JP2008529311A priority Critical patent/JP2009507302A/en
Priority to KR1020087007800A priority patent/KR101383853B1/en
Publication of WO2007028026A2 publication Critical patent/WO2007028026A2/en
Publication of WO2007028026A3 publication Critical patent/WO2007028026A3/en
Publication of WO2007028026B1 publication Critical patent/WO2007028026B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G06F2212/1036—Life time enhancement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7211—Wear leveling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A system and method comprising a non- volatile memory including one or more memory blocks to store data, a controller to allocate one or more of the memor blocks to store data, and a wear-leveling table populated with pointers to unallocated memory blocks in the non-volatile memory, the controller to identify one or more pointers in the wear-leveling table and to allocate the unallocated memory blocks associated with the identified pointers for the storage of data.

Claims

AMENDED CLAIMS [Received by the International Bureau on 07 January 2008 (07.01.08)]
1. A system comprising; a controller to allocate one or more of the memory blocks in a non-volatile memory to store data; a logical-to-physical table populated with pointers to the memory blocks in the nonvolatile memory, the controller to initially allocate the memory blocks to store data according to the pointers in the logical-to-physical table; and a wear-leveling table to store pointers to unallocated memory blocks in the non-volatile memory, the unallocated memory blocks previously allocated to store data by the controller according to the pointers in the logical-to-physical table, the controller to identify one or more pointers in the wear-leveling table and to store data to the memory blocks associated with the identified pointers.
2. The system of claim 1 where the controller is configured to erase data stored in one or more of the memory blocks and to populate the wear-leveling table with pointers to the erased memory blocks,
3. The system of claim 2 where the controller is configured to prioritize the pointers in the wear- leveling table according to when the memory blocks associated with the pointers were erased
4. The system of claim 3 where the controller is configured to linearly search the wear-leveling table for pointers to unallocated memory blocks that are available to store data.
5. The system of claim 1 where the controller is configured to identify erased memory blocks and faulty memory blocks in the non- volatile memory, to compare a number of identified erased memory blocks and faulty memory blocks to a threshold, and to populate the wear-leveling table responsive to the comparing or initializing the non-volatile memory with pointers to the memory blocks responsive to the comparing.
6. The system of claim 1 where the controller initializes the logical-to-physical table with the pointers concurrently to populating the wear-leveling table with pointers to the unallocated memory blocks.
7. The system of claim 6 where the controller is configured to allocate the memory blocks associated with the pointers in the logical-to-physical table prior to the controller accessing the wear-leveling table for pointers to the unallocated memory blocks.
8. The system of claim 1 where the wear-leveling table does not store pointers to the allocated memory blocks; and where the unallocated memory blocks were previously erased by the controller.
9. The system of claim 1 where the unallocated memory blocks include one or more memory blocks available to store data and one or more faulty memory blocks not to store data.
10. The system of claim 9 where the wear-leveling table is configured to indicate to the controller which of the pointers are associated with the faulty memory blocks.
11. The system of claim 1 where the non-volatile memory includes multiple memory zones, each memory zone including a plurality of memory blocks and having a different wear-leveling table, the controller to receive a write command identifying a memory zone to store data, to determine the wear-leveling table does not correspond to the identified memory zone, and to re- populate the wear-leveling table with pointers to memory blocks corresponding to the identified memory zone.
12. A method comprising: populating a wear-leveling table with pointers to one or more memory blocks it) a flash memory, where the pointers are associated with erased memory blocks or memory blocks that are faulty, identifying at least one pointer in the wear-leveling table associated with an erased memory block;
18 storing data to the memory block associated with the identified pointer; identifying erased memory blocks and faulty memory blocks in the flash memory; comparing a number of identified erased memory blocks and faulty memory blocks to a threshold; and populating the wear-leveling table responsive to the comparing or initializing the flash memory with pointers to the memory blocks responsive to the comparing.
13. The method of claim 12 includes erasing data stored in one or more of the memory blocks responsive to the identifying at least one pointer in the wear-leveling table and prior to storing data to the memory block associated with the identified pointer.
14. The method of claim 12 includes prioritizing the pointers in the wear-leveling table according to when the memory blocks associated with the pointers were erased.
15. The method of claim 14 includes accessing the wear-leveling table for pointers according to the prioritizing.
16. The method of claim 12 includes prioritizing the pointers in the wear-leveling table according to the number of write operations performed on the memory blocks associated with the pointers.
17. The method of claim 12 includes initializing a logical-to-physical table with pointers to the memory blocks in the flash memory concurrently to populating the wear-leveling table with pointers associated with the erased memory blocks.
18. The method of claim 17 includes allocating the memory blocks associated with the pointers in the logical-to-physical table prior to accessing the wear-leveling table for pointers to erased memory blocks.
19. A method comprising: populating a wear-leveling table with pointers to one or more memory blocks in a flash
19 memory, where the pointers are associated with erased memory blocks or memory blocks that are faulty; receiving a write command identifying a zone of the flash memory to store data; determining the wear-leveling table does not correspond to the identified zone; re-populating the wear-leveling table with pointers to memory blocks corresponding to the identified zone; identifying at least one pointer in the re-populated wear-leveling table associated with an erased memory block; and storing data to the memory block associated with the identified pointer.
20. The method of claim 19 identifying erased memory blocks and faulty memory blocks in the flash memory; comparing a number of identified erased memory blocks and faulty memory blocks to a threshold; and populating the wear-leveling table responsive to the comparing.
21. The method of claim 19 identifying erased memory blocks and faulty memory blocks in the flash memory; comparing a number of identified erased memory blocks and faulty memory blocks to a threshold; and initializing the flash memory with pointers to the memory blocks responsive to the comparing.
20
PCT/US2006/034243 2005-09-01 2006-08-31 Flash drive fast wear leveling WO2007028026A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2008529311A JP2009507302A (en) 2005-09-01 2006-08-31 High-speed wear leveling of flash drives
KR1020087007800A KR101383853B1 (en) 2005-09-01 2006-08-31 Flash drive fast wear leveling

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US71391305P 2005-09-01 2005-09-01
US60/713,913 2005-09-01
US11/468,569 US7853749B2 (en) 2005-09-01 2006-08-30 Flash drive fast wear leveling
US11/468,569 2006-08-30

Publications (3)

Publication Number Publication Date
WO2007028026A2 WO2007028026A2 (en) 2007-03-08
WO2007028026A3 WO2007028026A3 (en) 2007-12-27
WO2007028026B1 true WO2007028026B1 (en) 2008-03-06

Family

ID=37805689

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/034243 WO2007028026A2 (en) 2005-09-01 2006-08-31 Flash drive fast wear leveling

Country Status (4)

Country Link
US (2) US7853749B2 (en)
JP (1) JP2009507302A (en)
KR (1) KR101383853B1 (en)
WO (1) WO2007028026A2 (en)

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JP2009507302A (en) 2009-02-19
KR101383853B1 (en) 2014-04-17
WO2007028026A2 (en) 2007-03-08
US7853749B2 (en) 2010-12-14
US20070050536A1 (en) 2007-03-01
US8417881B1 (en) 2013-04-09
KR20080082601A (en) 2008-09-11
WO2007028026A3 (en) 2007-12-27

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