WO2007041505A3 - Programmable i/o cell capable of holding its state in power-down mode - Google Patents

Programmable i/o cell capable of holding its state in power-down mode Download PDF

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Publication number
WO2007041505A3
WO2007041505A3 PCT/US2006/038455 US2006038455W WO2007041505A3 WO 2007041505 A3 WO2007041505 A3 WO 2007041505A3 US 2006038455 W US2006038455 W US 2006038455W WO 2007041505 A3 WO2007041505 A3 WO 2007041505A3
Authority
WO
WIPO (PCT)
Prior art keywords
signal
responsive
state
input
power
Prior art date
Application number
PCT/US2006/038455
Other languages
French (fr)
Other versions
WO2007041505A2 (en
Inventor
Biranchinath Sahu
Douglas F Pastorello
Golam R Chowdhury
Original Assignee
Biranchinath Sahu
Douglas F Pastorello
Golam R Chowdhury
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Biranchinath Sahu, Douglas F Pastorello, Golam R Chowdhury filed Critical Biranchinath Sahu
Publication of WO2007041505A2 publication Critical patent/WO2007041505A2/en
Publication of WO2007041505A3 publication Critical patent/WO2007041505A3/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356147—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption

Abstract

The present invention comprises a microcontroller unit including a processor for generating a power down signal. Control logic generates a hold signal responsive to the power down signal. A voltage regulator (204) provides a regulated voltage responsive to an input voltage and powers down responsive to the power down signal. At least one digital device powered by the regulated voltage enters a powered down mode responsive to the voltage regulator entering the powered down state. The at least one digital device provides at least one digital output signal that is provided to an input/output cell (210). The input/output cell also is connected to receive a hold signal. The input/output cell maintains a last state of the digital output signal responsive to the hold signal when the at least one digital device enters the powered down state.
PCT/US2006/038455 2005-09-30 2006-09-29 Programmable i/o cell capable of holding its state in power-down mode WO2007041505A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/241,277 US7373533B2 (en) 2005-09-30 2005-09-30 Programmable I/O cell capable of holding its state in power-down mode
US11/241,277 2005-09-30

Publications (2)

Publication Number Publication Date
WO2007041505A2 WO2007041505A2 (en) 2007-04-12
WO2007041505A3 true WO2007041505A3 (en) 2007-08-23

Family

ID=37903254

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/038455 WO2007041505A2 (en) 2005-09-30 2006-09-29 Programmable i/o cell capable of holding its state in power-down mode

Country Status (3)

Country Link
US (2) US7373533B2 (en)
CN (1) CN100592243C (en)
WO (1) WO2007041505A2 (en)

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US7170315B2 (en) * 2003-07-31 2007-01-30 Actel Corporation Programmable system on a chip
US7441131B2 (en) * 2005-09-30 2008-10-21 Silicon Laboratories Inc. MCU with power saving mode
JP4772480B2 (en) * 2005-11-30 2011-09-14 株式会社東芝 Semiconductor integrated device
DE102006005779B3 (en) * 2006-02-03 2007-08-30 Atmel Germany Gmbh Integrated circuit and operating method for this
JP4705880B2 (en) * 2006-05-09 2011-06-22 Ｏｋｉセミコンダクタ株式会社 Semiconductor integrated circuit and its test method
US8392728B2 (en) * 2006-12-22 2013-03-05 Intel Corporation Reducing idle leakage power in an IC
DE102007030569B4 (en) * 2007-07-02 2012-11-08 Austriamicrosystems Ag Circuit arrangement and method for evaluating a data signal
JP5106219B2 (en) 2008-03-19 2012-12-26 株式会社東芝 Memory device, host device, memory system, memory device control method, host device control method, and memory system control method
US8049475B2 (en) * 2008-03-31 2011-11-01 Silicon Laboratories Inc. 5 volt tolerant voltage regulator
TWI392212B (en) * 2008-09-17 2013-04-01 Holtek Semiconductor Inc Control circuit of single chip ic
US7782702B1 (en) * 2008-10-03 2010-08-24 Xilinx, Inc. Apparatus and method for memory cell power-up sequence
US9138172B2 (en) 2011-02-24 2015-09-22 Rochester Institute Of Technology Method for monitoring exposure to an event and device thereof
US9339224B2 (en) 2011-02-24 2016-05-17 Rochester Institute Of Technology Event dosimeter devices and methods thereof
US10292445B2 (en) 2011-02-24 2019-05-21 Rochester Institute Of Technology Event monitoring dosimetry apparatuses and methods thereof
US9772668B1 (en) * 2012-09-27 2017-09-26 Cadence Design Systems, Inc. Power shutdown with isolation logic in I/O power domain
CN104393873B (en) * 2013-03-14 2019-12-03 硅实验室公司 For improving the device and correlation technique of the signal communication in electronic circuit
US9836071B2 (en) * 2015-12-29 2017-12-05 Silicon Laboratories Inc. Apparatus for multiple-input power architecture for electronic circuitry and associated methods
US10630493B2 (en) * 2017-11-29 2020-04-21 Birad—Research & Development Company Ltd. Physical unclonable functions related to inverter trip points
US10659038B1 (en) * 2019-03-12 2020-05-19 Nxp Usa, Inc. Power on reset latch circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6753698B2 (en) * 2002-08-08 2004-06-22 International Business Machines Corporation Low power low voltage transistor—transistor logic I/O driver

Family Cites Families (4)

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Publication number Priority date Publication date Assignee Title
US6882200B2 (en) * 2001-07-23 2005-04-19 Intel Corporation Controlling signal states and leakage current during a sleep mode
JP2005521353A (en) * 2002-03-26 2005-07-14 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ Interface for digital communication
JP3746273B2 (en) * 2003-02-12 2006-02-15 株式会社東芝 Signal level conversion circuit
US20060290404A1 (en) * 2005-06-23 2006-12-28 Ati Technologies Inc. Apparatus and methods for voltage level conversion

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6753698B2 (en) * 2002-08-08 2004-06-22 International Business Machines Corporation Low power low voltage transistor—transistor logic I/O driver

Also Published As

Publication number Publication date
US20080246526A1 (en) 2008-10-09
US20070079149A1 (en) 2007-04-05
CN100592243C (en) 2010-02-24
US8041975B2 (en) 2011-10-18
CN101313267A (en) 2008-11-26
WO2007041505A2 (en) 2007-04-12
US7373533B2 (en) 2008-05-13

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