WO2007056682A2 - Low voltage nanovolatile memory cell with electrically transparent control gate - Google Patents
Low voltage nanovolatile memory cell with electrically transparent control gate Download PDFInfo
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- WO2007056682A2 WO2007056682A2 PCT/US2006/060510 US2006060510W WO2007056682A2 WO 2007056682 A2 WO2007056682 A2 WO 2007056682A2 US 2006060510 W US2006060510 W US 2006060510W WO 2007056682 A2 WO2007056682 A2 WO 2007056682A2
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- 238000003860 storage Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000002800 charge carrier Substances 0.000 claims abstract description 3
- 238000004519 manufacturing process Methods 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims 3
- 238000000206 photolithography Methods 0.000 abstract 1
- 239000007943 implant Substances 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000000969 carrier Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- DNXHEGUUPJUMQT-UHFFFAOYSA-N (+)-estrone Natural products OC1=CC=C2C3CCC(C)(C(CC4)=O)C4C3CCC2=C1 DNXHEGUUPJUMQT-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 241000282887 Suidae Species 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
An EEPROM (11 ) having a charge: storage -element, i.e., a floating gate (21), in the substrate (13) adjacent to vertically separated source (15) and drain (19) electrodes. An electrically transparent poly control gate (27) allows relatively low voltages to be used for program, erase, and read operations when a plurality of similar devides are arranged in a memory array (41).A second poly member (31), called a tunnel poly member, communicates with source and drain electrodes in synchronism with the poly control gate to provide charge carriers to the floating gate. Manufacturing involves a series of layers with minimal needs for photolithography.
Description
- I-
Description
LOW VOLTAGE NANOV0LATILE MEMORY CELL WITH
ELECTRICALLY TRANSPARENT CONTROL GATE
TECHNICAL FIELD
The invention relates to non-volatile semiconductor memory devices and, more particularly, to an EEPROM device of the type having a buried floating gate structure ,
BACKGROUND ART
Buried floating gate structures in EEPROM devices are known as an alternative to customary floating gate devices where the floating gate is an isolated poly layer separated from the substrate by funnel oxide. For example, U.S. Pat. No, 6,052,311 to Fu shows a floating gate within a substrate. Source sn< drain electrodes are located beside the floating gate and the control gate is located over the surface of the substrate above the floating gate and insulated from the floating gate, The patent teaches thac a way to reduce the time for programming and the erasing the device is to enlarge the ovex~lap betwern the floating gate and the control- gate that is, to raise the. capacitive coupiing ratio of the device. Another way to shorten programming and erasa time is to increase voltage used for these operations. Because of shrinking device sizes, increasing voltage and concomitant power consumption is not a preferred alternative. Partially buried floating gate structures are shown in ϋ,S, Pat No. 6,720,611 to Jang and U, S. Pat. No. 6,906,379 to Chen et al .
One of the interesting aspects of the device of the V311 patent is that the channel region is shifted in a position to a location, between the source and drain
other words, the floating gate occupies the space normally occupied by the channel.
An object of the invention is an EBPROM device which is programmable with low voltages but that has fast programming and. erase times .
SUMMARY OF THE INVENTION
A charge storage EEPROM transistor device is disclosed, in which the charge storage element is disposed within a substrate with a very thin, control gate layer directly above the charge storage element and the substrate, with a program layer electrode above the control gate layer electrode. The control gate layer electrode is electrically transparent to current between the charge storage element and the program layer electrode but finds use in reading charge in the charge storage element , The source and drain electrodes are also in the substrate with the charge storage element directly between these electrodes* In the read mode, one of the source and drain electrodes is held at ground potential. With no charge on. the charge storage element, the control gate electrode layer can be made to communicate with the source and drain electrodes creating measurable conduction to the source and drain. With charge on the charge storage element a field associated with the charge storage element will block conduction between the control electrode and source and drain. For programming and the erase operations, voltage on the programming layer electrode causes charged particles to be kept off of the control layer electrode by an opposing voltage but the control layer electrode is so thin that charged particles tunnel through the control electrhde toward the source and drain becoming trapped on the charge storage element with charge being attracted by the voltage on the source
and drain electrodes. This is unusual because electrons usually only tunnel through thin oxide, called "tunnel oxide" « Here, however, tunneling is through poly, as well as thin oxide on both planar sides of the poly layer. For erasing, a reverse procedure is used with voltage on the source and drain electrodes expelling charge from the charge storage element, which is drawn to the programming layer through the control gate layer. For both programming and the erase operations, the control gate layer draws little or no current.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a perspective plan view of an EEPROM memory device in accord with the present invention, Fig. 2 is an electrical plan of a memory array employing the memory devices of Fig. 1,
Fig, 3 is an. electrical plan illustrating the programming mode of operation of the device of Fig. l.
Fig- 4 is an electrical plan illustrating the erase mode of operation of the device of Fig. l.
Fig. 5 is. an electrical plan illustrating the read mode of operation of the device of Fig. 1.
Figs. 6-12 are side sectional views illustrating principal manufacturing steps for the device of Fig. 1.
DETAILED DESCRIPTION OF THE INVENTION
With reference to Fig. 1, a nonvolatile EEPROM memory device 11 has a substrate 13 with several constituent layers. Base layer 14 is typically of P-type seraiconductor material, usually in a silicon wafer and has the thickness of the bulk material. An epitaxially grown N+ layer 15 over the base layer 14 forms a source layer. The conductivity of this layer is adequate
for the layer to act as an electrode. Above the source layer 15 is an epitaxially grown well layer 17,
Within the well layer 17 and extending into source layer 15, a trench 20 is formed and filled with S polysilicon, resembling a poly plug. The poly plug serves as a floating poly gate 21, bounded on all sides, ex,cept the top, by an oxide insulating layer 23, The floating poly gate 21 is surrounded at its top portion by drain regions 19, but is insulated from the drain regions 0 by ±nsulatlve oxide along the sides of the trench.20,
The top of well layer 17 is covered by an implanted boron field layer 24, i.e. a field implant layer, which is about: Ik Angstroms thick and surrounds the drain regions 19, as well as the floating poly gate 21. Over the boron 5 field implant layer 24 is a thin oxide layer 25 with a control poly layer 27 over the oxidee layer 25 that Is slightly thicker. Control poly layer 27 is planar and resides directly over oxide layer 25 but below a similar oxide layer 29, a tunnel oxide layer, in a sandwich 0 configuration, with, the opposed planar sicLes of the control poly layer 27 between the two oxide layers 25 and 29.
The thickness of control poly layer is about 50 Angstroms, pr-eferably less rather than more, while each 5 of the oxide layers 25 and 29 is about 40 Angstroms. The thickness of the poly layer must be of. the order of the mean path of the carriers, i.e., electrons or holes. Because of the thickness of the poly layer, charge transport through the poly layer is electrically 0 transparent i.e., does not involve energy loss. In other words, since the poly has a thickness on. the order of one mean free path of the charge carriers, there is no opportunity for scattering of the carriers leading to energy loss. This allows low voltages, i.e., about 2 5 volts more or less, to be used for program, erase and
read operations. A tunnel poly region 31 r a, conductive plug fitting into a notch 32 that extends to tunnel oxide layer 29, resides over tunnel oxide layer 29, directly over floating poly gate 21, The tunnel poly region 31 is aligned with the floating poly gate 21 by the notch 32 in insulation layer 33 directly over tunnel oxide layer 29,
In operation, charge may be transferred onto the floating gate 21 by application of proper voltages of the control poly electrode and the drain electrode. With reference to Fig. 2, memory array 41 has rows and columns that feature non-volatile memory transistors 43 that are the devices shown in Fig. 1. Each device defines a memory cell in the x-y memory array 41, The array includes word lines 45 and 47, bit lines 55, 57, and 59, as well as control poly linea 65, 67, and 69. The word lines 45 and 47 are associated with the control poly region 27 in Fig. 1 Each word line makes simultaneous electrical contact with a control poly layer that as common to all memory cells aligned with a notch. 32. At the same time, the tunnel poly lines 65, 67 and 69 make contact with respective tunnel poly regions 31 in Fig. 1, Although the word lines 45 and 47 intersect the tunnel poly lines 65, 67, and 69 in Pig. 2 there is no electrical contact between these lines. Mote that the bit lines 55, 57, and 59 connect to one electrode of the devices of a common column, say the source electrode, while the other subsurface electrode, the drain, is connected to a common array electrode on common line 60 that is held at a potential explained below in reference to Pigs. 3-5. By manipulating voltages on the word lines, bit lines, tunnel poly lines, and the common array electrode, appropriate voltages for writing, erasing and reading memory cells may be applied to the lines. Please note that select transistors and x-y address circuitry is not shown in order to simplify understanding of the
invention, but such circuitry is well known to those skilled in the art.
In Fig, 3 voltages for writing are indicated on the various lines, with the arrow A designating a charge storage operation in which electrical charge is stored on the floating poly gate 21 in Fig. 1. A voltage of +2V is applied to word line 45 while a voltage of ~2V is applied to tunnel poly line 65r a +VD voltage is applied to bit line 55 and a +VD voltage is applied to common source line 60. The value of the voltage -VD depends on the dimensions of source and drain electrodes, as well as other dimensions of the memory array. A typical range of voltage for +VD and -VD might bee +3 ,0 V to -3 ,0 V.
In Fig, 4 voltages for erasing are indicated on the various lines, with the arrow B designating an erase operation in which electrical charge is cleared from the floating poly gate 21 in Fig. l. A voltage of ~2V is applied to word line 45 while a voltage of +2.5 V is applied to tunnel poly line 65, a -VD voltage is applied to bit line 55 and a -VD voltacre is applied to common source line 60.
In Fig. 5 voltages for reading of stored charge or the absence of stored charge on the floating poly gate 21 in Pig. 1 are indicated on the various lines, A voltage of VD is applied to word line 45 while the tunnel poly line 65 is held floating, a +VD voltage is applied to bit line 55 while common source line 60 is held at ground potential. A sense transistor, not shown, is used to measure current from a memory cell relative to a threshold to determine the state of charge of the memory cell Such sense transistors and associated circuitry are wel1 known in the art .
In Fig. 6, the substrate 13 is seen to have a base layer 14 made of p-type material that is part of a doped seraiconductox wafer. Over the base layer 14, a
doped N+ epi layer 15 is formed. Electrical conductivity is sufficient that the layer forms a source electrode, i.e., tlie common line 60 in Fig, 2, termed source layer 15 Thickness of the source layer 15 is typically in the range of 500 A - 1500 A but the thickness is not critical. Above source layer 15, an N epi well layer 17 that is considerably thicker than the epi layer 15, say 2500 A ~ 5000 A thick. Into this well layer 17 a blanket boron field N+ implant layer 24 is formed. Boron field implant layer 24 is about Ik A thick.
In Fig. 7, field implant layer 25 is seen to have been covered by a pad oxide layer 25. Over this layer, a resist layer 26 is uniformly deposited across the wafer or wafer portion where devices are being fabricated. The resist layer 26 is patterned to create openings 22, 28 for an ion beam, indicated by arrows B, to created doped N+ drain regions 19 extending into the upper portion of well layer 17 The resist layer 26 is stripped away by conventional methods and the oxide surface is cleaned before deposition of a nitride layer 30 across the wa fer portion where devices are being fabricated, as seen in Fig. 8. Nitride layer 30 is insulative and has a thickness sufficient to support a new photoresist mask 34 with openings 36 centered on drain regions 19 but not as wide as the drain regions. The operings 36 are used to pattern a deep etch through all layers 30, 25, 24, implant regions 19, and well layer 17 and extending partly into N+ source layer 15. The photoresist mask 34 is then removed, leaving nitride layer 30 as the top layer, as seen in Pig. 9.
In Fig. 9, the deep etch trenches 20 are seen to split drain regions 19 so that the drain regions surround the uppermost region of trenches 20. In Fig. 10 the trenches 20 are lined with a thermal oxide lining 23, i.e., a gate oxide, then filled with polysilicon plug
that become floating polysilicon gates 21. Conductivity of the polysilicon plugs is adjusted by ion implantation into the plugs. The nitride layer 30 is then removed using a wet etch and the poly floating gates 21 are planarized with a dry etch. A top oxide sealant layer 29 is applied across the top of the device region as seen in Fig. 11. The thickness of this layer is approximately 40 Angstroms .but his is not critical
In Fig. 12, a thin P+ control poly layer 27, approximately 50 Angstroms thick extends over the pad oxide layer 25. The control poly layer 27 will function as a control gate as explained with reference to Fig. 2. Above the control poly layer 27 is tunnel oxide layer 29 which is also thin, say between 20 and 40 Angstroms thick. Above the tunnel oxide layer 29, a chemical vapor deposition oxide layer 33, sometimes known as TBOS, is deposited with a thickness in the range of 500-1000 Angstroms. A nitride layer, not shown, may optionally be deposited over oxide layer 33. Next, a photoresist layer 38 is deposited over oxide layer 33 and then patterned to create openings that form notch 32. The oxide in notch 32 is removed with an etch before the photoresist is removed. The wafer is cleaned and tunnel oxide is applied in the notch 32. Tunnel poly plugs 31 are applied over individual floating gates to drive electrical charge to and from the poly floating gates 21, as seen in Fig. 1.
Claims
1. A non-volatile EEPROM transistor device comprising; a substx-ate having a base layer (14) of a first conductive type; a source layer of second conductivity type suitable for electrode use covering the base layer; a well layer of a second conductivity type less conductive than the source layer, with spaced apart drain regions of the second conductivity type suitable for electrode use , and a trench between the drain regions ; a conductive charge storage element (21) in electrically floating relation seated in the trench; a first oxide layer over the substrate; a control poly layer over the first tunnel oxide layer; a second oxide layer over the control poly layer; art insulative layer over the second oxide layer; and poly contacts (31) disposed over the second oxide layer and over the charge storage element .
2. The, device of claim 1 wherein the base layer in P type.
3. The device of claim l wherein the source layer is N+ type.
4. The device of claim 1 wherein the well layer is N type .
5. The device of claim l wherein the drain regions are N+ type .
6. The device of claim 1 wherein the control poly layer has P type dopant.
7, The device of claim 1 wherein conductive charge storage element has N type dopant,
8. The device of claim 1 wherein poly contacts have a N type dopant .
9. A buried floating gate non-volatile EEPROM memory device coraprising: a substrate having a base layer of a first conductivity type, a source layer of a strongly doped second conductive type over the base layer and a top layer of the second conductive type over the source layer; an insulated trench filled with a first poly elug having an upward end; a drain electrode of the strongly doped second conductive type in proximity to the upward end of the poly plug within the top layer; a conductive control layer over the poly plug having a thickness of about 50 A in insulated relation to the poly plug by a first oxide layer; and a second poly plug in insulated relation over the conductive control layer by a second oxide layer.
10. The device of claim 9 wherein word lines of a memory array are associated with the control poly layer.
11. The device of claim 9 wherein a bit line of a memory array is associated with one of the source and drain layers
12. The device of claim 11 wherein a common line of a memory array is associated with the other of the source and drain layers .
13. The device of claim 11 wherein a tunnel poly line of a memory array is associated with a tunnel poly region.
14. A method of making an EBPROM device comprising: forming a, conductive charge storage element in a planar substrate in insulated relation to nearby source and drain regions also within the substrate; forming a thin control poly layer in insulated relation over the substrate, the thickness of the control poly layer being- on the order of the mean free path distance of a charge carrier; and disposing a tunnel poly region in insulated relation over the thin control poly layer and aligned over the conductive charge storage elements,
IS. The method of claim 14 wherein a memory array is formed by providing rows and columns of said EEPROM devices .
16. The method of claim 15 further defined by providing word lines for the memory array associated with the thin poly control layer.
17. The method of claim IS further defined by providing bit lines for the memory array associated with one of the source and drain regions.
18. The method of claim 15 further defined by providing common lines for the memory array associated with the other of the source and drain regions.
19. The methOd of claim 15 .further defined by providing t.unnel poly lines for the memory array, associated with the. tunnel poly regions
2.0. The method of claim 14 further defined by forming source and drain regions in vertical relation one above the other in proximity to the : charge, .storage element .
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/265,854 US7554151B2 (en) | 2005-11-03 | 2005-11-03 | Low voltage non-volatile memory cell with electrically transparent control gate |
| US11/265,854 | 2005-11-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2007056682A2 true WO2007056682A2 (en) | 2007-05-18 |
| WO2007056682A3 WO2007056682A3 (en) | 2008-06-12 |
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ID=37995141
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2006/060510 WO2007056682A2 (en) | 2005-11-03 | 2006-11-03 | Low voltage nanovolatile memory cell with electrically transparent control gate |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7554151B2 (en) |
| TW (1) | TW200807698A (en) |
| WO (1) | WO2007056682A2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7554151B2 (en) | 2005-11-03 | 2009-06-30 | Atmel Corporation | Low voltage non-volatile memory cell with electrically transparent control gate |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI355087B (en) * | 2008-04-10 | 2011-12-21 | Nanya Technology Corp | Two bits u-shape memory structure and method of ma |
| US7948027B1 (en) * | 2009-12-10 | 2011-05-24 | Nanya Technology Corp. | Embedded bit line structure, field effect transistor structure with the same and method of fabricating the same |
| US9466730B2 (en) | 2014-01-17 | 2016-10-11 | Vanguard International Semiconductor Corporation | Semiconductor device and method for fabricating the same |
| TWI557916B (en) * | 2014-04-25 | 2016-11-11 | 世界先進積體電路股份有限公司 | Semiconductor device and method of manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6906379B2 (en) * | 2003-08-28 | 2005-06-14 | Silicon Storage Technology, Inc. | Semiconductor memory array of floating gate memory cells with buried floating gate |
| US20050169049A1 (en) * | 2004-02-04 | 2005-08-04 | Bohumil Lojek | Non-volatile memory array with simultaneous write and erase feature |
| US20050194632A1 (en) * | 2003-09-04 | 2005-09-08 | Atmel Corporation | Method of making nonvolatile transistor pairs with shared control gate |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5432739A (en) * | 1994-06-17 | 1995-07-11 | Philips Electronics North America Corporation | Non-volatile sidewall memory cell method of fabricating same |
| JPH08306914A (en) * | 1995-04-27 | 1996-11-22 | Nippondenso Co Ltd | Semiconductor device and its manufacture |
| JP2964969B2 (en) * | 1996-12-20 | 1999-10-18 | 日本電気株式会社 | Nonvolatile semiconductor memory device and method of manufacturing the same |
| TW385550B (en) * | 1998-05-27 | 2000-03-21 | United Microelectronics Corp | Electrically erasable programmable read only flash memory |
| JP2002009248A (en) * | 2000-06-26 | 2002-01-11 | Oki Electric Ind Co Ltd | Capacitor and its manufacturing method |
| US6720611B2 (en) * | 2002-01-28 | 2004-04-13 | Winbond Electronics Corporation | Fabrication method for flash memory |
| US6919599B2 (en) * | 2002-06-28 | 2005-07-19 | International Rectifier Corporation | Short channel trench MOSFET with reduced gate charge |
| US20040004863A1 (en) * | 2002-07-05 | 2004-01-08 | Chih-Hsin Wang | Nonvolatile electrically alterable memory device and array made thereby |
| US6958513B2 (en) * | 2003-06-06 | 2005-10-25 | Chih-Hsin Wang | Floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells |
| US7554151B2 (en) | 2005-11-03 | 2009-06-30 | Atmel Corporation | Low voltage non-volatile memory cell with electrically transparent control gate |
-
2005
- 2005-11-03 US US11/265,854 patent/US7554151B2/en active Active
-
2006
- 2006-11-01 TW TW095140353A patent/TW200807698A/en unknown
- 2006-11-03 WO PCT/US2006/060510 patent/WO2007056682A2/en active Search and Examination
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6906379B2 (en) * | 2003-08-28 | 2005-06-14 | Silicon Storage Technology, Inc. | Semiconductor memory array of floating gate memory cells with buried floating gate |
| US20050194632A1 (en) * | 2003-09-04 | 2005-09-08 | Atmel Corporation | Method of making nonvolatile transistor pairs with shared control gate |
| US20050169049A1 (en) * | 2004-02-04 | 2005-08-04 | Bohumil Lojek | Non-volatile memory array with simultaneous write and erase feature |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7554151B2 (en) | 2005-11-03 | 2009-06-30 | Atmel Corporation | Low voltage non-volatile memory cell with electrically transparent control gate |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200807698A (en) | 2008-02-01 |
| US20070096222A1 (en) | 2007-05-03 |
| US7554151B2 (en) | 2009-06-30 |
| WO2007056682A3 (en) | 2008-06-12 |
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