WO2007092747A3 - Multi-core architecture with hardware messaging - Google Patents

Multi-core architecture with hardware messaging Download PDF

Info

Publication number
WO2007092747A3
WO2007092747A3 PCT/US2007/061509 US2007061509W WO2007092747A3 WO 2007092747 A3 WO2007092747 A3 WO 2007092747A3 US 2007061509 W US2007061509 W US 2007061509W WO 2007092747 A3 WO2007092747 A3 WO 2007092747A3
Authority
WO
WIPO (PCT)
Prior art keywords
cores
digital circuit
digital
message
hardware
Prior art date
Application number
PCT/US2007/061509
Other languages
French (fr)
Other versions
WO2007092747A2 (en
Inventor
William M Johnson
Jeffrey L Nye
Original Assignee
Texas Instruments Inc
William M Johnson
Jeffrey L Nye
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/627,786 external-priority patent/US20070180310A1/en
Application filed by Texas Instruments Inc, William M Johnson, Jeffrey L Nye filed Critical Texas Instruments Inc
Publication of WO2007092747A2 publication Critical patent/WO2007092747A2/en
Publication of WO2007092747A3 publication Critical patent/WO2007092747A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
    • G06F9/3828—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage with global bypass, e.g. between pipelines, between clusters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
    • G06F9/3891—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Multi Processors (AREA)

Abstract

Disclosed herein are a system and method for designing digital circuits. In some embodiments, the digital circuits (200) include processors having dedicated messaging hardware (210) that enable processor cores (212) to minimize interrupt activity related to inter- core communications. The messaging hardware receives (604) and parses (610) any message in its entirety prior to passing the contents of the message on to the digital circuit. In other embodiments, the digital circuit functionalities are partitioned across individual cores to enable parallel execution. Each core may be provided with standardized messaging hardware that shields internal implementation details from all other cores. This modular approach accelerates development and testing, and renders parallel circuit design to more efficiently attain feasible speedups. These digital circuit cores may be homogenous or heterogeneous.
PCT/US2007/061509 2006-02-02 2007-02-02 Multi-core architecture with hardware messaging WO2007092747A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US76449706P 2006-02-02 2006-02-02
US60/764,497 2006-02-02
US11/627,786 US20070180310A1 (en) 2006-02-02 2007-01-26 Multi-core architecture with hardware messaging
US11/627,786 2007-01-26

Publications (2)

Publication Number Publication Date
WO2007092747A2 WO2007092747A2 (en) 2007-08-16
WO2007092747A3 true WO2007092747A3 (en) 2008-04-03

Family

ID=38345880

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/061509 WO2007092747A2 (en) 2006-02-02 2007-02-02 Multi-core architecture with hardware messaging

Country Status (1)

Country Link
WO (1) WO2007092747A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9934079B2 (en) * 2010-05-27 2018-04-03 International Business Machines Corporation Fast remote communication and computation between processors using store and load operations on direct core-to-core memory

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040006584A1 (en) * 2000-08-08 2004-01-08 Ivo Vandeweerd Array of parallel programmable processing engines and deterministic method of operating the same
US20040163020A1 (en) * 2002-01-25 2004-08-19 David Sidman Apparatus method and system for registration effecting information access

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040006584A1 (en) * 2000-08-08 2004-01-08 Ivo Vandeweerd Array of parallel programmable processing engines and deterministic method of operating the same
US20040163020A1 (en) * 2002-01-25 2004-08-19 David Sidman Apparatus method and system for registration effecting information access

Also Published As

Publication number Publication date
WO2007092747A2 (en) 2007-08-16

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