WO2007094873A3 - Back-gated semiconductor device with a storage layer - Google Patents

Back-gated semiconductor device with a storage layer Download PDF

Info

Publication number
WO2007094873A3
WO2007094873A3 PCT/US2006/060639 US2006060639W WO2007094873A3 WO 2007094873 A3 WO2007094873 A3 WO 2007094873A3 US 2006060639 W US2006060639 W US 2006060639W WO 2007094873 A3 WO2007094873 A3 WO 2007094873A3
Authority
WO
WIPO (PCT)
Prior art keywords
storage layer
wafer
layer
semiconductor device
semiconductor structure
Prior art date
Application number
PCT/US2006/060639
Other languages
French (fr)
Other versions
WO2007094873A2 (en
Inventor
Craig T Swift
Gowrishankar L Chindalore
Thuy B Dao
Michael A Sadd
Original Assignee
Freescale Semiconductor Inc
Craig T Swift
Gowrishankar L Chindalore
Thuy B Dao
Michael A Sadd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, Craig T Swift, Gowrishankar L Chindalore, Thuy B Dao, Michael A Sadd filed Critical Freescale Semiconductor Inc
Priority to CN2006800468797A priority Critical patent/CN101416281B/en
Priority to JP2008545894A priority patent/JP5230870B2/en
Publication of WO2007094873A2 publication Critical patent/WO2007094873A2/en
Publication of WO2007094873A3 publication Critical patent/WO2007094873A3/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40114Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40117Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887Programmable transistors with more than two possible different levels of programmation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923Programmable transistors with more than two possible different levels of programmation

Abstract

Providing a first wafer (103) and a second wafer (101) having a first side and a second side, the second wafer (101) including a semiconductor substrate (105), a storage layer (107), and a layer of gate material (105) The storage layer (107) may be located between the semiconductor structure (105) and the layer of the gate material (105) and the storage layer (107) may be located closer to the first side of the second wafer (101) than the semiconductor structure (105) The method further includes bonding the first side of the second wafer (101) to the first wafer (103), removing a first portion of the semiconductor structure (105) to leave a layer of the semiconductor structure (105) after the bonding, and forming a transistor having a channel region (203), wherein at least a portion of the channel region (203) is formed from the layer of the semiconductor structure.
PCT/US2006/060639 2005-12-14 2006-11-08 Back-gated semiconductor device with a storage layer WO2007094873A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN2006800468797A CN101416281B (en) 2005-12-14 2006-11-08 Back-gated semiconductor device with a storage layer and methods for forming thereof
JP2008545894A JP5230870B2 (en) 2005-12-14 2006-11-08 Manufacturing method and structure of semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/300,077 US7679125B2 (en) 2005-12-14 2005-12-14 Back-gated semiconductor device with a storage layer and methods for forming thereof
US11/300,077 2005-12-14

Publications (2)

Publication Number Publication Date
WO2007094873A2 WO2007094873A2 (en) 2007-08-23
WO2007094873A3 true WO2007094873A3 (en) 2008-11-06

Family

ID=38139941

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/060639 WO2007094873A2 (en) 2005-12-14 2006-11-08 Back-gated semiconductor device with a storage layer

Country Status (4)

Country Link
US (1) US7679125B2 (en)
JP (1) JP5230870B2 (en)
CN (1) CN101416281B (en)
WO (1) WO2007094873A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI479609B (en) * 2010-05-19 2015-04-01 Winbond Electronics Corp Method for forming a flash memory device
US9780231B1 (en) 2016-09-21 2017-10-03 Globalfoundries Singapore Pte. Ltd. Integrated circuits with flash memory and methods for producing the same
US10522561B2 (en) 2017-08-23 2019-12-31 Yangtze Memory Technologies Co., Ltd. Method for forming a three-dimensional memory device
CN107464817B (en) * 2017-08-23 2018-09-18 长江存储科技有限责任公司 A kind of production method of 3D nand flash memories
US11061146B2 (en) * 2019-01-24 2021-07-13 International Business Machines Corporation Nanosheet radiation dosimeter

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4894693A (en) * 1985-05-01 1990-01-16 Tigelaar Howard L Single-polysilicon dram device and process
US20040108537A1 (en) * 2002-12-06 2004-06-10 Sandip Tiwari Scalable nano-transistor and memory using back-side trapping
US6888198B1 (en) * 2001-06-04 2005-05-03 Advanced Micro Devices, Inc. Straddled gate FDSOI device
US20050101072A1 (en) * 2001-11-02 2005-05-12 Andres Bryant Transistor structure with thick recessed source/drain structures and fabrication process of same
US6943084B2 (en) * 2001-09-10 2005-09-13 Samsung Electronics Co., Ltd. Semiconductor device on silicon-on-insulator and method for manufacturing the semiconductor device

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH461646A (en) * 1967-04-18 1968-08-31 Ibm Field-effect transistor and process for its manufacture
US5273921A (en) 1991-12-27 1993-12-28 Purdue Research Foundation Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor
JP2817500B2 (en) * 1992-02-07 1998-10-30 日本電気株式会社 Nonvolatile semiconductor memory device
JP2877103B2 (en) 1996-10-21 1999-03-31 日本電気株式会社 Nonvolatile semiconductor memory device and method of manufacturing the same
US5773331A (en) 1996-12-17 1998-06-30 International Business Machines Corporation Method for making single and double gate field effect transistors with sidewall source-drain contacts
US6064589A (en) 1998-02-02 2000-05-16 Walker; Darryl G. Double gate DRAM memory cell
US6339002B1 (en) 1999-02-10 2002-01-15 International Business Machines Corporation Method utilizing CMP to fabricate double gate MOSFETS with conductive sidewall contacts
TWI231969B (en) 1999-03-26 2005-05-01 Mosel Vitelic Inc Method for forming dual-gate MOS and interconnect with self-aligned contact
US6365465B1 (en) 1999-03-19 2002-04-02 International Business Machines Corporation Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques
US6392271B1 (en) 1999-06-28 2002-05-21 Intel Corporation Structure and process flow for fabrication of dual gate floating body integrated MOS transistors
US6642115B1 (en) 2000-05-15 2003-11-04 International Business Machines Corporation Double-gate FET with planarized surfaces and self-aligned silicides
US6982460B1 (en) 2000-07-07 2006-01-03 International Business Machines Corporation Self-aligned gate MOSFET with separate gates
JP4823408B2 (en) * 2000-06-08 2011-11-24 ルネサスエレクトロニクス株式会社 Nonvolatile semiconductor memory device
GB0021030D0 (en) * 2000-08-26 2000-10-11 Koninkl Philips Electronics Nv A method of forming a bottom-gate thin film transistor
KR100401130B1 (en) 2001-03-28 2003-10-10 한국전자통신연구원 Ultra small size vertical MOSFET device and fabrication method of the MOSFET device
US6646307B1 (en) 2002-02-21 2003-11-11 Advanced Micro Devices, Inc. MOSFET having a double gate
US6580132B1 (en) 2002-04-10 2003-06-17 International Business Machines Corporation Damascene double-gate FET
US6870213B2 (en) * 2002-05-10 2005-03-22 International Business Machines Corporation EEPROM device with substrate hot-electron injector for low-power
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US6812527B2 (en) 2002-09-05 2004-11-02 International Business Machines Corporation Method to control device threshold of SOI MOSFET's
JP3634830B2 (en) * 2002-09-25 2005-03-30 株式会社東芝 Power semiconductor device
JP4121844B2 (en) 2002-12-12 2008-07-23 新日本無線株式会社 Variable gain amplifier
US6946696B2 (en) 2002-12-23 2005-09-20 International Business Machines Corporation Self-aligned isolation double-gate FET
CN1194415C (en) * 2003-05-29 2005-03-23 北京大学 Back-gate MOS transistor, and manufacturing method thereof and static RAM
US6909139B2 (en) * 2003-06-27 2005-06-21 Infineon Technologies Ag One transistor flash memory cell
US6919647B2 (en) 2003-07-03 2005-07-19 American Semiconductor, Inc. SRAM cell
US7280456B2 (en) 2003-07-28 2007-10-09 Intel Corporation Methods and apparatus for determining the state of a variable resistive layer in a material stack
US7018873B2 (en) 2003-08-13 2006-03-28 International Business Machines Corporation Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate
KR100576703B1 (en) * 2003-10-23 2006-05-03 한국전자통신연구원 Metal-insulator transition high speed switching device and method for manufacturing the same
DE10361695B3 (en) * 2003-12-30 2005-02-03 Infineon Technologies Ag Transistor structure for dynamic random-access memory cell has recess structure between source/drain regions and vertical gate electrode enclosing active region on at least 2 sides
US6855982B1 (en) 2004-02-02 2005-02-15 Advanced Micro Devices, Inc. Self aligned double gate transistor having a strained channel region and process therefor
KR100546409B1 (en) * 2004-05-11 2006-01-26 삼성전자주식회사 2-bit SONOS type memory cell comprising recessed channel and manufacturing method for the same
US7132751B2 (en) * 2004-06-22 2006-11-07 Intel Corporation Memory cell using silicon carbide
CN100479193C (en) * 2004-08-17 2009-04-15 北京大学 Floating gate flash field effect transistor
US7276760B2 (en) * 2005-02-25 2007-10-02 Micron Technology, Inc. Low power memory subsystem with progressive non-volatility
US7402850B2 (en) * 2005-06-21 2008-07-22 Micron Technology, Inc. Back-side trapped non-volatile memory device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4894693A (en) * 1985-05-01 1990-01-16 Tigelaar Howard L Single-polysilicon dram device and process
US6888198B1 (en) * 2001-06-04 2005-05-03 Advanced Micro Devices, Inc. Straddled gate FDSOI device
US6943084B2 (en) * 2001-09-10 2005-09-13 Samsung Electronics Co., Ltd. Semiconductor device on silicon-on-insulator and method for manufacturing the semiconductor device
US20050101072A1 (en) * 2001-11-02 2005-05-12 Andres Bryant Transistor structure with thick recessed source/drain structures and fabrication process of same
US20040108537A1 (en) * 2002-12-06 2004-06-10 Sandip Tiwari Scalable nano-transistor and memory using back-side trapping

Also Published As

Publication number Publication date
CN101416281A (en) 2009-04-22
CN101416281B (en) 2012-03-21
JP5230870B2 (en) 2013-07-10
WO2007094873A2 (en) 2007-08-23
US7679125B2 (en) 2010-03-16
US20070134888A1 (en) 2007-06-14
JP2009520364A (en) 2009-05-21

Similar Documents

Publication Publication Date Title
JP2007520891A5 (en)
TW200742045A (en) Semiconductor device having a recess channel transistor
WO2006104562A3 (en) Method of forming a semiconductor device having asymmetric dielectric regions and structure thereof
WO2006034189A3 (en) High-mobility bulk silicon pfet
WO2006036985A3 (en) Shallow source mosfet
WO2005086237A3 (en) Ldmos transistor and method of making the same
TW200635037A (en) Semiconductor device with increased channel length and method for fabricating the same
WO2006086636A3 (en) Power mos device
WO2008051503A3 (en) Light-emitter-based devices with lattice-mismatched semiconductor structures
TW200610067A (en) Thin channel mosfet with source/drain stressors
WO2007018918A3 (en) Nitride-based transistors and fabrication methods with an etch stop layer
WO2003058723A1 (en) Organic thin-film transistor and manufacturing method thereof
WO2008120335A1 (en) Semiconductor device, and its manufacturing method
TW200633125A (en) Semiconductor device and method of semiconductor device
TW200625634A (en) Transistor with strained region and method of manufacture
WO2006070297A3 (en) Enhancement - depletion semiconductor structure and method for making it
WO2008105077A1 (en) Compound semiconductor device and process for producing the same
WO2008005916A3 (en) Method for making planar nanowire surround gate mosfet
SG139657A1 (en) Structure and method to implement dual stressor layers with improved silicide control
TW200731530A (en) Semiconductor devices and methods for fabricating the same
WO2007124209A3 (en) Stressor integration and method thereof
WO2010051133A3 (en) Semiconductor devices having faceted silicide contacts, and related fabrication methods
TW200707756A (en) Semiconductor device with thin-film transistors and method of fabricating the same
TW200717777A (en) Semiconductor memory device and manufacturing method thereof
WO2009051663A3 (en) Transistor device and method

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200680046879.7

Country of ref document: CN

WWE Wipo information: entry into national phase

Ref document number: 2008545894

Country of ref document: JP

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 06850116

Country of ref document: EP

Kind code of ref document: A2