WO2007095807A1

WO2007095807A1 - A parallel implementing method of iterative detect / decode receiving in a wireless communication system

Info

Publication number: WO2007095807A1
Application number: PCT/CN2006/003157
Authority: WO
Inventors: Xiqi Gao; Wenjin Wang; Xiao Liang; Xiaohu You; Chunming Zhao
Original assignee: Southeast University
Priority date: 2006-02-20
Filing date: 2006-11-24
Publication date: 2007-08-30
Also published as: CN1812309A; CN100369403C

Abstract

A parallel implementing method of iterative detect/decode receiving in a wireless communication system, a implementing method in accordance with wireless transferring and receiving technology, that used in high speed wireless transferring technology field. Said iterative receiver includes four modules, a soft-in soft-out (SISO) detector module (10), a soft-in soft-out decoder module (12), an interleaver module (13), and a de-interleaver module (11). The SISO detector module (12) outputs a new soft information to the de-interleaver module (11) according to the soft information provided by the interleaver module (13) and a received signal. The SISO decoder module (12) reads the soft signal from the de-interleaver (11), and outputs a new soft information to the interleaver (13). The SISO detector module (10) and the SISO decoder module (12) are parallel operating at the same time, and data in the interleaver (13) and the de-interleaver (11) is updated in real time. When the iterative operation is finished, the SISO decoder module (12) outputs decision bits (14). It is possible to process data twice as much as that of the prior art within same period with the same hardware source.

Description

TECHNICAL FIELD The present invention relates to a method for implementing a receiving technology in wireless transmission, and belongs to the technical field of high-speed wireless transmission. BACKGROUND OF THE INVENTION Future wireless communication systems require higher power efficiency and spectral efficiency. Strong error control coding such as Turbo codes or Low Density Parity Check (LDPC) codes allow the system to operate in a lower signal to noise ratio environment, thereby increasing the power efficiency of the system. Multi-antenna transmission and multi-antenna reception technology can greatly improve the system's ability to transmit information, thereby improving spectral efficiency. Broadband single-carrier transmission makes the wireless channel a frequency selective channel. Therefore, at the receiving end, there is intersymbol interference between signals. Especially at the receiving end of the multi-antenna wireless transmission system, the received signal has both inter-symbol interference and existence. Interference between antennas. In such a channel environment where there is not only fading and noise, but also interference, the iterative detection decoding receiver can greatly improve the system error at the same transmission power compared with the conventional detection decoding cascaded receiver. Rate (BER) or frame error rate (FER) performance. Or in order to achieve a particular BER or PER, the system needs less transmit power. Figure 1 shows the transmitter structure and iterative detection decoding receiver structure of a general multi-antenna bit interleaved coded modulation baseband system. The working principle of the iterative detection decoding receiver is that it works iteratively between the detector and the decoder, and multiple soft information (usually expressed by log likelihood ratio) is used between the two to exchange the information. Make a judgment. After the transmission bit is subjected to error control coding, it is interleaved, and then mapped into a complex baseband signal, and shunted to each transmission antenna for transmission. At the receiving end, the detector calculates new soft information based on the received signal and the soft information fed back by the decoder, de-interleaves it and sends it to the decoder. Based on the de-interleaved soft information and coding constraints, the decoder obtains new soft information and interleaves it into the detector. In general, detectors and decoders usually use different algorithms, so in hardware implementations, such as programmable logic devices or implementations of ASICs, detectors and decoders need to use different hard The module implementation is referred to as a detection module and a decoding module in the description of this specification. There are two main implementation methods at present. One is the pipeline implementation structure of the detection module-decoding module. This structure has high hardware use efficiency, but the receiver processing delay of the implementation structure is too high to meet the future. Low latency requirements for communication systems. Another serial implementation structure, the detection module and the decoding module are serially operated, that is, in a certain iterative process, the decoding module starts to work after the detection module finishes working, and likewise, the 'decoding module ends working. The post-detection module begins the next round of work. This implementation structure allows two hardware modules to work only alternately, and the hardware resources have only about half of the use efficiency at the same time, so that the processing delay of the iterative detection decoding receiver is relatively large. It is of great practical significance to design an efficient and low processing delay iterative detection decoding receiver implementation structure. Disclosure of Invention Technical Problem An object of the present invention is to provide a parallel implementation method for an iterative detection decoding receiver of a wireless communication system, which improves the use efficiency of hardware resources in the same hardware resource as compared with the conventional serial implementation method. Under the condition, the processing delay of the iterative detection decoding receiver is reduced. Technical solution: The iterative receiver includes four modules, a soft input soft output detection module, a soft input soft output decoding module, an interleaving module and an inverse interleaving module; and a soft input soft output detection module according to the soft information provided by the interleaving module. Receiving a signal, outputting new soft information to the anti-interleaving module; and the soft input soft output decoding module reads soft information from the anti-interleaving module, and outputs new soft information to the interleaving module; and soft input soft output detecting module and soft input The soft output decoding module simultaneously works in parallel, and performs real-time data updating in the interleaving module and the de-interleaving module; until the end of the iterative operation, the soft input soft output decoding module will output the decision bit.

Both the interleaving module and the anti-interleaving module are implemented by reading and writing dual-port memory. When the soft input soft output detecting module and the soft input soft output decoding module work simultaneously, the soft input soft output decoding module outputs the likelihood ratio of each bit. When the interleaved module is stored in the interleaved module, the bits of each likelihood ratio output by the soft input soft output detecting module are stored in the deinterleaving module according to the deinterleaved address.

The soft input soft output decoding module adopts iterative decoding, and the soft input soft output decoding module outputs soft information to the interleaver every iteration of decoding iteration. The parallel implementation structure method and working principle are described in four aspects: detection module, decoding module, interleaving and de-interleaving module, and working sequence. 1. The detection module detection module calculates the soft information and sends it to the de-interleaver according to the data of the received signal buffer and the interleaving module. The detection algorithm can employ any detection algorithm that detects the soft input soft output, such as the minimum mean square error filtered interference cancellation detection (MMSE-IC) algorithm or the matched filtered interference cancellation (MF-IC) algorithm. The data in the receive signal buffering and interleaving module is read in sequence by the detector, and the calculated result is stored in the de-interleaving module according to the de-interleaved address. The detection module starts to work when the receive signal buffer output is enabled, and waits until the last data in the receive signal buffer is taken, and then returns to the address of the first data for the next round of detection. After the detection of a certain number of times is completed, the data in the received signal buffer is updated, and the iterative detection and decoding of the next frame of data is performed.

2. The decoding module decodes the data in the anti-interleaving module, performs decoding of the soft input soft output according to the constraint relationship of the error control coding, and outputs the decoded soft information to the interleaving module. The specific soft input soft output decoding algorithm needs to be determined according to different error control coding. For example, the convolutional code and the turbo code can use the maximum a posteriori probability decoding (MAP) algorithm or a log-domain MAP (log-MAP) algorithm. The LDPC code can use a Confidence Propagation (BP) algorithm. In the iterative detection decoding of one frame of data, when the data outputted by the anti-interleaving module by the detecting module is filled for the first time, the decoding module is enabled, and the decoding module starts to work, in order from the de-interleaving module. The read data is decoded, and the result is stored in the interleaver according to the interleaved address. After all the data of one frame is decoded, the next round of decoding is started from the first data of one frame. After a certain number of decodings, the result of the decoder is output to the bit determiner for decision, and the final processing result of the receiver is obtained. Error control codes such as Turbo, LDPC, etc., are also used in the decoding itself, such as MAP, log-MAP, BP algorithm, and the like. In the iteration of each decoding module and detection module of the serial implementation structure, the decoder always outputs soft information to the interleaver after completing a certain number of its own iterations. In the parallel implementation structure proposed by the present invention, the decoding module always outputs the result to the interleaving module cyclically. By varying the ratio of processing delays between the decoding module and the internal implementation of the detection module, it is possible to determine the number of iterations of the decoder itself each time the decoding iteration is detected. 3. Interleaving module and anti-interleaving module In the parallel implementation structure, both the decoding module and the detecting module work continuously at the same time, and the decoding module needs to continuously read data from the de-interleaving module and continuously write data to the interleaving module. At the same time, the detection module also continuously reads data from the interleaving module and continuously writes the data to the de-interleaving module. Therefore, at the same time, both the interleaving module and the de-interleaving module are both read data and data. One convenient and resource-saving implementation is to use a dual-port memory. While each data is output from the detection module or the decoding module, the address control module generates an interleave address and an anti-interleave address, and also generates two sequential addresses in a natural order, and the detection module reads the data from the interleaver according to the sequential address. And the output data is stored in the anti-interleave module according to the de-interleaved address, and the decoding module reads the data from the de-interleaver according to the sequential address, and the output data is stored in the interleaving module according to the interleave address. It is worth mentioning that, since the general read-write dual-port RAM requires that the read/write addresses cannot conflict, in the design of the interleaver generation algorithm, the read address and write address of the interleaving and deinterleaving modules must be guaranteed at the same time. Can not be equal, this is not difficult to do in the design of the interleaver.

4. Working Timing Figure 3 compares the timing diagrams of the serial and parallel implementations. Compared with the two, the parallel implementation structure proposed by the present invention has three main differences. First, it is easy to know from the figure that under the serial implementation structure, at the same time, only one of the detection module and the decoding module is working; and in the parallel structure, after the first detection, the detection module and the translation Code modules can work in parallel at the same time. Second, under the serial implementation structure, after all the data of the iterative detection module or the decoding module is outputted, the interleaving or deinterleaving is performed. In the parallel structure, the interleaving and deinterleaving processes are real-time, each When the data is output. Third, when the decoding itself uses an iterative decoding algorithm, under the serial implementation structure, the decoding module sends the result to the interleaver after a certain number of self-iterations, and in the structure of the present invention, the decoding module When a new result is obtained, it is sent to the interleaver. Advantageous Effects: The parallel implementation method of the iterative detection decoding receiver provided by the present invention effectively overcomes the disadvantages of low hardware use efficiency and long delay in the same hardware compared with the existing serial implementation method. Resources reduce the latency of receiver processing, thereby increasing the speed at which hardware can process data Rate. As can be seen from FIG. 3, in the case where the number of iterations between the soft input soft output detection module and the soft input soft output decoding module is large, the parallel implementation method of the iterative detection decoding receiver given by the present invention is the same as the existing Compared with the serial implementation method, it can reduce the delay by nearly double, that is, the same hardware resources can be used to process twice the data in the same time. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a block diagram showing a structure of a transmitter and a receiver structure of an iterative detection decoding of a general multi-antenna bit interleaved coded modulation baseband system.

Figure 2 is a schematic diagram of the parallel implementation structure.

FIG. 3 is a schematic diagram showing the operation timing of the existing serial implementation structure and parallel implementation structure. DETAILED DESCRIPTION The iterative receiver includes four modules, a soft input soft output detection module, a soft input soft output decoding module, an interleaving module and an inverse interleaving module; and a soft input soft output detection module according to the soft information provided by the interleaving module. Receiving a signal, outputting new soft information to the anti-interleaving module; and the soft input soft output decoding module reads soft information from the anti-interleaving module, and outputs new soft information to the interleaving module; and soft input soft output detecting module and soft input The soft output decoding module simultaneously works in parallel, and performs real-time data updating in the interleaving module and the de-interleaving module; until the end of the iterative operation, the soft input soft output decoding module will output the decision bit.

The soft input soft output decoding module adopts iterative decoding, and the soft input soft output decoding module outputs the soft information to the interleaver every iteration of the iterative decoding.

The detection module starts to work continuously from the input signal of the receiver, calculates soft information and outputs it to the de-interleaving module one by one. When the data in the de-interleaving module is full, the decoder starts to work continuously, and the data in the de-interleaving module is taken out one by one. After calculation, new data is obtained, and they are sent to the interleaving module one by one.

The invention provides a parallel implementation structure of an iterative detection decoding receiver to meet future mobile communication System efficient, low latency requirements. The specific implementation is as follows:

(1) Determine the parameters of the receiver according to the frame structure transmitted by the system, such as the interleave length, the decoding length, the data rate, and the like.

(2) Select the number of iterations between the detector and decoder algorithm and the detector and decoder according to the performance requirements of BER, FER and other hardware resource conditions. If an iterative decoding algorithm is used, the total number of iterations of the decoder needs to be determined.

(3) Design a parallel implementation structure of the iterative receiver according to the technical scheme 1-4.

(3.1) According to the soft input soft output detection algorithm determined in step (2), the soft input soft output detection module is designed and implemented according to the method described below.

The detection module calculates the soft information and sends it to the inverse interleaver based on the data of the received signal buffer and interleaving module. The detection algorithm can use any detection algorithm that detects soft input soft output, such as interference reduction cancellation (MMSE-IC) algorithm of minimum mean square error filtering or interference cancellation (MF-IC) algorithm of matched filtering. The data in the receive signal buffering and interleaving module is read in sequence by the detector, and the calculated result is stored in the de-interleaving module according to the de-interleaved address. The detection module starts working when the receive signal buffer output is enabled, and waits until the last data in the receive signal buffer is taken, and then returns to the address of the first data for the next round of detection. After the detection of a certain number of times is completed, the data in the received signal buffer is updated, and the iterative detection and decoding of the next frame of data is performed.

(3.2) According to the soft input soft output decoding algorithm determined in step (2), the soft input soft output decoding module is designed and implemented according to the method described below. The decoding module reads the data in the anti-interleaving module, performs decoding of the soft input soft output according to the constraint relationship of the error control coding, and outputs the decoded soft information to the interleaving module. The specific soft input soft output decoding algorithm needs to be determined according to different error control coding. For example, the convolutional code and the turbo code can use the maximum a posteriori probability decoding (MAP) algorithm or a log-domain MAP (log-MAP) algorithm. The LDPC code can use a Confidence Propagation (BP) algorithm. In the iterative detection decoding of one frame of data, when the data outputted by the anti-interleaving module by the detecting module is filled for the first time, the decoding module is enabled, and the decoding module starts to work, in order from the de-interleaving module. The read data is decoded, and the result is stored in the interleaver according to the interleaved address. After all the data of one frame is decoded, the next round of decoding is started from the first data of one frame. After a certain number of decodings, the result of the decoder is output to the bit determiner for decision, and the final processing result of the receiver is obtained. Error control codes such as Turbo, LDPC, etc., are also used in the decoding itself, such as MAP, log-MAP, BP algorithm, and the like. In the iteration of each decoding module and detection module of the serial implementation structure, the decoder always outputs soft information to the interleaver after completing a certain number of its own iterations. In the parallel implementation structure proposed by the present invention, the decoding module always outputs the result to the interleaving module cyclically. By varying the ratio of processing delays between the decoding module and the internal implementation of the detection module, it is possible to determine the number of iterations of the decoder itself each time the decoding iteration is detected.

(3.3) The interleave module and the anti-interleave module are implemented according to the following design. In the parallel implementation structure, both the decoding module and the detection module work continuously at the same time, the decoding module needs to continuously read data from the de-interleaving module, and continuously write data to the interleaving module, and at the same time, the detecting module also needs Data is continuously read from the interleaving module and data is continuously written to the de-interleaving module. Therefore, at the same time, both the interleaving module and the de-interleaving module are both read data and data. One convenient and resource-saving implementation is to use a dual-port memory. While each data is output from the detection module or the decoding module, the address control module generates an interleave address and an anti-interleave address, and also generates two sequential addresses in a natural order, and the detection module reads the data from the interleaver according to the sequential address. And the output data is stored in the anti-interleave module according to the de-interleaved address, and the decoding module reads the data from the de-interleaver according to the sequential address, and the output data is stored in the interleaving module according to the interleave address. It is worth mentioning that, since the general read-write dual-port RAM requires that the read/write addresses cannot conflict, in the design of the interleaver generation algorithm, the read address and write address of the interleaving and deinterleaving modules must be guaranteed at the same time. Can not be equal, this is not difficult to do in the design of the interleaver.

(3.4) The iterative receiver is designed with timing as described below.

Figure 3 compares the timing diagrams of the serial and parallel implementations. Compared to the two, the parallel implementation architecture proposed by the present invention has three main differences. First, it is easy to know from the figure that under the serial implementation structure, at the same time, only one of the detection module and the decoding module is working; and in the parallel structure, after the first detection, the detection module and the translation Code modules can work in parallel at the same time. Second, under the serial implementation structure, after all the data of the iterative detection module or the decoding module is outputted, the interleaving or deinterleaving is performed. In the parallel structure, the interleaving and deinterleaving processes are real-time, each Data output When it is done. Third, when the decoding itself uses an iterative decoding algorithm, under the serial implementation structure, the decoding module sends the result to the interleaver after a certain number of self-iterations, and in the structure of the present invention, the decoding module When a new result is obtained, it is sent to the interleaver.

Claims

Claim

A parallel implementation method for iterative detection decoding reception of a wireless communication system, characterized in that the iterative receiver comprises four modules, a soft input soft output detection module, a soft input soft output decoding module, an interleaving module and a reverse The interleaving module; the soft input soft output detecting module outputs new soft information to the anti-interleaving module according to the soft information and the receiving signal provided by the interleaving module; and the soft input soft output decoding module reads the soft information from the anti-interleaving module, and outputs the new Soft information to the interleaving module; and the soft input soft output detection module and the soft input soft output decoding module work concurrently, real-time data update in the interleaving module and the anti-interlacing module; until the end of the iterative work, the soft input soft output The decoding module will output the decision bit.

2. The parallel implementation method for iterative detection decoding reception of a wireless communication system according to claim 1, wherein the interleaving module and the anti-interleaving module are implemented by using a read/write dual port memory, and a soft input soft output detection module and a soft input. When the soft output decoding module simultaneously works iteratively, when the soft input soft output decoding module outputs the likelihood ratio of each bit, the interleaved module is stored according to the interleaved address, and each likelihood of the soft input soft output detection module output is output. The bits of the ratio are stored in the de-interleaving module according to the de-interleaved address.

3. A parallel implementation method for iterative detection decoding reception of a wireless communication system according to claim 2, wherein the soft input soft output decoding module employs iterative decoding, and the soft input soft output decoding module iterates over itself. The soft information is output to the interleaver each decoding iteration of the decoding.