WO2007110306A3 - Method and arithmetic unit for operating a memory device - Google Patents

Method and arithmetic unit for operating a memory device Download PDF

Info

Publication number
WO2007110306A3
WO2007110306A3 PCT/EP2007/052169 EP2007052169W WO2007110306A3 WO 2007110306 A3 WO2007110306 A3 WO 2007110306A3 EP 2007052169 W EP2007052169 W EP 2007052169W WO 2007110306 A3 WO2007110306 A3 WO 2007110306A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory device
data
logic segment
stored
logic
Prior art date
Application number
PCT/EP2007/052169
Other languages
German (de)
French (fr)
Other versions
WO2007110306A2 (en
Inventor
Jens Liebehenschel
Original Assignee
Bosch Gmbh Robert
Jens Liebehenschel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bosch Gmbh Robert, Jens Liebehenschel filed Critical Bosch Gmbh Robert
Priority to EP07712480A priority Critical patent/EP2002342A2/en
Publication of WO2007110306A2 publication Critical patent/WO2007110306A2/en
Publication of WO2007110306A3 publication Critical patent/WO2007110306A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7202—Allocation control and policies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7205—Cleaning, compaction, garbage collection, erase control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7207—Details relating to flash memory management management of metadata or control data

Abstract

The invention relates to a method for operating a memory device for storing modifiable data (110',..., 118', 301,..., 305). According to said method: at least two logic segments (100, 150) are provided, a first of said segments (100) being identified as an active logic segment; a data element (116', 301) to be stored is stored in the active logic segment (100, 150); the memory device is reorganised and a second logic segment (150) is identified as a new active logic segment; data (110',..., 118') that is stored in the first logic segment (100) is transmitted to the second logic segment (150); and data (301,..., 305) from a working memory device (300) is stored in the second logic segment (150), if the data (301,..., 305) in the working memory device (300) does not correspond to the data (110',..., 118') in the first logic segment (100). The invention also relates to a corresponding arithmetic unit, a corresponding computer programme and a computer programme product. The solution according to the invention permits the service life of the memory device to be increased.
PCT/EP2007/052169 2006-03-24 2007-03-08 Method and arithmetic unit for operating a memory device WO2007110306A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP07712480A EP2002342A2 (en) 2006-03-24 2007-03-08 Method and arithmetic unit for operating a memory device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102006013759.0 2006-03-24
DE102006013759.0A DE102006013759B4 (en) 2006-03-24 2006-03-24 Method and computing unit for operating a memory device

Publications (2)

Publication Number Publication Date
WO2007110306A2 WO2007110306A2 (en) 2007-10-04
WO2007110306A3 true WO2007110306A3 (en) 2008-02-07

Family

ID=38091190

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2007/052169 WO2007110306A2 (en) 2006-03-24 2007-03-08 Method and arithmetic unit for operating a memory device

Country Status (3)

Country Link
EP (1) EP2002342A2 (en)
DE (1) DE102006013759B4 (en)
WO (1) WO2007110306A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102013019941A1 (en) * 2013-11-27 2015-05-28 Giesecke & Devrient Gmbh Method for operating a storage system and such a storage system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5822781A (en) * 1992-10-30 1998-10-13 Intel Corporation Sector-based storage device emulator having variable-sized sector

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10321104B4 (en) 2003-05-09 2016-04-07 Robert Bosch Gmbh Method for filing variable data

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5822781A (en) * 1992-10-30 1998-10-13 Intel Corporation Sector-based storage device emulator having variable-sized sector

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
GAL E ET AL: "ALGORITHMS AND DATA STRUCTURES FOR FLASH MEMORIES", ACM COMPUTING SURVEYS, ACM, NEW YORK, NY, US, US, vol. 37, no. 2, June 2005 (2005-06-01), pages 138 - 163, XP002453935, ISSN: 0360-0300 *

Also Published As

Publication number Publication date
DE102006013759B4 (en) 2023-03-16
EP2002342A2 (en) 2008-12-17
WO2007110306A2 (en) 2007-10-04
DE102006013759A1 (en) 2007-09-27

Similar Documents

Publication Publication Date Title
WO2007110294A3 (en) System, method and computer program product for storing multiple types of information
WO2004057479A3 (en) Page descriptors for prefetching and memory management
WO2007064477A3 (en) Network access control for many-core systems
WO2011040950A3 (en) Power interrupt management
GB2461841A (en) System comprising a plurality of processing and methods of operating the same
TW200609730A (en) Information processing apparatus and information processing method
TW200712875A (en) Method for fast switching between different operating systems in computer device with multiple operating systems
MY149197A (en) Ranking functions using document usage statistics
WO2006109289A3 (en) Smartcard power management
IL206847A0 (en) Dynamic address translation with frame management
TW200834298A (en) System, method, and computer program product for saving power in a multi-graphics processor environment
WO2004114128A3 (en) Instruction controlled data processing device
WO2004095212A3 (en) Memory management in a data processing system
WO2008114375A1 (en) Thin client terminal, its operating program and method, and thin client system
WO2006073666A3 (en) Selecting instruction set architectures using instruction address attributes
WO2008063647A3 (en) Delaying an operation that reduces a lifetime of memory
DE602004004101D1 (en) MACHINING MESSAGE DIGEST COMMANDS
WO2006129207A3 (en) Method of connecting mass storage device
WO2006050145A3 (en) Methods and apparatus for parallel execution of a process
SG155253A1 (en) Global switch resource manager
WO2012112710A3 (en) Systems and methods for managing data input/output operations
WO2009032732A3 (en) Secure computer working environment utilizing a read-only bootable media
WO2009075070A1 (en) Common cache control device, common cache control method, and integrated circuit
JP2003132005A5 (en)
WO2008030727A3 (en) Access control of memory space in microprocessor systems

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07712480

Country of ref document: EP

Kind code of ref document: A2

REEP Request for entry into the european phase

Ref document number: 2007712480

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2007712480

Country of ref document: EP