WO2007115227A3 - Multi-port memory device having variable port speeds - Google Patents

Multi-port memory device having variable port speeds Download PDF

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Publication number
WO2007115227A3
WO2007115227A3 PCT/US2007/065723 US2007065723W WO2007115227A3 WO 2007115227 A3 WO2007115227 A3 WO 2007115227A3 US 2007065723 W US2007065723 W US 2007065723W WO 2007115227 A3 WO2007115227 A3 WO 2007115227A3
Authority
WO
WIPO (PCT)
Prior art keywords
port
clock
memory device
ports
operate
Prior art date
Application number
PCT/US2007/065723
Other languages
French (fr)
Other versions
WO2007115227A2 (en
Inventor
Dongyun Lee
Myung Rai Cho
Sungjoon Kim
Original Assignee
Silicon Image Inc
Dongyun Lee
Myung Rai Cho
Sungjoon Kim
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Image Inc, Dongyun Lee, Myung Rai Cho, Sungjoon Kim filed Critical Silicon Image Inc
Priority to CN2007800185044A priority Critical patent/CN101449334B/en
Priority to EP07759902A priority patent/EP2008281B1/en
Priority to KR1020087026515A priority patent/KR101323400B1/en
Priority to JP2009503325A priority patent/JP5188493B2/en
Publication of WO2007115227A2 publication Critical patent/WO2007115227A2/en
Publication of WO2007115227A3 publication Critical patent/WO2007115227A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4054—Coupling between buses using bus bridges where the bridge performs a synchronising function where the function is bus cycle extension, e.g. to meet the timing requirements of the target bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports

Abstract

A multi-port memory device (100) having two or more ports (110) wherein each port may operate at a different speed. The multi-port memory device contains memory banks that may be accessed via the two or more ports. Two clock signals are applied to each port: a system clock (SCK) and a port clock (PCK). The system clock is applied to port logic (220) that interfaces with the memory banks so that the ports all operate at a common speed with respect to the memory banks. The port clock is applied to a clock divider circuit (230) that is associated with each port. The port clock is divided to a desired frequency or kept at its original frequency. Such a configuration allows the ports to operate at different speeds that may be set on a port-by-port basis.
PCT/US2007/065723 2006-03-30 2007-03-30 Multi-port memory device having variable port speeds WO2007115227A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN2007800185044A CN101449334B (en) 2006-03-30 2007-03-30 Multi-port memory device having variable port speeds
EP07759902A EP2008281B1 (en) 2006-03-30 2007-03-30 Multi-port memory device having variable port speeds
KR1020087026515A KR101323400B1 (en) 2006-03-30 2007-03-30 Multi-port memory device having variable port speeds
JP2009503325A JP5188493B2 (en) 2006-03-30 2007-03-30 Multiport memory device with variable port speed

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US78840106P 2006-03-30 2006-03-30
US60/788,401 2006-03-30

Publications (2)

Publication Number Publication Date
WO2007115227A2 WO2007115227A2 (en) 2007-10-11
WO2007115227A3 true WO2007115227A3 (en) 2007-11-29

Family

ID=38421761

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US2007/065723 WO2007115227A2 (en) 2006-03-30 2007-03-30 Multi-port memory device having variable port speeds
PCT/US2007/065722 WO2007115226A2 (en) 2006-03-30 2007-03-30 Inter-port communication in a multi- port memory device

Family Applications After (1)

Application Number Title Priority Date Filing Date
PCT/US2007/065722 WO2007115226A2 (en) 2006-03-30 2007-03-30 Inter-port communication in a multi- port memory device

Country Status (7)

Country Link
US (2) US7949863B2 (en)
EP (2) EP2008164A2 (en)
JP (2) JP5188493B2 (en)
KR (2) KR101323400B1 (en)
CN (3) CN101449334B (en)
TW (3) TWI386846B (en)
WO (2) WO2007115227A2 (en)

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Also Published As

Publication number Publication date
TW200802403A (en) 2008-01-01
US20070234021A1 (en) 2007-10-04
JP2009532815A (en) 2009-09-10
CN101449262B (en) 2012-07-04
EP2008281A2 (en) 2008-12-31
TWI353124B (en) 2011-11-21
US7949863B2 (en) 2011-05-24
WO2007115226A2 (en) 2007-10-11
KR101323400B1 (en) 2013-10-29
CN101449262A (en) 2009-06-03
JP5188493B2 (en) 2013-04-24
US7639561B2 (en) 2009-12-29
KR20080104388A (en) 2008-12-02
KR101341286B1 (en) 2013-12-12
EP2008281B1 (en) 2012-01-25
KR20090007378A (en) 2009-01-16
TWI340982B (en) 2011-04-21
WO2007115227A2 (en) 2007-10-11
US20070245094A1 (en) 2007-10-18
CN101438242B (en) 2013-09-18
CN101449334B (en) 2012-04-25
CN101438242A (en) 2009-05-20
WO2007115226A3 (en) 2008-10-30
JP2009532782A (en) 2009-09-10
CN101449334A (en) 2009-06-03
TW200802082A (en) 2008-01-01
EP2008164A2 (en) 2008-12-31
TW200818734A (en) 2008-04-16
TWI386846B (en) 2013-02-21
JP5197571B2 (en) 2013-05-15

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