WO2007116238A1 - METHOD OF MANUFACTURING A GaN MOSFET - Google Patents
METHOD OF MANUFACTURING A GaN MOSFET Download PDFInfo
- Publication number
- WO2007116238A1 WO2007116238A1 PCT/IB2006/001248 IB2006001248W WO2007116238A1 WO 2007116238 A1 WO2007116238 A1 WO 2007116238A1 IB 2006001248 W IB2006001248 W IB 2006001248W WO 2007116238 A1 WO2007116238 A1 WO 2007116238A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- manufacturing
- previous
- gan
- regions
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims description 24
- 239000012212 insulator Substances 0.000 claims description 20
- 238000000137 annealing Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052594 sapphire Inorganic materials 0.000 claims description 6
- 239000010980 sapphire Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- HYXGAEYDKFCVMU-UHFFFAOYSA-N scandium(III) oxide Inorganic materials O=[Sc]O[Sc]=O HYXGAEYDKFCVMU-UHFFFAOYSA-N 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- CMIHHWBVHJVIGI-UHFFFAOYSA-N gadolinium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Gd+3].[Gd+3] CMIHHWBVHJVIGI-UHFFFAOYSA-N 0.000 claims description 2
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 2
- 150000004767 nitrides Chemical group 0.000 claims description 2
- -1 Ga2θ3 Inorganic materials 0.000 claims 1
- 238000000034 method Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000001451 molecular beam epitaxy Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000003351 stiffener Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
- H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
- H01L21/26553—Through-implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3245—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering of AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
Abstract
The invention relates to a method of manufacturing a structure for electronics, comprising the following steps: (a) providing a layer of GaN; (b) forming a layer of AIN on the GaN layer; (c) doping the GaN layer at determinate and separate surface regions with doping species for forming therein regions of a greater electrical conductivity. The invention also relates to the manufacturing of a component for electronics, and a structure for electronics.
Description
METHOD OF MANUFACTURING A GaN MOSFET
The invention relates to a method of manufacturing a structure for electronics, comprising the following steps: providing a layer of GaN, or the like, and doping the GaN layer in at least two determinate and separate regions.
By the term "electronics", it is to be understood micro or nano-electronics or optoelectronics.
The said regions have, after doping and eventually heat treatment, a greater conductivity than the rest of the GaN layer. These two doped regions are dedicated to be a source and a drain of an electronic component.
GaN material is used for its better electrical properties than Si for the use in electronic components.
For example, GaN has a critical breakdown field (Ec) approximately 10 times larger than Si, and a larger band gap (Eg)
GaN has particularly a promising potential to permit the development of a new generation of High Power Devices, working at higher operating voltage, at higher current, and at higher ambient temperature.
The high power devices of GaN may be used for Regulating or Rectifying currents and/or voltages.
These high power devices may be power MOSFETs (Metal-Oxide- Semiconductor-Field-Electric-Transistors) or Rectifiers, that are two of the key components of inverter modules, employed in power flow control circuits.
GaN MOSFET Technology is a promising technology for all DC or AC applications demanding device operating at very high voltages (from 100V up to 1kV and beyond), driving large currents.
The applications of high voltage power flow control systems would be for example soft-switching systems (to eliminate harmonics and dramatically improve power quality), or other applications.
These electronic circuits are more generally used to block any voltage and current urges. Indeed, these blocking circuits are required for protecting electronics components and improving reliability. Applications like hybrid electric vehicle could implement this technology in their power control systems.
Typically, with reference to figure 1 , a GaN MOSFET device comprises:
- a substrate 10,
- a thick GaN layer 20 comprising the said doped regions 21 and 22 that respectively form a source and a drain,
- a source pad 40 and a drain pad 50 on top of these regions 21 and 22,
- an insulating layer 30 forming the gate insulator layer of the MOSFET,
- a conductive gate 60 on top of the insulator gate 30, forming an Ohmic contact between them. Like for the Silicon MOSFET, the insulating grid 30 of a GaN MOSFET tends to reduce the leakage and increase the breakdown voltage relative to an equivalent metal gate structures.
Typically, the production of such a device firstly comprises the providing of a thick GaN layer (so-called a template or buffer), obtained for example by crystal growth from the substrate 10.
Secondly, Silicon species are implanted at the said regions beneath for forming a drain and a source, to increase the electrical conductivity of these regions and facilitate the ohmic contact with the pads 40-50 subsequently formed.
Then an insulating layer is deposited on the GaN for forming the gate insulator layer 30.
Finally, a metallization is implemented such as to form the conductive gate layer 60 on the gate insulator layer 30 to form the source pad 40 and the drain pad 50.
Furthermore, an annealing at a temperature greater than 10000C is needed to activate the implanted Silicon dopants in the regions 21-22.
This high temperature degrades the GaN surface roughness.
Accordingly, the annealing degrades the quality of the gate insulator layer 30 which is subsequently deposited on this rough surface.
Alternatively, if the gate insulator 30 is deposited before the annealing step, some of the dielectric materials which constituted it, like some oxides, can not withstand this annealing temperature.
Therefore, these latter dielectrics cannot be deposited prior to annealing. The control of the roughness of the GaN layer 20 is then a critical step of the high power MOSFET manufacturing.
A first object of the invention is to produce a high power FET transistor with an active layer of GaN having a good surface quality.
Another object of the invention is to produce a high power FET transistor with an active layer of GaN having a good surface quality and with a gate insulator made of oxides or other materials which do not withstand temperature higher than about 10000C.
To reach these purposes, the invention proposes, in a first aspect, a method of manufacturing a structure for electronics, comprising the following steps:
(a) providing a layer of GaN;
(b) forming a layer of AIN on the GaN layer;
(c) doping the GaN layer at determinate and separate surface regions with doping species for forming therein regions of a greater electrical conductivity.
Other characteristics of this method of manufacturing a structure for electronics are:
- the step (b) is implemented so that the AIN layer is amorphous;
- the method further comprising the following step, after step (c), a removal of the AIN layer;
- the step (d) includes a wet etch;
- the doping of step (c) comprises a step of implanting the doping species through the AIN layer to the said regions and a step of annealing for diffusing the species into the regions; - the annealing step is operated at a temperature greater than about 10000C;
- the doping species comprises silicon;
- the GaN layer is included in a wafer, the wafer further comprising a substrate for the GaN layer;
- the substrate comprises SiC or sapphire; - the substrate further comprises a monocrystalline semiconductor layer on top of the SiC or sapphire support, like Si;
- the wafer further comprises a buffer layer between the substrate the GaN layer, like a buffer of AIGaN;
- the GaN layer was initially grown. In a second aspect, the invention proposes a method of manufacturing a component for electronics, comprising the following steps:
(a) the said method of manufacturing a structure;
(b) forming a gate insulator layer on a portion of the surface of GaN layer located between the two said regions; (c) forming a conductive gate layer on the gate insulator layer; (d) forming a source pad and a drain pad on the said regions.
Other characteristics of this method of manufacturing a component for electronics are:
- step (b) is implemented by material deposition;
- the material of the deposited gate insulator layer is chosen among oxides, like SiO2, Ga2O3, Gd2O3, MgO, Sc2O3, or other dielectrics, like Si3N4;
In a third aspect, the invention proposes a Structure for electronics, characterized in that it comprises: — a layer of GaN, or the like;
— a layer of AIN on the GaN layer;
- two separated surface regions in the GaN layer comprising doping species, forming regions of a greater electrical conductivity.
Other characteristics of this structure for electronics are: - the doping species comprises silicon;
- the structure further comprises a gate insulator layer extending on a portion of the GaN layer surface located between the two separate regions;
- the structure further comprises a gate conductor layer on a portion the gate insulator layer and a source pad on a first region and a drain pad on a second region;
- the structure is a MOSFET.
Other characteristics, objects, and advantages of the invention will appear clearer in the description below, which is illustrated by the following figures:
Figure 1 shows a schematic cross-section view of a MOS-FET. Figure 2 shows a schematic cross-section view of an intermediate structure for forming an electronic component.
A first step of the method according to the invention is to provide a GaN layer 20.
The GaN layer 20 can be sufficiently thick for constituting a substrate by itself.
Alternatively, the GaN layer 20 is formed onto a stiffener substrate 10.
The material of the substrate 10 can be chosen for having a lattice parameter close to those of the GaN, like bulk SiC or bulk sapphire.
The substrate 10 can alternatively be a composite substrate whose materials are chosen for having a good thermal compatibility with GaN.
To this aim, a substrate 10 comprising a bulk polycrystalline SiC and a Si, sige or Ge layer on top of it can be chosen. This substrate can be realised by a Smart Cut® technique, as teaching for example in FR 0411579 (not published yet).
In a first embodiment, the GaN layer 20 may be bonded to the substrate 10 by well-known wafer bonding techniques - see for example "Semiconductor Wafer Bonding Science and Technology" (Q-Y. Tong et U. Gόsele, a Wiley lnterscience publication, Johnson Wiley & Sons, Inc.) for more precisions.
In a second embodiment, the GaN layer 20 may be grown on the substrate 10.
If the lattice mismatch and/or the difference of thermal crystal expansion between the material(s) constituting the substrate 10 on one side and GaN on the other side, nucleation layer is advantageously formed prior to the growth of the GaN layer 20.
This nucleation step is particularly recommended if the substrate 10 is comprised bulk SiC or bulk Sapphire.
Alternatively, a buffer layer (not shown on figure 1 ) may be provided between the substrate 10 and the GaN layer, whose material(s) is (are) chosen for improving the crystal quality of the GaN layer 20 subsequently grown.
Thus the substrate 10 may further comprises a AIGaN buffer (not shown) grown on the substrate 10.
GaN layer 20 may be grown by either MOCVD (Metal Organic Chemical Vapor Deposition) or MBE (Molecular Beam Epitaxy) epitaxy.
The GaN layer 20 may be grown at around 900 0C for MBE Epitaxy or above 1000 0C for MOCVD.
After GaN growth, a AIN layer 70 is deposited onto the GaN layer 20.
The technique chosen for depositing the AIN layer 70 can be crystal growth, or one among numerous known techniques using sputtering.
Mainly based on the growth conditions, either a crystalline AIN layer 70 or an amorphous AIN layer 70 is grown.
The deposition temperature is advantageously kept at around 600-700 0C.
AIN allows higher temperature during the annealing and keep the roughness of the surface as it was before annealing. Crystalline or amorphous have substantially the same thermal properties.
However amorphous AIN will ease the subsequent etching step after annealing.
The fabrication of the MOSFET comprises then the formation of at least two separated doped regions 21 and 22 in the GaN layer 20, comprising the following steps:
- implantation of doping species, like Si, at the said regions,
- diffusion of the doping species in the GaN by annealing at a temperature of about 10000C or more for activating the Si. Once the doped regions 21-22 are formed, the AIN layer 70 can be kept or at least partially removed.
In one embodiment, this AIN layer 70 is kept.
Beneath the source and drain metallic pads 40-50 subsequently formed, the AIN layer 70 can be kept with a high doping, for increasing the electrical conductivity between the source and drain and doped regions 21-22.
In a second embodiment, the AIN layer 70 is chemically etched and/or mechanically polished.
A dry etch can be chosen, but a wet etch is preferably chosen.
Preferably, the whole AIN layer 70 is removed. Then, the gate insulator 30 is deposed by well-known techniques (see for example "High power GaN Power Devices" - A.P. Zhang, F. Ren, T. I. Anderson, S.J. Pearton, for more precisions).
The gate insulator 30 can be made of at least one oxide material.
Ga2θ3, Gd2θ3, SiO2, MgO and/or Sc2O3 may then be chosen.
Other dielectrics can be chosen, like nitride materials (e.g. Si3N4).
Finally, a metallization is performed for forming a metallic gate 60 between the source 21 and drain 22 regions, as well as a source pad 40 and a drain pad 50 on top of, respectively, the source 21 and drain 22 regions. Other known techniques able to etch such a layer may also be used (see for example "High power GaN Power Devices" - AP. Zhang, F. Ren, T. I. Anderson, SJ. Pearton, for more precisions)
The AIN layer 70 was used here as an encapsulant layer that protects the surface of the GaN layer 20 during annealing from becoming rough. Indeed after the annealing for diffusing the implanted Si species (in order to activate them), the surface of the GaN layer 20 would have been damaged.
It is all the more critical than the device has a large surface (e.g. active surface - including drain 50, source 40 and gate 60 - of the device of the order of 6mm2).
Claims
1. Method of manufacturing a structure for electronics, comprising the following steps:
(a) providing a layer of GaN;
(b) forming a layer of AIN on the GaN layer;
(c) doping the GaN layer at determinate and separate surface regions with doping species for forming therein regions of a greater electrical conductivity.
2. Method of manufacturing a structure according to the previous claim, wherein the step (b) is implemented so that the AIN layer is amorphous.
3. Method of manufacturing a structure according to one of the previous claims, further comprising the following step, after step (c) : (d) removing the AIN layer.
4. Method of manufacturing a structure according to the previous claim, wherein step (d) includes a wet etch.
5. Method of manufacturing a structure according to any of the previous claims, wherein the doping of step (c) comprises a step of implanting the doping species through the AIN layer to the said regions and a step of annealing for diffusing the species into the regions.
6. Method of manufacturing a structure according to any of the previous claims, wherein the annealing step is operated at a temperature greater than about 10000C.
7. Method of manufacturing a structure according to any of the previous claims, wherein the doping species comprises silicon.
8. Method of manufacturing a structure according to any of the previous claims, wherein the GaN layer is included in a wafer, the wafer further comprising a substrate for the GaN layer.
9. Method of manufacturing a structure according to any of the previous claims, wherein the substrate comprises SiC or sapphire.
10. Method of manufacturing a structure according to any of the previous claims, wherein the substrate further comprises a monocrystalline semiconductor layer on top of the SiC or sapphire support, like Si.
11. Method of manufacturing a structure according to any of the previous claims, wherein the wafer further comprises a buffer layer between the substrate the GaN layer.
12. Method of manufacturing a structure according to the previous claim, wherein the buffer comprises AIGaN.
13. Method of manufacturing a structure according to one of the previous claims, wherein the GaN layer was initially grown.
14. Method of manufacturing a component for electronics, comprising the following steps :
(a) method of manufacturing a structure according to one of the previous claims;
(b) forming a gate insulator layer on a portion of the surface of GaN layer located between the two said regions* (c) forming a conductive gate layer on the gate insulator layer;
(d) forming a source pad and a drain pad on the said regions.
15. Method of manufacturing a component according to the previous claim, wherein step (b) is implemented by material deposition.
16. Method of manufacturing a component according to one of the two previous claims, wherein the material of the deposited gate insulator layer is chosen among oxides.
17. Method of manufacturing a component according to the previous claim, wherein the oxide is chosen among SiO2, Ga2θ3, Gd2O3, MgO, or Sc2O3.
18. Method of manufacturing a component according to any of claims 14 and 15, wherein the material of the deposited gate insulator layer is a nitride, like
Si3N4.
19. Structure for electronics, characterized in that it comprises :
- a layer of GaN; — a layer of AIN on the GaN layer;
— two separated surface regions in the GaN layer comprising doping species, forming regions of a greater electrical conductivity.
20. Structure for electronics according to the previous claim, wherein the doping species comprises silicon.
21. Structure for electronics according to the previous claim, further comprising a gate insulator layer extending on a portion of the GaN layer surface located between the two separate regions.
22. Structure for electronics according to the previous claim, further comprising a gate conductor layer on a portion the gate insulator layer and a source pad on a first region and a drain pad on a second region.
23. Structure for electronics according to the previous claim, wherein it is a MOSFET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/IB2006/001248 WO2007116238A1 (en) | 2006-04-11 | 2006-04-11 | METHOD OF MANUFACTURING A GaN MOSFET |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/IB2006/001248 WO2007116238A1 (en) | 2006-04-11 | 2006-04-11 | METHOD OF MANUFACTURING A GaN MOSFET |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2007116238A1 true WO2007116238A1 (en) | 2007-10-18 |
Family
ID=37909394
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/IB2006/001248 WO2007116238A1 (en) | 2006-04-11 | 2006-04-11 | METHOD OF MANUFACTURING A GaN MOSFET |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO2007116238A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11264492B2 (en) | 2019-07-09 | 2022-03-01 | United Microelectronics Corp. | High electron mobility transistor and method for fabricating the same |
| US11482600B1 (en) | 2019-09-05 | 2022-10-25 | United States of America as represented by Wright-Patterson the Secretary of the Air Force | Alignment-tolerant gallium oxide device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0112657A2 (en) * | 1982-11-29 | 1984-07-04 | Fujitsu Limited | Field effect transistor and process for fabricating it |
| EP0224614A1 (en) * | 1985-12-06 | 1987-06-10 | International Business Machines Corporation | Process of fabricating a fully self- aligned field effect transistor |
| US4863879A (en) * | 1987-12-16 | 1989-09-05 | Ford Microelectronics, Inc. | Method of manufacturing self-aligned GaAs MESFET |
| EP0987746A1 (en) * | 1998-09-18 | 2000-03-22 | Lucent Technologies Inc. | Method of making an integrated circuit comprising an oxide layer on a GaAs-based semiconductor substrate |
| US6297538B1 (en) * | 1998-03-23 | 2001-10-02 | The University Of Delaware | Metal-insulator-semiconductor field effect transistor having an oxidized aluminum nitride gate insulator formed on a gallium nitride or silicon substrate |
| US20040041169A1 (en) * | 2002-08-26 | 2004-03-04 | Fan Ren | GaN-type enhancement MOSFET using hetero structure |
| US20040043548A1 (en) * | 2002-08-27 | 2004-03-04 | Redd Randy D. | Method for forming a semiconductor device |
-
2006
- 2006-04-11 WO PCT/IB2006/001248 patent/WO2007116238A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0112657A2 (en) * | 1982-11-29 | 1984-07-04 | Fujitsu Limited | Field effect transistor and process for fabricating it |
| EP0224614A1 (en) * | 1985-12-06 | 1987-06-10 | International Business Machines Corporation | Process of fabricating a fully self- aligned field effect transistor |
| US4863879A (en) * | 1987-12-16 | 1989-09-05 | Ford Microelectronics, Inc. | Method of manufacturing self-aligned GaAs MESFET |
| US6297538B1 (en) * | 1998-03-23 | 2001-10-02 | The University Of Delaware | Metal-insulator-semiconductor field effect transistor having an oxidized aluminum nitride gate insulator formed on a gallium nitride or silicon substrate |
| EP0987746A1 (en) * | 1998-09-18 | 2000-03-22 | Lucent Technologies Inc. | Method of making an integrated circuit comprising an oxide layer on a GaAs-based semiconductor substrate |
| US20040041169A1 (en) * | 2002-08-26 | 2004-03-04 | Fan Ren | GaN-type enhancement MOSFET using hetero structure |
| US20040043548A1 (en) * | 2002-08-27 | 2004-03-04 | Redd Randy D. | Method for forming a semiconductor device |
Non-Patent Citations (5)
| Title |
|---|
| EITING C J ET AL: "Activation studies of low-dose Si implants in gallium nitride", APPLIED PHYSICS LETTERS, AIP, AMERICAN INSTITUTE OF PHYSICS, MELVILLE, NY, US, vol. 73, no. 26, 28 December 1998 (1998-12-28), pages 3875 - 3877, XP012021718, ISSN: 0003-6951 * |
| HASEGAWA F ET AL: "Passivation properties of plasma CVD AlN films for GaAs", JAPANESE JOURNAL OF APPLIED PHYSICS, PART 2 (LETTERS) JAPAN, vol. 26, no. 9, September 1987 (1987-09-01), pages L1448 - L1450, XP002431301, ISSN: 0021-4922 * |
| HASEGAWA F ET AL: "PLASMA CVD OF AMORPHOUS ALN FROM METALORGANIC AL SOURCE AND PROPERTIES OF THE DEPOSITED FILMS", JAPANESE JOURNAL OF APPLIED PHYSICS, JAPAN SOCIETY OF APPLIED PHYSICS, TOKYO, JP, vol. 26, no. 9, September 1987 (1987-09-01), pages 1555 - 1560, XP000818527, ISSN: 0021-4922 * |
| MATOCHA K ET AL: "High-voltage accumulation-mode lateral RESURF GaN MOSFETs on SiC substrate", 2003 IEEE 15TH. INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICESAND IC'S PROCEEDINGS. CAMBRIDGE, UIK, APRIL 14 - 17, 2003, INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & IC'S, NEW YORK, NY : IEEE, US, 14 April 2003 (2003-04-14), pages 54 - 57, XP010653724, ISBN: 0-7803-7876-8 * |
| QIAO D ET AL: "Low resistance ohmic contacts on AlGaN/GaN structures using implantation and the advancing Al/Ti metallization", APPLIED PHYSICS LETTERS, AIP, AMERICAN INSTITUTE OF PHYSICS, MELVILLE, NY, US, vol. 74, no. 18, 3 May 1999 (1999-05-03), pages 2652 - 2654, XP012022548, ISSN: 0003-6951 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11264492B2 (en) | 2019-07-09 | 2022-03-01 | United Microelectronics Corp. | High electron mobility transistor and method for fabricating the same |
| US11804544B2 (en) | 2019-07-09 | 2023-10-31 | United Microelectronics Corp. | High electron mobility transistor and method for fabricating the same |
| US11482600B1 (en) | 2019-09-05 | 2022-10-25 | United States of America as represented by Wright-Patterson the Secretary of the Air Force | Alignment-tolerant gallium oxide device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102403038B1 (en) | Electronic Power Device Integrated with Machined Substrate | |
| US8703623B2 (en) | Fabrication technique for gallium nitride substrates | |
| CN109844184B (en) | Engineered substrate structures for power and radio frequency applications | |
| US8765577B2 (en) | Defect free strained silicon on insulator (SSOI) substrates | |
| US7183175B2 (en) | Shallow trench isolation structure for strained Si on SiGe | |
| TWI518898B (en) | Group iii-n hemt with a floating substrate region and a grounded substrate region | |
| CN111512415B (en) | System and method for engineering integrated devices on a substrate | |
| WO2011072027A2 (en) | Reverse side engineered iii-nitride devices | |
| KR20200077558A (en) | Power and RF devices implemented using machined substrate structures | |
| WO2017144852A1 (en) | Layered vertical field effect transistor and methods of fabrication | |
| CN116705605A (en) | Silicon-based gallium nitride HEMT device and preparation method thereof | |
| WO2007116238A1 (en) | METHOD OF MANUFACTURING A GaN MOSFET | |
| US8318563B2 (en) | Growth of group III nitride-based structures and integration with conventional CMOS processing tools | |
| CN115863400B (en) | High-heat-conductivity GaN-based HEMT device and preparation method thereof | |
| EP4287239A1 (en) | A low loss semiconductor substrate | |
| US20240021724A1 (en) | GaN TRENCH MOSFET AND FABRICATION METHOD | |
| US10446677B2 (en) | Semiconductor structures and method for fabricating the same | |
| CN116936639A (en) | Polarization matching enhancement type transistor modulated by SiN stress and preparation method | |
| JP2023550520A (en) | Method for manufacturing a transistor with high electron mobility and the manufactured transistor | |
| CN116598203A (en) | Gallium nitride HEMT device and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 06727597 Country of ref document: EP Kind code of ref document: A1 |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 06727597 Country of ref document: EP Kind code of ref document: A1 |