WO2007117977A2 - Memory cell with reduced size and standby current - Google Patents

Memory cell with reduced size and standby current Download PDF

Info

Publication number
WO2007117977A2
WO2007117977A2 PCT/US2007/064952 US2007064952W WO2007117977A2 WO 2007117977 A2 WO2007117977 A2 WO 2007117977A2 US 2007064952 W US2007064952 W US 2007064952W WO 2007117977 A2 WO2007117977 A2 WO 2007117977A2
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
dielectric film
dopant
aperture
film layer
Prior art date
Application number
PCT/US2007/064952
Other languages
French (fr)
Other versions
WO2007117977A3 (en
Inventor
Bohumil Lojek
Original Assignee
Atmel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corporation filed Critical Atmel Corporation
Publication of WO2007117977A2 publication Critical patent/WO2007117977A2/en
Publication of WO2007117977A3 publication Critical patent/WO2007117977A3/en

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/947Subphotolithographic processing

Definitions

  • the invention relates to non-volatile memory cell and memory arrays and, in particular, to a compact architectural arrangement for fabrication of non-volatile memory devices with low standby current and a method of making same,
  • non-volatile memory device retains data even after power to th,e device Is terminated
  • One particular type of non-volatile memory device i.s an electrically erasable programmable read only memory (E ⁇ PROM) device.
  • E ⁇ PROM electrically erasable programmable read only memory
  • programming and ⁇ erasing are accomplished by transferring electrons to and from a floating gate electrode through, a thin dielectric layer, known as a tunnel-oxide layer, located between the floating gate elactrode and an underlying substrate.
  • a voltage is coupled to the floating gate electrode by a control gate electrode, also known as a programming region.
  • the control gate electrode or programming region is capacitively coupiled to the floating gate electrode such that a yoltage applied to the programming region is coupled to the floating gate electrode.
  • a traditional ESPROM device utilizes the floating gate, in a field effect transistor structure, positioned, over tout insulated from a channel region in the semiconductor substrate, and between source and drain regions.
  • a threshold voltage characteristic of the transistor is controlled by an amount of charge that is retained on the floating gate. Thus, a minimum amount of voltage (i.e., the threshold voltage) must be applied to the coirrol gate ibefore the transistor is turned “on, " thus permitting conduction between source and drain regions of the transistor. Conduction is controlled by the amount of charge on the floating gate .
  • a memory transistor is programmed or erased to one of two states by transferring electrons from the substrate channel region, through a tunnel window constructed in the thin dielectric tunnel! layer and onto and from the floating gate .
  • a state of the memory transistor is read by placing an operating voltage across the source and drain with an additional! voltage on the control gate of the memory transistor.
  • a level of current flowing between the source and dr.ain is detected to determine whether the device is programmed to be "on” or "off” for a given control gate volt.age,
  • a specific single memory transistor cell i-n a two-dimensional array of EEPROM memory cells is addressed for reading by (1) applying a source-drain volt-age to source and drain lines in a column containing the cell being addressed, and; (2) applying a contra! gate voltage to the control gates in a row containing the cell being addressed.
  • EEPROM memory cells may be erased electrically.
  • One way in which the cell is erased electrically is by transfer" of charge from the floating gate to the transistor drain through a thin tunnel dielectric layer.1 Charge transfer is again accomplished by applying appropriate voltages to the source, drain, and control gate of the floating gate transistor.
  • An array of ⁇ SPROM cells is generally referred to as a Flash EEPROM array because an entire array of cells, or a significant group of cells, is erased simultaneously.
  • Flash EEPROM arrays become increasingly larger in terms of storage capacity, the semiconductor industry has attempted various ways of reducing a size of individual memory cells, and thus, reducing a size of the entire array. The size reduction however cannot impact reliability nor critical characteristics of the memory device such as standby current.
  • the reduction in sise of individual memory cells means an overall reduction in the area of the memory array. With more devices available in a given area, it is critical that each device maintains as low a standby current as possible.
  • EEPROM cell size has been limited by the x-equired width of the active region,
  • a primary limiting ;factor in determining the active region width is the size of the tunnel window.
  • the tunnel window is defined by lithography which produces a limitation on a minimum aperture size for the tunnel window.
  • the active area is required by process design rules to extend beyond this minimum aperture size. Consequently, this requirement determines a minimum width of the memory device conduction channel. To achieve a maximum of saturation current through the conduction channel, it is desirable to maximize the ratio of width to length of the ;memory device.
  • the lithographic limits in determining the minimum width of ithe tunnel window also determine a minimum width of (the memory device. With the width of the memory device determined, the length of the memory device is also determined.
  • the constraints determined by the feature size of the tunnel window therefore produce a limitation on the scalability of the EEPROM cell and in turn limit the ability to minimize the memory cell si ⁇ e.
  • the present invention is a 1 method, and resulting device,: for fabricating memory cells with an extremely small area and low standby! current .
  • the low standby current requirement is met by two factors as we&l.
  • the present invention is a method of fabricating an electronic integrated circuit device on a first surface of a substrate (e.g., a silicon wafer) .
  • the method includes forming a first dielectric layer, such as silicon dioxide (e.g., thermally or deposited) .
  • At least one additional dielectric film Hayer is then formed over the first dielectric film llayer.
  • An aperture is created and spacers are formed on sidewalls of the aperture. The spacers are produced such that a distance between spacers on opposing sidewalls of fchie aperture is less than a limit of optical photolithography.
  • An injector dopant region is then formed withi.il the aperture created by the spacers and a portion of thie area immediately adjacent.
  • the first dielectric film Layer and an upper portion of the substrate und ⁇ rlying thie second aperture are etched and covered with a dielectr-ic layer, thus forming the tunneling window.
  • Figs. IA - IH are; an exemplary embodliment of process steps employing a sspacer application and tunneling window fabrication technique used in the present invention.
  • a cross-section A-A of Fig. IA includes a substrace 101, a first dielectric layer 103A, a second dielectric layer 105, and a third dielectric layer 107 in an exemplary embodiment of the present invention.
  • the second dielectric layer 105 and the third dielectric layer 107 contain a first aperture 108.
  • the substrate 101 may be comprised of various materials known in the semiconductor art . Such materials include silicon (or other group IV materials), compound semiconductors (e.g., compounds of elements, especially elements from periodic table groups IH-V and II-V1), quartz reticles, or other suitable materials.
  • the substrate 10l is a p-type silicon wafer (or alternatively, a p-type well in a substrate)
  • the first dielectric layer 103A is a silicon dioxide layer and may be formed by a thermal oxidation technique or alternatively may be deposited by any of a variety of techniques such as atomic layer deposition (ALD) , chemical vapor deposition (CVD) , low-pressure CVD
  • the second dielectric layer 105 and tliird dielectric layer 107 are substantially comprised of silicon nitride and TEOS oxide ⁇ tetra-ethoxysilane or tehraethyl orthosilicate) respectively.
  • a selective etchant such as a highly selective dry etch or wet chemical etch is chosen to etch the third dielectric layer 107 and the second dielectric layer 105, thus forming a first aperture 10S.
  • Etching of underlying layers can occur through various wet-etch techniques (e.g., the first dielectric layer 103A may be etched in hydrofluoric acid, such as contained in a standard buffered oxide etch (BOE) , or orthophosphoric acid) or dry etch techniques (e.g., reactive-ion -etching (RIE)) .
  • BOE buffered oxide etch
  • RIE reactive-ion -etching
  • one or more selective etchants are chosen such that there is a high selectivity of etch rate between the second and third dielecciric layers 105, 107 and the underlying first dielectric layer 103A. Therefore, due co the selectivity of the etchant itself there is no need for critical timingi as the first dielectric layer :1Q3A acts as an etch stop for the second and third dielectric layers 105, 107.
  • This selective etch capability is used to produce the first aperture 108 and similar techniques are used in subsequent process steps .
  • a blanket dielectric spacer layer (not shown) is formed for example, by CVD or LPCVD techniques.
  • the dielectric spacer- layer is chosen to be chemically dissimilar to the underlying etched third dielectric layer 107.
  • the dielectric spacer layer may be chosen to be silicon nitride, In this way, an etchant which is selective between silicon dioxide and silicon nirride allows the etched third dielectric (e.g., TEOS oxide) layer 107 to act as an etch stop for etching a dielectric spacer 109 from the spacer dielectric (e.g., silicon nitride) .layer.
  • This first spacer etch step is exemplified with reference to both the plan view and a cross -sectional view A-A of Fig, IA.
  • a dielectric spacer 109 is formed on the first aperture sidewalls by a selecti"/e etchant.
  • the selective etchant is used to etch the dielectric spacer 109 without substantially affecting an integrity of any other layer.
  • Etching of the spacer laye ⁇ r is performed such that substantiality all horizontal surfaces- (i.e., those paralie_ to the face of the substrate) are etched while leaving surfaces cthat are essentially vertical substantially intact.
  • the resulting: width of the dielectric spacert 109 is essentially the thickness of the spacer dielectric layer deposited before selective etching.
  • the dielectric spacert 109 is a thickness; of 500A f a thickness of the second dielectric (i_.e., a step thickness) is IOOOA, ind a thickness of the first dielectric layer 103A is lOG-JOOA, Such- etches, ais those of the spacer dielectric layer,t are accomplished by, for example, a reactiv"* ion etch.
  • the plan view of! Fig- IA indicates both a size of trs second aperture through the spacer layer and visible layers.
  • the layers visible at this stage of fabrication are the patterned dielectric spacer 109, the third dielectric layer 107, and the substrate 101.
  • typical photolithographic techniques are limited by physical constraints of the photolithographic system involving actinic radiation wavelength, ⁇ , and geometrical configurations of the projection system optics. According to Kayleigh's criterion,
  • a "width" of the dielectric spacer 109 is dependent upon a .thickness of the deposited spacer layer and a step height; of a proximate structure; the dielectric spacer! 109 is approximately 0.7 - t, where is the thickness of the combined thicknesses of the etched second and third dielectric layers 105, 107.
  • the width at the spacers and, consequently any underlying features may be fabricated to be extremely small. Therefore, the fabrication method described herein, and.
  • a device resulting from employing the method may have, components that are formed below a limit of resolution of optical photolithography by utilizing spacers to separate laterally displaced features ⁇ i.e., features that have spatial dimensio ⁇ is less than the limit of resolution in planes parallel to a face of a substrate or wafer, or "x-y" dimensions) * i
  • the plan view of Fig. IA indicates how the dielectric spaced 109 can significantly reduce a size of an aperture.
  • the first aperture 108 For example, compare a, size of the first aperture 108 opening onto the third dielectric layer 107 with a size of the second aperture now open to the substrate 101, If the first aperture 108 were at the limit of resolution for a particular photolithographic stepper, in this case, 0.18 ⁇ m, a.nd the thickness of the spacer dielectric layer was 100 nm (i.e., 0,10 ⁇ m) , then the aperture sise "S" between the spacers 109 on opposing sidewalls of the original aperture (i.e., the aperture opening onto the substrate 101) is !
  • the second aperture formed by the dielectric spaceris 109 may be significantly less than the limit of resolution of the stepper. ;
  • An additional benefit is that ai select transistor width can also be scaled down to a minimum size, thus ; ⁇ eeping current through the devide minimized while enabling further scaling capabilities. Further elaboration on a difference in a select gate width versus a storage gate width is discussed infra.
  • the first dielectric layer 103A is etched to form an etched first dielectric layer 103B and an etch aperture 110 exposing a portion of the substrate 101.
  • the second aperture formed by the dielectric spacer 109 (Fig, IA) is used to perform a selective etch on the first dielectric layer 103A to form the etched first ' dielectric layer 103B and Che etch aperture 110.
  • the etch aperture 110 is formed by the selective etch, the third dielectric layer 107, the second dielectric layer 105, and the dielectric spacers
  • etchants 109 are removed by a sequence of the etchants such as those mentioned supra.
  • the size of the etch .aperture 110 formed by the dielectric spacer exposes a portion of the substrate IQl. A relative indication of the small size of the etch aperture 110 is demonstrated.
  • the substrate 101 is selectiyely etched to produce an etched substrate recess 113.
  • the substrate 101 is iover etched, through the etch aperture
  • the dielectric spacer 109 thus serves as an etch mask.
  • T ⁇ ie dielectric spacer 109 also serves ;o limit an area for; a subsequent dopant step, thereby forming an injector; dopant region 111.
  • the injector dopant region ill may be formed by processes known to a skilled artisan and include techniques such as diffusion and ion implantation.
  • the injector dopant region ill per the present exemplary embodiment, is made by doping a localized area (e.g., through injector ion implantation) creating a subsurface highly-doped region for i-eeeiving bias from a nearby contact for charge generation, i.e., a tunneling injector.
  • a localized area e.g., through injector ion implantation
  • a small feature size of the etched substrate recess 113 is carried through to a recessed first dielectric layer 103C with a thin oxide grown osrer the etcned substrate recess 113.
  • the thin oxide is, for example, the same material as the etched first dielectric layer IQBB.
  • an initial floating gate 115A and an initial etched fortn dialectic layer 117A are fabricated on the recessed first dieLectric layer 103C above /the etched substrata recess 1,13 and the injector dopant region 111 so as to form a floating gate portion of a storage device.
  • Fabrication of the initial floating gate 115A and the initial etched fourrth dielectric layer I117A commences withi a first semiconductor layer (not shown) being deposited across the first surface of the substrate IDl. A subsequent deposition of a flourth dielectric layer (not shown) is applied on top of the first dielectric layer 1.03B.
  • the first semiconductor layer and the fcurth dielectric layer are etched to form the initial floating gate 1.15ft. and the initial etched fcurth dielectric laylsr 117A wi,th a non- critical gate length 118.
  • the first semiconduictor layer, in the present exemplary embodiment ⁇ is a highi concentration n-tiype polysilicon material . Wi-th reference to the plan view of Fig.
  • the initial etched fourth dielectric layer 117A is situated atop the initial floating gate 115A and the recessed first dielectric layer 103C.
  • a second semiconductor layer 119A is deposited in a conformal layer across the upper surface of the recessed first dielectric layer 103C which covers the initial floating gate 115A and the initial etched fourth dielectric layer 117A.
  • the second semiconductor layer 119A is an undoped polysilicon material.
  • a photoresist material is deposited on top of the second semiconductor layer 119A and is processed to form a patterned photoresist layer 121,
  • the patterning of the patterned photoresist layer 121 produces a select gate region 123 in close proximity to the floating gate portion (i.e., the initial floating gate 115A and the initial etched fourth dielectric layer 117A) of the storage device (Fig. ID) .
  • a high concentration of p-type dopant material is applied at the select gate implant region 123 and into the exposed second semiconductor layer 1L9A.
  • a skulled artisan would readily consider an ion implantation technique for injecting the dopant at the select gate implant region 123 or other effective means for application of thie high concentration p-type dopant naterial .
  • a fifth dielectric layer 125A is deposited in a conformal layer across an tipper surface of the recessed first dielectric layer 1Q3C and over a storage gate 119 B i and a select gate 119 B2 .
  • a final etched structure of a floating gate 115B and an etched fourth dielectric layer 117B with a final gate length 120 is produced.
  • the final gate length 120 dimension is less than the non-critical gate length 118 (Fig. ID).
  • the second semiconductor layer 119A (Fig. IE) is selectively patterned with photoresist and selectively etched (not shown) to form the storage gate 119 B i and the select gate 2.19 B ⁇ ,
  • the select gate 119 B2 is, for example, of high concentration p-type dopant material (Fig. IE) due to the application of that material discussed supra.
  • the fifth dielectric layer 125A layer also covers vertical sidewalls of the select gate 119&2 and the storage device formed by the storage gate 119 B i, "he etched fourth dielectric layer 117B, and the floating gate 115B-
  • the fifth dielectric layer 125A may be selected from materials such as an oxynitride or OKO.
  • the plan view of Fig. IF has delineation rioting conformal ridges m the fifth dielectz ⁇ ic layer 155A of the oxynitride in thei exemplary embodiment of the present invention. i
  • a second spacer etch step removes the fifth dielectric layer 125A
  • a plurality of dielectric spabers 125B abut the sidewalls of the select gate 119m and the storage gate 119 B1 .
  • a high concentration n-typ ⁇ material is applied to the open regions of the. recessed first dielectric layer 103C in the present exemplary emfaodimerit .
  • the high concentration n-type material forms a plurality of implant regions 127.
  • the area of the select gate 119 S2 is masked with a patterned photoresist before the n+-type material is applied, thus no dopant material reaches a select gate ll9 B a.
  • the storage gate 119BI is left unmasked and exposed to the application of the high concentration n-type material.
  • the select gate 119 B3 is still composed of a high concentration p-type ⁇ nate ⁇ -ial and the storage gate 119Bl is composed of the high concentration n-type material.
  • the select gate 119 B 2 being high concentration p-type material with source/drain diffusions (i.e., the two implant regions 127 adjacent to the select gate 119 Bi ) of n+-type material , reduces the standby leakage current .
  • IA: - IH can be employed in advanced memory array design as described supra.
  • the specific exemplary embodiment demonstrates particular fabrication processes capable of producing a tunnel window with an aperture size significantly in excess of what photolithography is capable of ;(i.e., significantly smaller size) .
  • the prbsent exemplary embodiment is a fiabricati ⁇ n process Df a BEPROM storage cell with a recessed tunnel window.
  • the recessed tunnel window is produced with a spacer technique that allows a tunnel window of smaller dimensions and closer tolerances to adjacent features in a device channel. Together the smaller feature size and reduced tolerances produce a smaller storage cell size and a capability for the cell to be readily scalable.
  • the substrate itself may be comprised of a non- semiconducting material r for example, a quartz reticle with a deposited and doped polysilic ⁇ n layer.

Abstract

A present invention is a method, and resulting device, for fabricating memory cells with an extremely small area and reduced standby current. The small area is accomplished by a judicious use of spacers (109) which allows a tunnel window (113) of a storage device to be fabricated in close proximity to an associated select gate (11982) and with a reduced gate width (120) compared to typical devices. The tunnel window is recessed within an upper surface of a substrate (101). The tunnel window recess is made possible by selective etching of the substrate and oxides {103, 105, 107} covering the substrate. A substantial reduction in the size of a tunnel window means device scaling is possible far beyond what is attainable with standard photolithography. Standby current is reduced significantly by fabricating a select device with complementary material types for the gate compared with the adjacent source/drain regions.

Description

DESCRIPTION
MEMORY CELL WITH REDUCED SIZE AND STANDBY CURRENT
TECHNICAL FIELD
The invention relates to non-volatile memory cell and memory arrays and, in particular, to a compact architectural arrangement for fabrication of non-volatile memory devices with low standby current and a method of making same,
BACKGROUND ART i A non-volatile memory device retains data even after power to th,e device Is terminated, One particular type of non-volatile memory device i.s an electrically erasable programmable read only memory (EΞPROM) device. In an E3PROM devUce, programming and< erasing are accomplished by transferring electrons to and from a floating gate electrode through, a thin dielectric layer, known as a tunnel-oxide layer, located between the floating gate elactrode and an underlying substrate. Typically, electron transfer is carried out by either hot electron injection or by Fowler-Nordheim tunneling, In either electron transfer mechanism, a voltage is coupled to the floating gate electrode by a control gate electrode, also known as a programming region. The control gate electrode or programming region is capacitively coupiled to the floating gate electrode such that a yoltage applied to the programming region is coupled to the floating gate electrode.
A traditional ESPROM device utilizes the floating gate, in a field effect transistor structure, positioned, over tout insulated from a channel region in the semiconductor substrate, and between source and drain regions. A threshold voltage characteristic of the transistor is controlled by an amount of charge that is retained on the floating gate. Thus, a minimum amount of voltage (i.e., the threshold voltage) must be applied to the coirrol gate ibefore the transistor is turned "on, " thus permitting conduction between source and drain regions of the transistor. Conduction is controlled by the amount of charge on the floating gate . A memory transistor is programmed or erased to one of two states by transferring electrons from the substrate channel region, through a tunnel window constructed in the thin dielectric tunnel! layer and onto and from the floating gate . A state of the memory transistor is read by placing an operating voltage across the source and drain with an additional! voltage on the control gate of the memory transistor. A level of current flowing between the source and dr.ain is detected to determine whether the device is programmed to be "on" or "off" for a given control gate volt.age, A specific single memory transistor cell i-n a two-dimensional array of EEPROM memory cells is addressed for reading by (1) applying a source-drain volt-age to source and drain lines in a column containing the cell being addressed, and; (2) applying a contra! gate voltage to the control gates in a row containing the cell being addressed.
As discussed, EEPROM memory cells may be erased electrically. One way in which the cell is erased electrically is by transfer" of charge from the floating gate to the transistor drain through a thin tunnel dielectric layer.1 Charge transfer is again accomplished by applying appropriate voltages to the source, drain, and control gate of the floating gate transistor. An array of ΞSPROM cells is generally referred to as a Flash EEPROM array because an entire array of cells, or a significant group of cells, is erased simultaneously. As Plash EEPROM arrays become increasingly larger in terms of storage capacity, the semiconductor industry has attempted various ways of reducing a size of individual memory cells, and thus, reducing a size of the entire array. The size reduction however cannot impact reliability nor critical characteristics of the memory device such as standby current. The reduction in sise of individual memory cells means an overall reduction in the area of the memory array. With more devices available in a given area, it is critical that each device maintains as low a standby current as possible.
Traditionally, EEPROM cell size has been limited by the x-equired width of the active region, A primary limiting ;factor in determining the active region width is the size of the tunnel window. Traditionally, the tunnel window is defined by lithography which produces a limitation on a minimum aperture size for the tunnel window. The active area is required by process design rules to extend beyond this minimum aperture size. Consequently, this requirement determines a minimum width of the memory device conduction channel. To achieve a maximum of saturation current through the conduction channel, it is desirable to maximize the ratio of width to length of the ;memory device.
The lithographic limits in determining the minimum width of ithe tunnel window also determine a minimum width of (the memory device. With the width of the memory device determined, the length of the memory device is also determined. The constraints determined by the feature size of the tunnel window therefore produce a limitation on the scalability of the EEPROM cell and in turn limit the ability to minimize the memory cell si^e.
It would be desirable to achieve an enhancement to a tunnel window fabrication process which would further reduce the minimum aperture size of the tunnel diode window. A 'further reduction in the minimum feature size of the tunnel window directly affects the minimum features of a memory device. A further reduction in tunnel window size would enhance the scalability of the EEPROM memory cell. Additionally it would toe further desirable to achϋeve the reduction in minimal feature size while maintalining an extremely low standby current .
SUMMARY OF THE INVENTION The present invention is a1 method, and resulting device,: for fabricating memory cells with an extremely small area and low standby! current . The small area requirement ds met due primarily to two significant factors. First, :a judicious use of spacers, described in detail infra, allows a tunneling window to be fabricated with feature sizes less than comparable features produced by conventional 1'ithography. Using spacers, a tunneling- window may be fabricated with an aperture significantly smaller than the .limits set by optical photolithography. The low standby current requirement is met by two factors as we&l. First the scaling capability, besides offering areduced feature sizss, also means that an amount of standby current is reduced due to smaller device geometries. Secondly a devics width of a select gate of the memorJy device can be narrowed independent of the wid~h of the storage device. Th≥ work function, of the select gate i-s proportional to the standby current . Experimental evidence suggests an appropriate work function of the select gate produces a significantly lcwex- standby current .
In one exemplary embodiment, the present invention is a method of fabricating an electronic integrated circuit device on a first surface of a substrate (e.g., a silicon wafer) . The method includes forming a first dielectric layer, such as silicon dioxide (e.g., thermally or deposited) . At least one additional dielectric film Hayer is then formed over the first dielectric film llayer. An aperture is created and spacers are formed on sidewalls of the aperture. The spacers are produced such that a distance between spacers on opposing sidewalls of fchie aperture is less than a limit of optical photolithography. An injector dopant region is then formed withi.il the aperture created by the spacers and a portion of thie area immediately adjacent. The first dielectric film Layer and an upper portion of the substrate und≥rlying thie second aperture are etched and covered with a dielectr-ic layer, thus forming the tunneling window.,
BRIEF DESCRI PTION: OF THE DRAWINGS
Figs. IA - IH are; an exemplary embodliment of process steps employing a sspacer application and tunneling window fabrication technique used in the present invention.
DETAILED DESCRIPTION OF THB INVENTION With reference to Figs. IA - IE, advanced spacer fabrication techniques are described in detail. The spacer fabrication techinique is described with regard to a sinplxfied topology too clearly describe and define various process steps. Although the simplified topology is a variation of a topology actnially employed in the present invention, the simplified topology fabrication steps are described so as to more clearly describe the technique .
A cross-section A-A of Fig. IA includes a substrace 101, a first dielectric layer 103A, a second dielectric layer 105, and a third dielectric layer 107 in an exemplary embodiment of the present invention. The second dielectric layer 105 and the third dielectric layer 107 contain a first aperture 108. The substrate 101 may be comprised of various materials known in the semiconductor art . Such materials include silicon (or other group IV materials), compound semiconductors (e.g., compounds of elements, especially elements from periodic table groups IH-V and II-V1), quartz reticles, or other suitable materials.
In a specific exemplary embodiment, the substrate 10l is a p-type silicon wafer (or alternatively, a p-type well in a substrate) , The first dielectric layer 103A is a silicon dioxide layer and may be formed by a thermal oxidation technique or alternatively may be deposited by any of a variety of techniques such as atomic layer deposition (ALD) , chemical vapor deposition (CVD) , low-pressure CVD
(LPCVD) , plasma-enhanced CVD (PECVD) , or plasma-assisted CVD (PACVD) . In this specific exemplary embodiment, the second dielectric layer 105 and tliird dielectric layer 107 are substantially comprised of silicon nitride and TEOS oxide { tetra-ethoxysilane or tehraethyl orthosilicate) respectively. i
A selective etchant, such as a highly selective dry etch or wet chemical etch is chosen to etch the third dielectric layer 107 and the second dielectric layer 105, thus forming a first aperture 10S. Etching of underlying layers can occur through various wet-etch techniques (e.g., the first dielectric layer 103A may be etched in hydrofluoric acid, such as contained in a standard buffered oxide etch (BOE) , or orthophosphoric acid) or dry etch techniques (e.g., reactive-ion -etching (RIE)) . A skilled artisan will recognize that various chemistries may be chosen which will readily etch, for example, a polysilicon layer while leaving a nitride layer essentially intact (or vice versa) or etch a nitride layer while leaving a silicon dioxide layer intact {or vice versa) . Therefore, etches of one layex" may be performed while leaving adjacent layers intact while avoiding tedious and critical timing! steps . Layers comprised of materials dissimilar to the layer being etched thus serve as an etch stop. Such etching techniques are known in the semiconductor- art. In this exemplary embodiment, one or more selective etchants are chosen such that there is a high selectivity of etch rate between the second and third dielecciric layers 105, 107 and the underlying first dielectric layer 103A. Therefore, due co the selectivity of the etchant itself there is no need for critical timingi as the first dielectric layer :1Q3A acts as an etch stop for the second and third dielectric layers 105, 107. This selective etch capability is used to produce the first aperture 108 and similar techniques are used in subsequent process steps . A blanket dielectric spacer layer (not shown) is formed for example, by CVD or LPCVD techniques. In a specific exemplary embodiment, the dielectric spacer- layer is chosen to be chemically dissimilar to the underlying etched third dielectric layer 107. For example, if the etched third dielectric layer 107 is chosen to i?e TEOS oxide, then the dielectric spacer layer may be chosen to be silicon nitride, In this way, an etchant which is selective between silicon dioxide and silicon nirride allows the etched third dielectric (e.g., TEOS oxide) layer 107 to act as an etch stop for etching a dielectric spacer 109 from the spacer dielectric (e.g., silicon nitride) .layer. This first spacer etch step is exemplified with reference to both the plan view and a cross -sectional view A-A of Fig, IA. In a case where dissimilar materials are used for the etched third dielectric layer 107 and the spacer dielectr-ic layer, a dielectric spacer 109 is formed on the first aperture sidewalls by a selecti"/e etchant. The selective etchant is used to etch the dielectric spacer 109 without substantially affecting an integrity of any other layer.
Etching of the spacer layeϊr is performed such that substantiality all horizontal surfaces- (i.e., those paralie_ to the face of the substrate) are etched while leaving surfaces cthat are essentially vertical substantially intact. The resulting: width of the dielectric spacert 109 is essentially the thickness of the spacer dielectric layer deposited before selective etching. In the present exemplary embodiment the dielectric spacert 109 is a thickness; of 500Af a thickness of the second dielectric (i_.e., a step thickness) is IOOOA, ind a thickness of the first dielectric layer 103A is lOG-JOOA, Such- etches, ais those of the spacer dielectric layer,t are accomplished by, for example, a reactiv"* ion etch. The plan view of! Fig- IA indicates both a size of trs second aperture through the spacer layer and visible layers. The layers visible at this stage of fabrication are the patterned dielectric spacer 109, the third dielectric layer 107, and the substrate 101. Generally, typical photolithographic techniques are limited by physical constraints of the photolithographic system involving actinic radiation wavelength, λ, and geometrical configurations of the projection system optics. According to Kayleigh's criterion,
0. δlλ
Lτ
NA
where NA is the numerical aperture of the optical system and is defined as NA = nsinα, where n is the index of refraction of the medium which the radiation traverses
(usually air for this application, sb n = 1} and α is a half-angle of divergence of the actinic x'adiation. For example, using deep ultraviolet (DUV) illumination with λ=193 ran, and NA = 0.7, the lower limit of resolution is 168 nanometers (1680 A) . Techniques such as phase- shifted masks can extend this limit downward, but photomasks required employing this technique are extremely expensive. This expense becomes greatly compounded with a realisation that an advanced semiconductor process may employ mors than 25 photomasks.
A "width" of the dielectric spacer 109 is dependent upon a .thickness of the deposited spacer layer and a step height; of a proximate structure; the dielectric spacer! 109 is approximately 0.7 - t, where is the thickness of the combined thicknesses of the etched second and third dielectric layers 105, 107. Thus, the width at the spacers and, consequently any underlying features, may be fabricated to be extremely small. Therefore, the fabrication method described herein, and. a device resulting from employing the method, may have, components that are formed below a limit of resolution of optical photolithography by utilizing spacers to separate laterally displaced features {i.e., features that have spatial dimensioπis less than the limit of resolution in planes parallel to a face of a substrate or wafer, or "x-y" dimensions) * i The plan view of Fig. IA indicates how the dielectric spaced 109 can significantly reduce a size of an aperture. For example, compare a, size of the first aperture 108 opening onto the third dielectric layer 107 with a size of the second aperture now open to the substrate 101, If the first aperture 108 were at the limit of resolution for a particular photolithographic stepper, in this case, 0.18 μm, a.nd the thickness of the spacer dielectric layer was 100 nm (i.e., 0,10 μm) , then the aperture sise "S" between the spacers 109 on opposing sidewalls of the original aperture (i.e., the aperture opening onto the substrate 101) is !
S = 0.18 μm - [2 {θ.7(θ.lθ μπ)}]
S ^ 0.04 μm
Thus, the second aperture formed by the dielectric spaceris 109 may be significantly less than the limit of resolution of the stepper. ; An additional benefit is that ai select transistor width can also be scaled down to a minimum size, thus ;<eeping current through the devide minimized while enabling further scaling capabilities. Further elaboration on a difference in a select gate width versus a storage gate width is discussed infra.
With, reference to cross- section B-B of Fig. IB, in the present exemplary embodiment, the first dielectric layer 103A is etched to form an etched first dielectric layer 103B and an etch aperture 110 exposing a portion of the substrate 101. The second aperture formed by the dielectric spacer 109 (Fig, IA) is used to perform a selective etch on the first dielectric layer 103A to form the etched first 'dielectric layer 103B and Che etch aperture 110. After the etch aperture 110 is formed by the selective etch, the third dielectric layer 107, the second dielectric layer 105, and the dielectric spacers
109 are removed by a sequence of the etchants such as those mentioned supra.
With reference to the plan view of Fig. IB, the size of the etch .aperture 110 formed by the dielectric spacer exposes a portion of the substrate IQl. A relative indication of the small size of the etch aperture 110 is demonstrated.
With reference to cross- section C-C of Fig. 1C, in the present exemplary embodiment, the substrate 101 is selectiyely etched to produce an etched substrate recess 113. To produce /the etcheci substrate recess 113 the substrate 101 is iover etched, through the etch aperture
110 (Pig. IB) , tec a depth of about 2G0-3Q0A below an uppermost surface of the etched first dielectric layer 103A. A size of the etcheci substrate recess 113 is roughly the size pf the second aperture formed by the dielectric spacer! 109. The dielectric spacer 109 thus serves as an etch mask. Tϊie dielectric spacer 109 also serves ;o limit an area for; a subsequent dopant step, thereby forming an injector; dopant region 111. The injector dopant region ill may be formed by processes known to a skilled artisan and include techniques such as diffusion and ion implantation. The injector dopant region ill, per the present exemplary embodiment, is made by doping a localized area (e.g., through injector ion implantation) creating a subsurface highly-doped region for i-eeeiving bias from a nearby contact for charge generation, i.e., a tunneling injector.
With reference to the plan view of Fig. 1C, a small feature size of the etched substrate recess 113 is carried through to a recessed first dielectric layer 103C with a thin oxide grown osrer the etcned substrate recess 113. The thin oxide is, for example, the same material as the etched first dielectric layer IQBB. With reference to cross-section D-D of Fig. ID, in the present exemplary embodiment, an initial floating gate 115A and an initial etched fortn dialectic layer 117A are fabricated on the recessed first dieLectric layer 103C above /the etched substrata recess 1,13 and the injector dopant region 111 so as to form a floating gate portion of a storage device. Fabrication of the initial floating gate 115A and the initial etched fourrth dielectric layer I117A commences withi a first semiconductor layer (not shown) being deposited across the first surface of the substrate IDl. A subsequent deposition of a flourth dielectric layer (not shown) is applied on top of the first dielectric layer 1.03B. The first semiconductor layer and the fcurth dielectric layer are etched to form the initial floating gate 1.15ft. and the initial etched fcurth dielectric laylsr 117A wi,th a non- critical gate length 118. The first semiconduictor layer, in the present exemplary embodiment ,ι is a highi concentration n-tiype polysilicon material . Wi-th reference to the plan view of Fig. ID, the initial etched fourth dielectric layer 117A is situated atop the initial floating gate 115A and the recessed first dielectric layer 103C. With reference to cross -section E-S of Fig, IE, in the present exemplary embodiment a second semiconductor layer 119A is deposited in a conformal layer across the upper surface of the recessed first dielectric layer 103C which covers the initial floating gate 115A and the initial etched fourth dielectric layer 117A. In the present exemplary embodiment the second semiconductor layer 119A is an undoped polysilicon material. A photoresist material is deposited on top of the second semiconductor layer 119A and is processed to form a patterned photoresist layer 121,
In the plan view of Fig. IE, the patterning of the patterned photoresist layer 121 produces a select gate region 123 in close proximity to the floating gate portion (i.e., the initial floating gate 115A and the initial etched fourth dielectric layer 117A) of the storage device (Fig. ID) . A high concentration of p-type dopant material is applied at the select gate implant region 123 and into the exposed second semiconductor layer 1L9A. A skulled artisan would readily consider an ion implantation technique for injecting the dopant at the select gate implant region 123 or other effective means for application of thie high concentration p-type dopant naterial .
With reference to cross-section F-F of Fig. IF, in the present exemplary embodiment , a fifth dielectric layer 125A is deposited in a conformal layer across an tipper surface of the recessed first dielectric layer 1Q3C and over a storage gate 119Bi and a select gate 119B2. From a 311st prior set of patterning and lithographic steps {not shown) a final etched structure of a floating gate 115B and an etched fourth dielectric layer 117B with a final gate length 120 is produced. The final gate length 120 dimension is less than the non-critical gate length 118 (Fig. ID).
The second semiconductor layer 119A (Fig. IE) is selectively patterned with photoresist and selectively etched (not shown) to form the storage gate 119Bi and the select gate 2.19B≤, The select gate 119B2 is, for example, of high concentration p-type dopant material (Fig. IE) due to the application of that material discussed supra. The fifth dielectric layer 125A layer also covers vertical sidewalls of the select gate 119&2 and the storage device formed by the storage gate 119Bi, "he etched fourth dielectric layer 117B, and the floating gate 115B- The fifth dielectric layer 125A may be selected from materials such as an oxynitride or OKO. The plan view of Fig. IF has delineation rioting conformal ridges m the fifth dielectz~ic layer 155A of the oxynitride in thei exemplary embodiment of the present invention. i
With reference to cross- section G-G of Fig. IG, in the present specific exemplary embodiment a second spacer etch step removes the fifth dielectric layer 125A
(for example, oxynitride) from essentially all horizontal surfaces. The spacer etching is achieved without substantially affHCting an integrity of any other layer. With reference to: the plan view of Fig. IG, a plurality of dielectric spabers 125B abut the sidewalls of the select gate 119m and the storage gate 119B1.
Wi th reference to cross-section H-H of Fig. IH, a high concentration n-typβ material is applied to the open regions of the. recessed first dielectric layer 103C in the present exemplary emfaodimerit . The high concentration n-type material forms a plurality of implant regions 127. Additionally the area of the select gate 119S2 is masked with a patterned photoresist before the n+-type material is applied, thus no dopant material reaches a select gate ll9Ba. The storage gate 119BI is left unmasked and exposed to the application of the high concentration n-type material. Aftear application of the high concentration n-type material, the select gate 119B3 is still composed of a high concentration p-type τnateχ-ial and the storage gate 119Bl is composed of the high concentration n-type material. The select gate 119B2 being high concentration p-type material with source/drain diffusions (i.e., the two implant regions 127 adjacent to the select gate 119Bi) of n+-type material , reduces the standby leakage current . The source/drain diffusions of n+-tγpe rniaterial and the select gate 119B2 of p+-type material; (in contrast to a typical NMOS device having a select gate of n+--type material) adjusts the work function between the regions to cause the reduction in the standby leakage current ,
The fabrication processes employed and described with reference to Figs . IA: - IH can be employed in advanced memory array design as described supra.
While various setr.iconductor fabrication and processing techniques may be used to accomplish a similar' result, the specific exemplary embodiment demonstrates particular fabrication processes capable of producing a tunnel window with an aperture size significantly in excess of what photolithography is capable of ;(i.e., significantly smaller size) . Additionally, the prbsent exemplary embodiment is a fiabricatiαn process Df a BEPROM storage cell with a recessed tunnel window. The recessed tunnel window is produced with a spacer technique that allows a tunnel window of smaller dimensions and closer tolerances to adjacent features in a device channel. Together the smaller feature size and reduced tolerances produce a smaller storage cell size and a capability for the cell to be readily scalable.
In the foregoing specification, the present invention has been described with reference to specific embodiments thereof. It will, however, be evident to a skilled artisan that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. , For example, skilled artisans will appreciate that other types of semiconducting and insulating materials other than those listed may be employed. Additional particular process fabrication and deposition techniques, such as low pressure chemical vapor deposition (LPCVD), ultra -high vacuum CVD (UHCVD), and low pressure .tetra-ethoxysilane (LPTEOS) may be readily employed for various layers and still be within the scope of the present invention. Although the exemplary embodiments describe pax-ticular types of dielectric and semiconductor materials, one skilled in the art will realise that other types of materials and arrangements of materials may also be effectively utilized and achieve the same or similar advantages. Also, the substrate itself may be comprised of a non- semiconducting material r for example, a quartz reticle with a deposited and doped polysilicσn layer.
Additionally, although the exemplary embodiments are described in terms of an EEPROM memory cell integrated circuit device, ai person of ordinary skill in the art will recognize that other integrated circuit devices may readily benefit from the fabrication process described herein as well. The specification and drawings are, accordingly, to be regarded in an. illustrative rather than a restrictive sense.

Claims

ClaimsWhat xs claimed is:
1. A method of fabricating an electronic integrated circuit device on a first surface of a substrate, comprising : forming a first dielectric film layer over the first surface of the substrate,- forming an at least one further dielectric film layer- over the first dielectric and creating a first aperture in the at least one further dielectric film layer, the first aperture having sidewalis that are non- parallel to the first surface of the substrate; forming spacers on the sidewalis of the first aperture such tha:t a distance between spacers on opposing sidewalis of the ϊirst aperture is less than a limit of optical photolithography, the opposing spacers thus forming a second aperture; creating a dopant region formed substantially within an upper portion of the substrate underlying the first aperture ; and i etching a po.rti.on of the first dielectric film layer and an upper portion of the first surface of the substrate underlying the second apermre thus forming a tunneling window.-
2. The method of. claim 1, wherein t.ie dopant region is formed by ion implantation.
3. The method of: claim 1, wherein t.ne dopant region is formed by diffusing a dopant species..
4. The method of claim 1, wherein the step of forming spacers on the sidewalls of the first aperture comprises: forming a spacer dielectric film layer over the at least one further dielectric film layer and a portion of the first dielectric film layer underlying the first aperture; and etching regions of the spacer dielectric film layer that are essentially parallel to the first surface of the substrate while leaving regions of the spacer dielectric film layer that are essentially perpendicular to the first surface of the substrate., thus creating spacers.
5. The method of claim 4, wherein the step of etching regions of the spacer dielectric film layer is performed by a reactive ion etch (RIE) .
6. The method of claim 4, wherein the spacer dielectric film is chosen such that a chemical etching property of the spacer dielectric film layer is dissimilar to a chemical etching property of the first dielectric film.
7. The method of claim l, wherein the substrate is substantially comprised o£ a p-type silicon wafer.
8. A memory device, comprising: a floating gate forming a portion of the storage device, the floating gate being comprised substantially of a first semiconducting material and being constructed over a substrate; a gate dielectric material interposed between the floating gate and: a first surface of the substrate; a tunneling window etched in an upper portion of the first surface of the substrate to form a recess, the gate dielectric material and the floating gate conforming to the recess forming the tunneling window; and an injector dopant region disposed in close relationship to the tunneling window and underlying a portion of the floating gate.
9. The memory device of claim S, wherein the substrate is comprised substantially of p-type. silicon.
10. The memory device of claim 8, wherein the gate dielectric material is comprised substantially of silicon dioxide .
11. The storage device of claim 8, wherein a related select device is fabricated with a select gate of a second semiconducting material and with a plurality of source/drain regions adjacent to the select gate, the select gate produced with a high concentration, of a first dopant material and the plurality of source/drain regions produced with a high concentration of a second dopant, material ,
12. The storage device of claim 11, wherein che first dopant naterial and the second dopant material are of complementary material types .
13. The storage device of claim 11, wherein the first dopant naterial is a high- concentration p-type dopant and the second dopant is a high-concentration n-type dopant.
PCT/US2007/064952 2006-04-06 2007-03-26 Memory cell with reduced size and standby current WO2007117977A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/399,137 US7253057B1 (en) 2006-04-06 2006-04-06 Memory cell with reduced size and standby current
US11/399,137 2006-04-06

Publications (2)

Publication Number Publication Date
WO2007117977A2 true WO2007117977A2 (en) 2007-10-18
WO2007117977A3 WO2007117977A3 (en) 2008-10-30

Family

ID=38324315

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/064952 WO2007117977A2 (en) 2006-04-06 2007-03-26 Memory cell with reduced size and standby current

Country Status (3)

Country Link
US (2) US7253057B1 (en)
TW (1) TW200807640A (en)
WO (1) WO2007117977A2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5998512B2 (en) * 2012-02-16 2016-09-28 ローム株式会社 Semiconductor device and manufacturing method of semiconductor device
FR3012672B1 (en) 2013-10-31 2017-04-14 Stmicroelectronics Rousset MEMORY CELL COMPRISING NON-SELF-ALIGNED HORIZONTAL AND VERTICAL CONTROL GRIDS
CN104810370B (en) 2014-01-26 2018-04-13 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method and electronic device
FR3017746B1 (en) 2014-02-18 2016-05-27 Stmicroelectronics Rousset VERTICAL MEMORY CELL HAVING NON-SELF-ALIGNED FLOATING DRAIN-SOURCE IMPLANT
CN105514107B (en) * 2014-09-22 2018-07-24 中芯国际集成电路制造(上海)有限公司 Nonvolatile memory and preparation method thereof
CN114551452A (en) * 2016-10-21 2022-05-27 联华电子股份有限公司 Single-layer polysilicon electronic erasing type rewritable read-only memory

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5516713A (en) * 1994-09-06 1996-05-14 United Microelectronics Corporation Method of making high coupling ratio NAND type flash memory
US5756385A (en) * 1994-03-30 1998-05-26 Sandisk Corporation Dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers
US6506646B1 (en) * 2000-01-25 2003-01-14 Oki Electric Industry Co., Ltd. Method for manufacturing a semiconductor memory
US6579808B2 (en) * 2001-10-15 2003-06-17 Hynix Semiconductor Inc. Method of fabricating a semiconductor device
US7205197B2 (en) * 2005-02-16 2007-04-17 Oki Electric Industry Co., Ltd. Method of fabricating a nonvolatile semiconductor memory

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH081933B2 (en) * 1989-12-11 1996-01-10 株式会社東芝 Nonvolatile semiconductor memory device
US7071060B1 (en) 1996-02-28 2006-07-04 Sandisk Corporation EEPROM with split gate source side infection with sidewall spacers
US5712180A (en) 1992-01-14 1998-01-27 Sundisk Corporation EEPROM with split gate source side injection
US5313421A (en) 1992-01-14 1994-05-17 Sundisk Corporation EEPROM with split gate source side injection
US5972752A (en) * 1997-12-29 1999-10-26 United Semiconductor Corp. Method of manufacturing a flash memory cell having a tunnel oxide with a long narrow top profile
EP1172856A1 (en) * 2000-07-03 2002-01-16 Matsushita Electric Industrial Co., Ltd. Nonvolatile semiconductor memory device and method for fabricating the same
KR20040061616A (en) * 2002-12-31 2004-07-07 동부전자 주식회사 method for manufacturing a non-voltage memory device
US7132329B1 (en) * 2005-06-29 2006-11-07 Freescale Semiconductor, Inc. Source side injection storage device with spacer gates and method therefor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5756385A (en) * 1994-03-30 1998-05-26 Sandisk Corporation Dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers
US5516713A (en) * 1994-09-06 1996-05-14 United Microelectronics Corporation Method of making high coupling ratio NAND type flash memory
US6506646B1 (en) * 2000-01-25 2003-01-14 Oki Electric Industry Co., Ltd. Method for manufacturing a semiconductor memory
US6579808B2 (en) * 2001-10-15 2003-06-17 Hynix Semiconductor Inc. Method of fabricating a semiconductor device
US7205197B2 (en) * 2005-02-16 2007-04-17 Oki Electric Industry Co., Ltd. Method of fabricating a nonvolatile semiconductor memory

Also Published As

Publication number Publication date
WO2007117977A3 (en) 2008-10-30
US20070257298A1 (en) 2007-11-08
TW200807640A (en) 2008-02-01
US7253057B1 (en) 2007-08-07

Similar Documents

Publication Publication Date Title
US5495441A (en) Split-gate flash memory cell
US6372617B1 (en) Method of manufacturing non-volatile memory
KR100669864B1 (en) Method for manufacturing a non-volatile memory device
US6720611B2 (en) Fabrication method for flash memory
KR100201451B1 (en) Nonvolatile memory device
WO2007117977A2 (en) Memory cell with reduced size and standby current
US6590253B2 (en) Memory cell with self-aligned floating gate and separate select gate, and fabrication process
US6306708B1 (en) Fabrication method for an electrically erasable programmable read only memory
KR20050007373A (en) Ultra small thin windows in floating gate transistors defined by lost nitride spacers
KR20030088826A (en) Split-gate memory device and fabricating method thereof
US5750428A (en) Self-aligned non-volatile process with differentially grown gate oxide thickness
US7491998B2 (en) One time programmable memory and the manufacturing method thereof
KR100852236B1 (en) Eeprom device and method of manufacturing the eeprom device
JP2004228575A (en) Eeprom cell and manufacturing method for the same
KR100672718B1 (en) A flash memory and a method for fabricating the same
KR100467816B1 (en) Flash memory with low operation voltage and manufacturing method thereof
US7682894B2 (en) Flash memory and a method of manufacturing the same
US6924199B2 (en) Method to form flash memory with very narrow polysilicon spacing
KR20020045434A (en) Method for fabricating split gate type flash memory device
US20070235797A1 (en) Process for reducing a size of a compact EEPROM device
KR100202115B1 (en) The method of starter for culturing mushroom
US20080157170A1 (en) Eeprom cell with adjustable barrier in the tunnel window region
KR20040064926A (en) Cell structure of EPROM device and fabrication thereof
KR100201813B1 (en) Breaking curcuit and method of duble control in exchange system
KR100279001B1 (en) Manufacturing Method of Flash Memory Cell

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07759404

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
122 Ep: pct application non-entry in european phase

Ref document number: 07759404

Country of ref document: EP

Kind code of ref document: A2

DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)