WO2007117977A3 - Memory cell with reduced size and standby current - Google Patents
Memory cell with reduced size and standby current Download PDFInfo
- Publication number
- WO2007117977A3 WO2007117977A3 PCT/US2007/064952 US2007064952W WO2007117977A3 WO 2007117977 A3 WO2007117977 A3 WO 2007117977A3 US 2007064952 W US2007064952 W US 2007064952W WO 2007117977 A3 WO2007117977 A3 WO 2007117977A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- tunnel window
- standby current
- substrate
- reduced
- gate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/947—Subphotolithographic processing
Abstract
A present invention is a method, and resulting device, for fabricating memory cells with an extremely small area and reduced standby current. The small area is accomplished by a judicious use of spacers (109) which allows a tunnel window (113) of a storage device to be fabricated in close proximity to an associated select gate (11982) and with a reduced gate width (120) compared to typical devices. The tunnel window is recessed within an upper surface of a substrate (101). The tunnel window recess is made possible by selective etching of the substrate and oxides {103, 105, 107} covering the substrate. A substantial reduction in the size of a tunnel window means device scaling is possible far beyond what is attainable with standard photolithography. Standby current is reduced significantly by fabricating a select device with complementary material types for the gate compared with the adjacent source/drain regions.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/399,137 US7253057B1 (en) | 2006-04-06 | 2006-04-06 | Memory cell with reduced size and standby current |
US11/399,137 | 2006-04-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2007117977A2 WO2007117977A2 (en) | 2007-10-18 |
WO2007117977A3 true WO2007117977A3 (en) | 2008-10-30 |
Family
ID=38324315
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/064952 WO2007117977A2 (en) | 2006-04-06 | 2007-03-26 | Memory cell with reduced size and standby current |
Country Status (3)
Country | Link |
---|---|
US (2) | US7253057B1 (en) |
TW (1) | TW200807640A (en) |
WO (1) | WO2007117977A2 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5998512B2 (en) * | 2012-02-16 | 2016-09-28 | ローム株式会社 | Semiconductor device and manufacturing method of semiconductor device |
FR3012672B1 (en) | 2013-10-31 | 2017-04-14 | Stmicroelectronics Rousset | MEMORY CELL COMPRISING NON-SELF-ALIGNED HORIZONTAL AND VERTICAL CONTROL GRIDS |
CN104810370B (en) | 2014-01-26 | 2018-04-13 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method and electronic device |
FR3017746B1 (en) | 2014-02-18 | 2016-05-27 | Stmicroelectronics Rousset | VERTICAL MEMORY CELL HAVING NON-SELF-ALIGNED FLOATING DRAIN-SOURCE IMPLANT |
CN105514107B (en) * | 2014-09-22 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | Nonvolatile memory and preparation method thereof |
CN107978601B (en) * | 2016-10-21 | 2022-02-22 | 联华电子股份有限公司 | Single-layer polysilicon electronic erasing type rewritable read-only memory |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5516713A (en) * | 1994-09-06 | 1996-05-14 | United Microelectronics Corporation | Method of making high coupling ratio NAND type flash memory |
US5756385A (en) * | 1994-03-30 | 1998-05-26 | Sandisk Corporation | Dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers |
US6506646B1 (en) * | 2000-01-25 | 2003-01-14 | Oki Electric Industry Co., Ltd. | Method for manufacturing a semiconductor memory |
US6579808B2 (en) * | 2001-10-15 | 2003-06-17 | Hynix Semiconductor Inc. | Method of fabricating a semiconductor device |
US7205197B2 (en) * | 2005-02-16 | 2007-04-17 | Oki Electric Industry Co., Ltd. | Method of fabricating a nonvolatile semiconductor memory |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH081933B2 (en) * | 1989-12-11 | 1996-01-10 | 株式会社東芝 | Nonvolatile semiconductor memory device |
US7071060B1 (en) | 1996-02-28 | 2006-07-04 | Sandisk Corporation | EEPROM with split gate source side infection with sidewall spacers |
US5313421A (en) | 1992-01-14 | 1994-05-17 | Sundisk Corporation | EEPROM with split gate source side injection |
US5712180A (en) | 1992-01-14 | 1998-01-27 | Sundisk Corporation | EEPROM with split gate source side injection |
US5972752A (en) * | 1997-12-29 | 1999-10-26 | United Semiconductor Corp. | Method of manufacturing a flash memory cell having a tunnel oxide with a long narrow top profile |
EP1172856A1 (en) * | 2000-07-03 | 2002-01-16 | Matsushita Electric Industrial Co., Ltd. | Nonvolatile semiconductor memory device and method for fabricating the same |
KR20040061616A (en) * | 2002-12-31 | 2004-07-07 | 동부전자 주식회사 | method for manufacturing a non-voltage memory device |
US7132329B1 (en) * | 2005-06-29 | 2006-11-07 | Freescale Semiconductor, Inc. | Source side injection storage device with spacer gates and method therefor |
-
2006
- 2006-04-06 US US11/399,137 patent/US7253057B1/en active Active
-
2007
- 2007-03-26 WO PCT/US2007/064952 patent/WO2007117977A2/en active Search and Examination
- 2007-04-02 TW TW096111630A patent/TW200807640A/en unknown
- 2007-07-13 US US11/777,498 patent/US20070257298A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5756385A (en) * | 1994-03-30 | 1998-05-26 | Sandisk Corporation | Dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers |
US5516713A (en) * | 1994-09-06 | 1996-05-14 | United Microelectronics Corporation | Method of making high coupling ratio NAND type flash memory |
US6506646B1 (en) * | 2000-01-25 | 2003-01-14 | Oki Electric Industry Co., Ltd. | Method for manufacturing a semiconductor memory |
US6579808B2 (en) * | 2001-10-15 | 2003-06-17 | Hynix Semiconductor Inc. | Method of fabricating a semiconductor device |
US7205197B2 (en) * | 2005-02-16 | 2007-04-17 | Oki Electric Industry Co., Ltd. | Method of fabricating a nonvolatile semiconductor memory |
Also Published As
Publication number | Publication date |
---|---|
US20070257298A1 (en) | 2007-11-08 |
WO2007117977A2 (en) | 2007-10-18 |
US7253057B1 (en) | 2007-08-07 |
TW200807640A (en) | 2008-02-01 |
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