WO2007129293A3 - Corruption-resistant data porting with multiple error correction schemes - Google Patents
Corruption-resistant data porting with multiple error correction schemes Download PDFInfo
- Publication number
- WO2007129293A3 WO2007129293A3 PCT/IL2006/001249 IL2006001249W WO2007129293A3 WO 2007129293 A3 WO2007129293 A3 WO 2007129293A3 IL 2006001249 W IL2006001249 W IL 2006001249W WO 2007129293 A3 WO2007129293 A3 WO 2007129293A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- corruption
- error correction
- multiple error
- correction schemes
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
Abstract
To export (e.g. store or transmit)(50) input data, only the input data are encoded (34) separately according to first and second encoding schemes (30) tp rovide first and second encoded data. The first encoded data and the second encoded data data are exported (48). Upon importimg (e.g., retriving or receiving) representations of the exported data, a first decoding scheme is applied to the representation of the first encoded data to recover the input data (42). If that application fails, then a second decoding scheme is applied to the representation of the second encoded data to recover the input data.
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US74689106P | 2006-05-10 | 2006-05-10 | |
US60/746,891 | 2006-05-10 | ||
US11/505,798 | 2006-08-18 | ||
US11/505,798 US7823043B2 (en) | 2006-05-10 | 2006-08-18 | Corruption-resistant data porting with multiple error correction schemes |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2007129293A2 WO2007129293A2 (en) | 2007-11-15 |
WO2007129293A3 true WO2007129293A3 (en) | 2009-04-09 |
Family
ID=38668161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IL2006/001249 WO2007129293A2 (en) | 2006-05-10 | 2006-10-30 | Corruption-resistant data porting with multiple error correction schemes |
Country Status (3)
Country | Link |
---|---|
US (1) | US7823043B2 (en) |
KR (1) | KR20090015927A (en) |
WO (1) | WO2007129293A2 (en) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8209580B1 (en) | 2006-05-08 | 2012-06-26 | Marvell International Ltd. | Error correction coding for varying signal-to-noise ratio channels |
US7685494B1 (en) | 2006-05-08 | 2010-03-23 | Marvell International, Ltd. | Error correction coding for varying signal-to-noise ratio channels |
US8042029B2 (en) | 2006-05-21 | 2011-10-18 | Ramot At Tel Aviv University Ltd. | Error correction decoding by trial and error |
KR100872186B1 (en) * | 2007-01-04 | 2008-12-09 | 삼성전자주식회사 | Hybrid flash memory device with different error control scheme and memory system includign the same |
US7975209B2 (en) * | 2007-03-31 | 2011-07-05 | Sandisk Technologies Inc. | Non-volatile memory with guided simulated annealing error correction control |
US7966546B2 (en) * | 2007-03-31 | 2011-06-21 | Sandisk Technologies Inc. | Non-volatile memory with soft bit data transmission for error correction control |
US7966550B2 (en) * | 2007-03-31 | 2011-06-21 | Sandisk Technologies Inc. | Soft bit data transmission for error correction control in non-volatile memory |
US7971127B2 (en) * | 2007-03-31 | 2011-06-28 | Sandisk Technologies Inc. | Guided simulated annealing in non-volatile memory error correction control |
US8301979B2 (en) * | 2008-10-07 | 2012-10-30 | Sandisk Il Ltd. | Low density parity code (LDPC) decoding for memory with multiple log likelihood ratio (LLR) decoders |
JP5638956B2 (en) * | 2008-10-23 | 2014-12-10 | パナソニック インテレクチュアル プロパティ コーポレーション オブアメリカPanasonic Intellectual Property Corporation of America | Wireless transmission device, wireless reception device, encoded data transmission method, and encoded data reception method |
KR20100104840A (en) * | 2009-03-19 | 2010-09-29 | 삼성전자주식회사 | Semiconductor memory device that addition ecc is possible according to cell pattern, electronic system there-of |
US8650437B2 (en) * | 2010-06-29 | 2014-02-11 | International Business Machines Corporation | Computer system and method of protection for the system's marking store |
US8756473B1 (en) * | 2010-12-23 | 2014-06-17 | Sk Hynix Memory Solutions Inc. | Solid state device coding architecture for chipkill and endurance improvement |
US8812939B2 (en) * | 2011-01-28 | 2014-08-19 | Marvell World Trade Ltd. | Soft decoding systems and methods for flash based memory systems |
US8788922B2 (en) * | 2011-02-28 | 2014-07-22 | Apple Inc | Error correction codes for incremental redundancy |
US9032269B2 (en) | 2011-07-22 | 2015-05-12 | Sandisk Technologies Inc. | Systems and methods of storing data |
US8645789B2 (en) | 2011-12-22 | 2014-02-04 | Sandisk Technologies Inc. | Multi-phase ECC encoding using algebraic codes |
US8719677B2 (en) | 2011-12-22 | 2014-05-06 | Sandisk Technologies Inc. | Using ECC encoding to verify an ECC decode operation |
US8918705B1 (en) | 2012-01-11 | 2014-12-23 | Sk Hynix Memory Solutions Inc. | Error recovery by modifying soft information |
US9183095B1 (en) | 2013-06-28 | 2015-11-10 | Sk Hynix Memory Solutions Inc. | Recovering from a program failure by combining write data |
KR102305095B1 (en) | 2015-04-13 | 2021-09-24 | 삼성전자주식회사 | Method for operating non-volatile memory controller |
US9984771B2 (en) * | 2016-01-11 | 2018-05-29 | Sandisk Technologies Llc | Multi-level raid-type encoding with random correction capability |
US9940194B2 (en) | 2016-03-04 | 2018-04-10 | Sandisk Technologies Llc | ECC decoding using raid-type parity |
US10536172B2 (en) | 2016-03-04 | 2020-01-14 | Western Digital Technologies, Inc. | ECC and raid-type decoding |
US9959168B2 (en) | 2016-03-04 | 2018-05-01 | Sandisk Technologies Llc | ECC and RAID-type decoding |
US10374639B2 (en) | 2016-12-06 | 2019-08-06 | Western Digital Technologies, Inc. | Adaptive bit-flipping decoder based on dynamic error information |
US10158380B2 (en) | 2016-12-06 | 2018-12-18 | Sandisk Technologies Llc | ECC and read adjustment based on dynamic memory error model estimation |
US10284233B2 (en) * | 2016-12-06 | 2019-05-07 | Western Digital Technologies, Inc. | ECC adjustment based on dynamic error information |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030061558A1 (en) * | 2001-09-25 | 2003-03-27 | Fackenthal Richard E. | Double error correcting code system |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4712215A (en) | 1985-12-02 | 1987-12-08 | Advanced Micro Devices, Inc. | CRC calculation machine for separate calculation of checkbits for the header packet and data packet |
US5404485A (en) | 1993-03-08 | 1995-04-04 | M-Systems Flash Disk Pioneers Ltd. | Flash file system |
US6041001A (en) * | 1999-02-25 | 2000-03-21 | Lexar Media, Inc. | Method of increasing data reliability of a flash memory device without compromising compatibility |
GB2370477B (en) | 2000-12-22 | 2004-03-03 | Tandberg Television Asa | Method and apparatus for encoding a product code |
US20040015771A1 (en) | 2002-07-16 | 2004-01-22 | Menahem Lasser | Error correction for non-volatile memory |
US7162678B2 (en) * | 2003-03-14 | 2007-01-09 | Quantum Corporation | Extended error correction codes |
JP4056488B2 (en) * | 2004-03-30 | 2008-03-05 | エルピーダメモリ株式会社 | Semiconductor device testing method and manufacturing method |
US7562283B2 (en) * | 2005-12-27 | 2009-07-14 | D.S.P. Group Ltd. | Systems and methods for error correction using binary coded hexidecimal or hamming decoding |
US8046660B2 (en) | 2006-08-07 | 2011-10-25 | Marvell World Trade Ltd. | System and method for correcting errors in non-volatile memory using product codes |
-
2006
- 2006-08-18 US US11/505,798 patent/US7823043B2/en active Active
- 2006-10-30 WO PCT/IL2006/001249 patent/WO2007129293A2/en active Application Filing
- 2006-10-30 KR KR1020087028260A patent/KR20090015927A/en not_active Application Discontinuation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030061558A1 (en) * | 2001-09-25 | 2003-03-27 | Fackenthal Richard E. | Double error correcting code system |
Also Published As
Publication number | Publication date |
---|---|
WO2007129293A2 (en) | 2007-11-15 |
KR20090015927A (en) | 2009-02-12 |
US7823043B2 (en) | 2010-10-26 |
US20070283214A1 (en) | 2007-12-06 |
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