WO2007140130A3 - N-channel mosfets comprising dual stressors, and methods for forming the same - Google Patents

N-channel mosfets comprising dual stressors, and methods for forming the same Download PDF

Info

Publication number
WO2007140130A3
WO2007140130A3 PCT/US2007/069100 US2007069100W WO2007140130A3 WO 2007140130 A3 WO2007140130 A3 WO 2007140130A3 US 2007069100 W US2007069100 W US 2007069100W WO 2007140130 A3 WO2007140130 A3 WO 2007140130A3
Authority
WO
WIPO (PCT)
Prior art keywords
fet
carbon concentration
patterned stressor
methods
forming
Prior art date
Application number
PCT/US2007/069100
Other languages
French (fr)
Other versions
WO2007140130A2 (en
Inventor
Jinghong H Li
Yaocheng Liu
Zhijiong Luo
Anita Madan
Nivo Rovedo
Original Assignee
Ibm
Jinghong H Li
Yaocheng Liu
Zhijiong Luo
Anita Madan
Nivo Rovedo
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm, Jinghong H Li, Yaocheng Liu, Zhijiong Luo, Anita Madan, Nivo Rovedo filed Critical Ibm
Priority to CN2007800183087A priority Critical patent/CN101523608B/en
Priority to AT07797521T priority patent/ATE521089T1/en
Priority to EP07797521A priority patent/EP2036130B1/en
Publication of WO2007140130A2 publication Critical patent/WO2007140130A2/en
Publication of WO2007140130A3 publication Critical patent/WO2007140130A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Amplifiers (AREA)
  • Measuring Fluid Pressure (AREA)

Abstract

The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.
PCT/US2007/069100 2006-05-24 2007-05-17 N-channel mosfets comprising dual stressors, and methods for forming the same WO2007140130A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2007800183087A CN101523608B (en) 2006-05-24 2007-05-17 N-channel mosfets comprising dual stressors, and methods for forming the same
AT07797521T ATE521089T1 (en) 2006-05-24 2007-05-17 N-CHANNEL MOSFET WITH DOUBLE STRESSORS AND METHOD FOR PRODUCING SAME
EP07797521A EP2036130B1 (en) 2006-05-24 2007-05-17 N-channel mosfets comprising dual stressors, and methods for forming the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/420,047 2006-05-24
US11/420,047 US7279758B1 (en) 2006-05-24 2006-05-24 N-channel MOSFETs comprising dual stressors, and methods for forming the same

Publications (2)

Publication Number Publication Date
WO2007140130A2 WO2007140130A2 (en) 2007-12-06
WO2007140130A3 true WO2007140130A3 (en) 2009-04-09

Family

ID=38562118

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/069100 WO2007140130A2 (en) 2006-05-24 2007-05-17 N-channel mosfets comprising dual stressors, and methods for forming the same

Country Status (6)

Country Link
US (2) US7279758B1 (en)
EP (1) EP2036130B1 (en)
CN (1) CN101523608B (en)
AT (1) ATE521089T1 (en)
TW (1) TWI459557B (en)
WO (1) WO2007140130A2 (en)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006009272B4 (en) * 2006-02-28 2013-01-03 Globalfoundries Inc. Method of fabricating a strained transistor by late amorphization and spacers to be removed
DE102006019935B4 (en) * 2006-04-28 2011-01-13 Advanced Micro Devices, Inc., Sunnyvale Reduced body potential SOI transistor and method of manufacture
DE102006019921B4 (en) * 2006-04-28 2010-10-28 Advanced Micro Devices, Inc., Sunnyvale A method of manufacturing the embedded-layer transistor with tensile strain at a short distance from the gate electrode
US7279758B1 (en) * 2006-05-24 2007-10-09 International Business Machines Corporation N-channel MOSFETs comprising dual stressors, and methods for forming the same
US7625801B2 (en) * 2006-09-19 2009-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide formation with a pre-amorphous implant
US7892935B2 (en) * 2006-11-30 2011-02-22 United Microelectronics Corp. Semiconductor process
US20090035911A1 (en) * 2007-07-30 2009-02-05 Willy Rachmady Method for forming a semiconductor device having abrupt ultra shallow epi-tip regions
CN101447510B (en) * 2007-11-27 2010-12-22 中芯国际集成电路制造(上海)有限公司 Semiconductor device and forming method thereof
US8048750B2 (en) 2008-03-10 2011-11-01 Texas Instruments Incorporated Method to enhance channel stress in CMOS processes
US7524740B1 (en) 2008-04-24 2009-04-28 International Business Machines Corporation Localized strain relaxation for strained Si directly on insulator
JP5235486B2 (en) * 2008-05-07 2013-07-10 パナソニック株式会社 Semiconductor device
US8623728B2 (en) * 2009-07-28 2014-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high germanium concentration SiGe stressor
US8836036B2 (en) * 2010-01-05 2014-09-16 Globalfoundries Singapore Pte. Ltd. Method for fabricating semiconductor devices using stress engineering
CN102130054B (en) * 2010-01-20 2013-05-01 中芯国际集成电路制造(上海)有限公司 Method for improving divergence of cut-off leakage current of semiconductor device
US8551845B2 (en) 2010-09-21 2013-10-08 International Business Machines Corporation Structure and method for increasing strain in a device
US20120153350A1 (en) * 2010-12-17 2012-06-21 Globalfoundries Inc. Semiconductor devices and methods for fabricating the same
CN102693917B (en) * 2011-03-25 2015-07-08 中国科学院微电子研究所 Heat-stability nickel-based silicide source/drain MOSFETs (metal-oxide-semiconductor field-effect transistors) and manufacture method thereof
CN102693916B (en) * 2011-03-25 2015-01-14 中国科学院微电子研究所 Method for improving MOSFETs nickel base silicide heat stability
US8592308B2 (en) 2011-07-20 2013-11-26 International Business Machines Corporation Silicided device with shallow impurity regions at interface between silicide and stressed liner
JP5802492B2 (en) * 2011-09-09 2015-10-28 株式会社東芝 Semiconductor device and manufacturing method thereof
US8916428B2 (en) * 2012-01-05 2014-12-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a semiconductor device
US20130193492A1 (en) * 2012-01-30 2013-08-01 International Business Machines Corporation Silicon carbon film structure and method
US9018690B2 (en) * 2012-09-28 2015-04-28 Silicon Storage Technology, Inc. Split-gate memory cell with substrate stressor region, and method of making same
US8927375B2 (en) 2012-10-08 2015-01-06 International Business Machines Corporation Forming silicon-carbon embedded source/drain junctions with high substitutional carbon level
CN103811349A (en) * 2012-11-06 2014-05-21 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof
CN104217955B (en) * 2013-06-05 2017-11-03 中芯国际集成电路制造(上海)有限公司 N-type transistor and preparation method thereof, complementary metal oxide semiconductor
US9419138B2 (en) * 2014-09-29 2016-08-16 International Business Machines Corporation Embedded carbon-doped germanium as stressor for germanium nFET devices
WO2018063166A1 (en) * 2016-09-27 2018-04-05 Intel Corporation Techniques for increasing channel region tensile strain in n-mos devices
CN108962987B (en) * 2017-05-19 2020-11-13 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method for manufacturing the same
JP6852703B2 (en) * 2018-03-16 2021-03-31 信越半導体株式会社 Carbon concentration evaluation method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050035409A1 (en) * 2003-08-15 2005-02-17 Chih-Hsin Ko Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
US20050285187A1 (en) * 2004-06-24 2005-12-29 International Business Machines Corporation Strained-silicon CMOS device and method

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3443343B2 (en) * 1997-12-03 2003-09-02 松下電器産業株式会社 Semiconductor device
US6368947B1 (en) 2000-06-20 2002-04-09 Advanced Micro Devices, Inc. Process utilizing a cap layer optimized to reduce gate line over-melt
DE10034942B4 (en) 2000-07-12 2004-08-05 Infineon Technologies Ag Method for producing a semiconductor substrate with buried doping
KR100342306B1 (en) * 2000-09-05 2002-07-02 윤종용 Transistor And Method For Manufacturing The Same
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
US6703293B2 (en) 2002-07-11 2004-03-09 Sharp Laboratories Of America, Inc. Implantation at elevated temperatures for amorphization re-crystallization of Si1-xGex films on silicon substrates
US6911379B2 (en) * 2003-03-05 2005-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming strained silicon on insulator substrate
US7101742B2 (en) * 2003-08-12 2006-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel complementary field-effect transistors and methods of manufacture
CN100446272C (en) * 2003-09-04 2008-12-24 台湾积体电路制造股份有限公司 Strained-channel semiconductor structure and method of fabricating the same
US6906360B2 (en) 2003-09-10 2005-06-14 International Business Machines Corporation Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions
EP1524699B1 (en) 2003-10-17 2012-12-26 Imec Method for forming CMOS semiconductor devices having a notched gate insulator and devices thus obtained
US7303949B2 (en) 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
TWI222673B (en) * 2003-10-24 2004-10-21 Taiwan Semiconductor Mfg Substrate structure having relaxed thin-film layer with low defect-density and its manufacturing method
US7005333B2 (en) * 2003-12-30 2006-02-28 Infineon Technologies Ag Transistor with silicon and carbon layer in the channel region
US20050186722A1 (en) * 2004-02-25 2005-08-25 Kuan-Lun Cheng Method and structure for CMOS device with stress relaxed by ion implantation of carbon or oxygen containing ions
US7015108B2 (en) 2004-02-26 2006-03-21 Intel Corporation Implanting carbon to form P-type drain extensions
US7002209B2 (en) * 2004-05-21 2006-02-21 International Business Machines Corporation MOSFET structure with high mechanical stress in the channel
DE102004037087A1 (en) * 2004-07-30 2006-03-23 Advanced Micro Devices, Inc., Sunnyvale Self-biasing transistor structure and SRAM cells with fewer than six transistors
US7288448B2 (en) * 2004-08-24 2007-10-30 Orlowski Marius K Method and apparatus for mobility enhancement in a semiconductor device
US7067868B2 (en) * 2004-09-29 2006-06-27 Freescale Semiconductor, Inc. Double gate device having a heterojunction source/drain and strained channel
US7164163B2 (en) * 2005-02-22 2007-01-16 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with hybrid-strain inducing layer
JP4361886B2 (en) * 2005-02-24 2009-11-11 富士通マイクロエレクトロニクス株式会社 Semiconductor integrated circuit device and manufacturing method thereof
US7355221B2 (en) * 2005-05-12 2008-04-08 International Business Machines Corporation Field effect transistor having an asymmetrically stressed channel region
US7279758B1 (en) * 2006-05-24 2007-10-09 International Business Machines Corporation N-channel MOSFETs comprising dual stressors, and methods for forming the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050035409A1 (en) * 2003-08-15 2005-02-17 Chih-Hsin Ko Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
US20050285187A1 (en) * 2004-06-24 2005-12-29 International Business Machines Corporation Strained-silicon CMOS device and method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ANG ET AL.: "Enhanced performance in 50 nm N-MOSFETs with silicon-carbon source/drain regions. Electron Devices Meeting, 2004", IEDM TECHNICAL DIGEST. IEEE INTEMATIONAL, 13 December 2004 (2004-12-13), pages 1069 - 1071, XP010789001 *

Also Published As

Publication number Publication date
US20070281413A1 (en) 2007-12-06
TW200810119A (en) 2008-02-16
WO2007140130A2 (en) 2007-12-06
EP2036130B1 (en) 2011-08-17
CN101523608B (en) 2010-11-10
TWI459557B (en) 2014-11-01
US7473608B2 (en) 2009-01-06
EP2036130A4 (en) 2009-12-23
CN101523608A (en) 2009-09-02
ATE521089T1 (en) 2011-09-15
US7279758B1 (en) 2007-10-09
EP2036130A2 (en) 2009-03-18

Similar Documents

Publication Publication Date Title
WO2007140130A3 (en) N-channel mosfets comprising dual stressors, and methods for forming the same
TW200620479A (en) MOSFET device with localized stressor
TW200741976A (en) Methods for fabricating a stressed MOS device
TW200638463A (en) Method of forming locally strained transistor
TW200729465A (en) An embedded strain layer in thin SOI transistors and a method of forming the same
TW200802803A (en) Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions
TW200631065A (en) Strained transistor with hybrid-strain inducing layer
SG143174A1 (en) Method to form selective strained si using lateral epitaxy
WO2007075755A3 (en) Cmos device with asymmetric gate strain
WO2006023219A3 (en) Method and apparatus for mobility enhancement in a semiconductor device
WO2010056433A3 (en) OPTIMIZED COMPRESSIVE SiGe CHANNEL PMOS TRANSISTOR WITH ENGINEERED Ge PROFILE AND OPTIMIZED SILICON CAP LAYER
GB2491778A (en) A P-Fet with a strained nanowire channel and embedded sige source and drain stressors
TW200638543A (en) Hybrid-strained sidewall spacer for CMOS process
WO2006066194A3 (en) Strained nmos transistor featuring deep carbon doped regions and raised donor doped source and drain
GB2437867A (en) Non-planer mos structure with a strained channel region
TW200511583A (en) Strained-channel fin field effect transistor (FET) with a uniform channel thickness and separate gates
TW200711148A (en) Stressed field effect transistors on hybrid orientation substrate
TWI265575B (en) MOSFET device with localized stressor
JP2007324589A5 (en)
WO2007078892A3 (en) A tensile strained nmos transistor using group iii-n source/drain regions
DE602006008017D1 (en) HIGH-PERFORMANCE MOSFET WITH A SEPARATE GATE METAL SILICIDE COAT AND METHOD OF MANUFACTURING THEREOF
WO2009120612A3 (en) Semiconductor devices having tensile and/or compressive strain and methods of manufacturing and design structure
WO2005122270A3 (en) Gated field effect devices and methods of forming a gated field effect device
TW200605322A (en) Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility
TW200625523A (en) Improve transistor mobility by adjuasting stress in shallow trench isolation

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 200780018308.7

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 07797521

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2007797521

Country of ref document: EP