WO2007142865A2

WO2007142865A2 - Thin film photovoltaic structure and fabrication

Info

Publication number: WO2007142865A2
Application number: PCT/US2007/012422
Authority: WO
Inventors: David F Dawson-Elli; Kishor P Gadkaree; Robin M Walton
Original assignee: Corning Incorporated
Priority date: 2006-05-31
Filing date: 2007-05-24
Publication date: 2007-12-13
Also published as: JP2009539255A; EP2022097A2; TW200814341A; WO2007142865A3; KR20090028581A

Abstract

Novel photovoltaic structures comprising an insulator structure bonded to an exfoliation layer, preferably of a substantially single-crystal donor semiconductor wafer, and at least one photovoltaic device layer, such as a conductive layer, and systems and methods of production of a photovoltaic device, comprising creating on a donor semiconductor wafer an exfoliation layer and transferring the exfoliation layer to an insulator substrate.

Description

TBON FILM PHOTOVOLTAIC STRUCTURE AND FABRICATION

FIELD OF THE INVENTION

10001 ] The present invention relates to the systems, methods and products of manufacture of a thin film photovoltaic structure, preferably having a substantially single crystal thin film, using improved processes, including in particular transferring photovoltaic structure foundations or partially completed photovoltaic structures to insulator substrates and anodic bonding to the insulator substrates.

BACKGROUND OF THE INVENTION [0002 ] Photovoltaic structures (PVS) are a specialized form of semiconductor structure that converts photons into electricity. Fundamentally, the device needs to fulfill only two functions: photogeneration of charge carriers (electrons and holes) in a light-absorbing material, and separation of the charge carriers to a conductive contact that will transmit the electricity. This conversion is called the photovoltaic (PV) effect and used in solar cells, which convert light energy into electrical energy, and the field of research related to solar cells is known as photovoltaics. Some PVS' are semiconductor-on-insulator (SOI) structures. [0003] Referring to FIGS . 1 , 2, and 3 , block diagrams illustrate a si ngle-junction, a dual- junction, and a triple-junction photovoltaic structure, respectively. The references numerals in these figures have the following meaning: AlOl: Ge substrate; A103/105: 1.4eV GaAs cell; Al 07: grid contact; A201 : Ge substrate; A203: 1.4eV GaAs cell; A207: AlGaLnP or AlGaAs tunnel junction; A209/211: 1.9eV InGaP cell; A213: grid contract; A301: 0.7eV Ge cell and substrate; A305: GaAs tunnel junction; A307/309: 1.4eV GaAs cell; A311: tunnel junction; A313/315: 1.9eV InGaP cell; and A317: grid contact. The germanium substrate illustrated is a single crystal Ge wafer. While the efficiency of each has risen l%-3.5% over the past few years, the greater increases in efficiency have come with the addition of junctions, with each additional junction adding about 4.5%. This benefit of the additional junctions is due to the ability of the PVS device to absorb light across different band gaps and convert it to electricity, making use of more of the available light. [0004] There is a need for mechanically strong, large area, less expensive solar cells. GaAs based solar cells are a route to improved conversion efficiencies and improved outdoor reliability. GaAs which has a band gap of 1.42 eV which is close to the optimum value (1.5 eV) of band gap energy for solar energy conversion. Unlike silicon cells, GaAs cells are relatively insensitive to heat. Another significant advantage of gallium arsenide and its alloys as PV cell materials is that it is amenable to a wide range of designs. Most notably are the high efficiency multijunction solar cells which utilize thin films of GaAs or other III-V based materials such as GaInP₂ and GaInAs on bulk Ge single crystal substrates. GaAs-based multijunction solar cells have the highest demonstrated efficiencies of over 37%. Germanium substrates have been used for these cells as GaAs and Ge are closely matched in lattice spacing and thermal expansion. [0005] Substrates lower in cost than crystalline silicon including glass and ceramic alumina are being investigated for III-V compound semiconductor solar cell applications. In one example, fused silica and ceramic alumina coated with thick Ge films are used as Ge-coated surrogate substrates for epitaxial growth of high-performance GaAs/InGaP solar cells. Germanium films (2-5 μm) are deposited on thermal-expansion matched polycrystalline alumina (P-AI₂O₃). The Ge films are subsequently capped with various metal and oxide films and then re- crystallized with rapid thermal processing. Average grain sizes greater than 1 mm are achieved. Epitaxial layers of GaAs are grown on these large grain (>1 mm) thin (~2 μm) Ge layers using a CSVT technique. These GaAs/Ge/ceramic structures have been proposed as a starting point for tandem junction devices.

[0006] Having III-V semiconductor thin-film solar cells directly on a cover glass is very advantageous in that it reduces the weight of the substrate and reduces integration process costs. The solar cell practically may take a configuration with incident solar radiation upon the cover glass substrate side.

[0007 ] Researchers have investigated deposited polycrystalline thin films on glass substrates for space solar cell application. The crystal quality limits the performance of the III-V solar cells with polycrystalline films. To wit, none of the aforementioned structures on low cost, glass substrates have led to GaAs cells with high efficiencies (>30%). Hence, a process and product based on a low cost and transparent glass substrate are desired that overcome the issues associated with prior art.

[0008] Drawing from the microelectronic semiconductor world and for ease of presentation, the following discussion will at times be in terms of semiconductor-on-insulator (SOI) structures. The references to this particular type of SOI structure are made to facilitate, the explanation of the invention and are not intended to, and should not be interpreted as, limiting the invention's scope in any way. The SOI abbreviation is used herein to refer to semiconductor-on- insulator structures in general, including, but not limited to, silicon-on-insulator structures, such as silicon-on-glass (SiOG) structures. Similarly, the SiOG abbreviation is used to refer to semiconductor-on-glass structures in general, including, but not limited to, silicon-on-glass structures. The SiOG nomenclature is also intended to include semiconductor-on-glass-ceramic structures, including, but not limited to, silicon-on-glass-ceramic structures. The abbreviation SOI encompasses SiOG structures. [ 0009] Various ways of obtaining SOI-structure wafers include (1) epitaxial growth of silicon (Si) on lattice-matched substrates; (2) bonding of a single-crystal silicon wafer to another silicon wafer on which an oxide layer of Siθ₂ has been grown, followed by polishing or etching of the top wafer down to, for example, a 0.05 to 0.3 micron (50 - 300 ran) layer of single-crystal silicon; and (3) ion-implantation methods, in which ions (such as hydrogen or oxygen ions) are implanted to form, e.g., a buried oxide layer in the silicon wafer topped by Si, in the case of oxygen ion implantation, or to separate (exfoliate) a thin Si layer from one silicon wafer for bonding to another Si wafer with an oxide layer, as in the case of hydrogen ion implantation. [ 0010 ] Chemical mechanical polishing (CMP) may be used also to process the SOI structure after the thin silicon film has been exfoliated from the silicon material wafer. Disadvantageously, however, the CMP process does not remove material uniformly across the surface of the thin silicon film during polishing. Typical surface non-uniformities (standard deviation / mean removal thickness) are in the 3-5% range for semiconductor films. As more of the silicon film's thickness is removed, the variation in the film thickness correspondingly worsens.

[ 0011] In contrast to microelectronic applications of SOI structures, photovoltaic structures are more tolerant of such defects, although such defects nonetheless adversely may affect performance of the photovoltaic cell. While such finishing techniques as CMP may improve surface characteristics, the defect-tolerance of photovoltaic structures may make them cost-prohibitive. It would therefore be desirable to incorporate the advantages of SOI structure manufacturing advances with the requirements of the photovoltaic structure manufacturing, while minimizing the disadvantages of the associated SOI structure manufacturing advances. SUMMARY OF THE INVENTION

[0012] In accordance with one or more embodiments of the present invention, systems, methods and apparatus of forming a photovoltaic device include creating an exfoliation layer and transferring it to an insulator structure. The exfoliation layer may be created from a donor semiconductor wafer. The donor semiconductor wafer and the exfoliation layer preferably may comprise substantially single crystal semiconductor material. The exfoliation layer preferably may include one or more photovoltaic device layers, such as a conductive layer, created prior to transfer to the insulator substrate. Transferring the exfoliation layer preferably may include forming by electrolysis an anodic bond between the exfoliation layer and the insulator substrate and then separating the exfoliation layer from the donor semiconductor wafer using thermo- mechanical stress. One or more photovoltaic device layers also may be created in, on or above the exfoliation layer after the exfoliation layer has been transferred to the insulator substrate. One or more finishing processes may be performed before or after transferring the exfoliation layer, and performance of a finishing process may create a photovoltaic device layer. [0013 ] In accordance with one or more embodiments of the present invention, systems, methods and apparatus of forming a photovoltaic semiconductor-on-insulator structure, include creating a photovoltaic structure foundation on a donor semiconductor wafer, transferring the photovoltaic structure foundation to an insulator substrate, and depositing a plurality of photovoltaic structure layers on the PV foundation. Transferring may include anodic bonding of the photovoltaic structure foundation to the insulator structure, and separating the photovoltaic structure foundation from the donor semiconductor wafer. [0014] In accordance with one or more embodiments of the present invention, systems, methods and apparatus of forming a photovoltaic semiconductor-on-insulator structure, include creating a partially completed photovoltaic cell on a donor semiconductor wafer, and transferring the partially completed photovoltaic structure to an insulator substrate. Transferring may include anodic bonding of the partially completed photovoltaic cell to the insulator structure, and separating the partially completed photovoltaic cell from the donor semiconductor wafer.

[0015] In accordance with one or more embodiments of the present invention, systems, methods and apparatus of forming a photovoltaic device include: subjecting a donor semiconductor wafer to an ion implantation process to create an exfoliation layer in the donor semiconductor wafer; bonding the exfoliation layer to an insulator substrate; separating the exfoliation layer from the donor semiconductor wafer, the exfoliation layer to serve as a photovoltaic structure foundation; and creating a plurality of photovoltaic structure layers on the photovoltaic structure foundation.

[ 0016] In accordance with one or more embodiments of the present invention, systems, methods and apparatus of forming a photovoltaic device include: subjecting a donor semiconductor wafer to an ion implantation process to create an exfoliation layer in the donor semiconductor wafer; creating a partially completed photovoltaic cell on the exfoliation layer; bonding the exfoliation layer to an insulator substrate; separating the exfoliation layer having the partially completed photovoltaic cell from the donor semiconductor wafer, thereby exposing at least one cleaved surface; and subjecting the at least one cleaved surface to a finishing process. [0017] In accordance with one or more embodiments of the present invention, systems, methods and apparatus of forming a photovoltaic device include: creating a partially completed photovoltaic cell on a donor semiconductor wafer; subjecting the partially completed photovoltaic cell and the prepared donor surface of the donor semiconductor wafer to an ion implantation process to create an exfoliation layer in the donor semiconductor wafer; bonding the exfoliation layer to an insulator substrate; separating the exfoliation layer having the partially completed photovoltaic cell from the donor semiconductor wafer, thereby exposing at least one cleaved surface; and subjecting the at least one cleaved surface to a finishing process. [ 0018 ] In one or more embodiments, the step of bonding may include: heating at least one of the insulator substrate and the donor semiconductor wafer; bringing the insulator substrate into direct or indirect contact with the exfoliation layer of the donor semiconductor wafer; and applying a voltage potential across the insulator substrate and the donor semiconductor wafer to induce the bond. The temperature of the insulator substrate and the semiconductor wafer may be elevated to within about 150⁰C of the strain point of the insulator substrate. The temperatures of the insulator substrate and the semiconductor wafer may be elevated to different levels. The voltage potential across the insulator substrate and the semiconductor wafer may be between about 100 to 10000 volts. Stress may be induced by cooling the bonded insulator substrate, exfoliation layer, and donor semiconductor wafer such that a fracture occurs substantially at an ion-defect phase defining a boundary of the exfoliation layer within the donor semiconductor wafer. The heat and differential coefficients of thermal expansion, of the ion-defect phase, versus the surrounding wafer, cause the exfoliation layer to cleave at the ion-defect phase. The result is a thin film of semiconductor-bonded to the insulator.

[ 0019 ]- The at least one cleaved surface may include a first cleaved surface of the donor semiconductor wafer and a second cleaved surface of the exfoliation layer. With respect to the first cleaved surface associated with donor semiconductor wafer, the finishing process may include preparing the donor semiconductor wafer for reuse. With respect to the second cleaved surface associated with exfoliated layer, the finishing process may include completing the partially completed photovoltaic cell.

[0020 ] According to one or more preferred embodiment of the present invention, new solar cells may be based on single crystal Ge, Si or GaAs films on transparent glass or glass ceramic substrates. In the case of GaAs-based cells, as an added advantage, a germanium layer may be present between the substrate and the single crystalline GaAs layer. The germanium layer may be doped in order to use the substrate as a bottom layer (i.e., back contact layer) of a multi- junction solar cell. The glass or glass ceramic substrates may be expansion matched to Ge, Si, GaAs or Ge/GaAs. The strongly adherent single crystal layer of Si, Ge, GaAs or Ge/GaAs film may be obtained on the glass or glass ceramic substrate via an anodic bonding process described in U.S. Patent Application No.: 2004/0229444.

[0021] The process first involves hydrogen or hydrogen and helium implantation of the

Ge, Si or GaAs wafer, and in the case of GaAs, possibly followed by deposition of a germanium film on the surface of the GaAs wafer. The Ge, Si or Ge-coated GaAs wafer is then bonded to the glass substrate, followed by separation of a thin film structure of Ge, Si, GaAs or GaAs/Ge. The SOG structure thus obtained may be polished to remove the damaged region and to expose the good quality single crystal layer of the semiconductor. This SOG structure may be used then as a template for subsequent epitaxial growth of multiple layers of Si, Ge, GaAS, GaInP₂, GaInAs, etc. to form desired solar cells. The glass, in addition to being expansion matched to the semiconductor layer also may have a strain point high enough to withstand subsequent deposition conditions. [0022] Typical photovoltaic cell structures include a p-type — intrinsic — n-type (p-i-n), a metal-insulator-semiconductor (MIS), so-called "tandem" junction cells, multi-junction cells, and complex p-n multilayer structures, but the present invention is not limited to these structures. It is within the competency of persons of ordinary skill in the photovoltaics arts to create the partially completed photovoltaic cell on the donor semiconductor wafer according to desired product characteristics, such as single-junction versus multi-junction. Similarly, whether the partially completed photovoltaic cell is created before or after the ion implantation is a decision within the competency of persons of ordinary skill, taking into consideration a suitable ion penetration depth in the semiconductor material. [0023] It is noted that the donor semiconductor wafer may be a part of structure that includes a substantially single-crystal donor semiconductor wafer and optionally includes an epitaxial semiconductor layer disposed on the donor semiconductor wafer. The exfoliation layer (e.g., the layer bonded to the insulator substrate and separated from the donor semiconductor structure) may thus be formed substantially from the single-crystal donor semiconductor wafer material. Alternatively, the exfoliation layer may be formed substantially from the epitaxial semiconductor layer (and which may also include some of the single-crystal donor semiconductor wafer material).

[ 0024 ] The advantages of one or more embodiments of the present invention are best understood after reading the detailed technical description, and in relation to existing SOI processes. Nonetheless, the primary advantages include: photovoltaic structure variation; thinner silicon films; more uniform silicon films with higher crystal quality; faster manufacturing throughput; improved manufacturing yield; reduced contamination; and scalability to large substrates. These benefits naturally combine to reduce costs. [ 0025] Photovoltaic structures (PVS) may be varied insofar as complex photovoltaic structures may be made through high temperature processes on donor semiconductor wafers. The resultant high performance PVS then may be transferred to a low-cost glass substrate and completed, for instance, with deposition of remaining layers and any patterning required to complete the circuitry. [ 0026] The present invention allows use of only the required thickness of semiconductor (around 10-30 microns for Si₅ and 1-3 microns for direct bandgap semiconductors such as GaAs). hi contrast to the transfer of thicker silicon films to the insulator substrate that are then polished to remove the damaged surface, control of which is difficult for very thin films, little material is removed in the process as described in this invention, allowing thin silicon films to be transferred directly, with additional thickness deposited or grown thereafter. [ 0027 ] Uniform films are very desirable. Again, because little material is removed in the process, the silicon film thickness uniformity is determined by the ion implant. This has been shown to be quite uniform in certain embodiments, with a standard deviation of around 1 run. In contrast, polishing typically results in a deviation in film thickness of 5% of the amount removed. [0028] As demand continues to rise, faster throughput is critical. However, the polishing technologies identified for fabricating SiOG have process times on the order of tens of minutes, and the furnace anneals can be several hours. With more uniform films, the need in photovoltaic cells for polishing or furnace annealing is reduced.

[ 0029] Improving manufacturing yield is also important for waste and cost reduction.

By avoiding the wire-saw kerf loss, material waste may be reduced significantly. Likewise, the expensive donor semiconductor wafer may be polished and reused multiple times. By using thin films, material consumption likewise may be reduced significantly. If polishing of the SOI structure is avoided, the overall manufacturing yield is expected to improve. This is particularly true if the polishing process has a low step yield, as anticipated. The process window is expected to be large because of the crystalline nature of the film, and therefore the yield is expected to be high. [0030] Due to the sensitive nature of SOIs, contamination adversely may affect performance, so reducing contamination is highly desirable. With this in mind, avoiding the need for polishing with an abrasive slurry to reduce layer thickness reduces the potential for contamination. Furthermore, avoiding the need for a furnace anneal also avoids the diffusion of contaminants that may occur during a lengthy thermal anneal process. This may play an important consideration in the efficiency of the photovoltaic devices.

[0031] The process is scalable to large areas. This scalability potentially extends the product life as customer substrate size requirements increase. Solar panels are often large to maximize use of available space, so the larger photovoltaic cells become, the fewer photovoltaic cells are necessary to connect to create a large solar panel. In contrast, surface polishing and furnace annealing become increasing difficult for larger substrate sizes.

[ 0032 ] In particular, key advantages of preferred embodiments of the present invention include: 1) the use of low cost, expansion-matched glass or glass ceramic substrates, compared to other more expensive semiconductor substrates (such as silicon for a Ge layer and subsequent GaAs growth, as has been used previously) or thermally mismatched ceramic substrates described in the prior art; 2) the presence of the single crystal template layer of Si, Ge or multilayer

GaAs/Ge on the glass substrate, which is used as a template to create lattice matched, very low defect semiconductor layers for the solar cells with high efficiencies, unlike polycrystalline templates used in prior art; 3) the transparency of the substrate allowing flexibility in module fabrication. [ 0033 ] Other aspects, features, advantages, etc. will become apparent to one skilled in the art when the description of the invention herein is taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS [ 0034 ] For the purposes of illustrating the various aspects of the invention, wherein like numerals indicate like elements, there are shown in the drawings simplified forms that are presently preferred, it being understood, however, that the invention is not limited by or to the precise arrangements and instrumentalities shown, but rather only by the issued claims. The drawings are not to scale, nor are the aspects of the drawings to scale relative to each other. [0035] FIGS. 1 , 2 and 3 are block diagrams illustrating, respectively, a single-junction, a dual-junction, and a triple-junction photovoltaic structure.

[ 0036 ] FIGS. 4, 5 and 6 are block diagrams, each illustrating a photovoltaic structure in accordance with one or more embodiments of the present invention. [0037 ] FIGS. 7, 8 and 9 are flow diagrams illustrating process steps that may be carried out to produce a photovoltaic SOI structure in accordance with one or more embodiments of the present invention.

[ 0038 ] FIGS. 10-18 are block diagrams illustrating intermediate and near-final structures formed using the processes in accordance with one or more embodiments of the present invention.

[0039 ] FIG. 19 depicts a simplified multijunction photovoltaic structure according to one or more preferred embodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0040] Unless otherwise indicated, all numbers such as those expressing weight percents of ingredients, dimensions, and values for certain physical properties used in the specification and claims are to be understood as being modified in all instances by the term "about." It should also be understood that the precise numerical values used in the specification and claims form additional embodiments of the invention. Efforts have been made to ensure the accuracy of the numerical values disclosed in the Examples. Any measured numerical value, however, can inherently contain certain errors resulting from the standard deviation found in its respective measuring technique. [0041] By "crystalline semiconductor material," it is meant that the material may be completely crystalline or substantially crystalline, with or without intentionally or accidentally introduced defects and/or dopants therein. Thus it should include: (i) precursor materials, semiconductive or non-semiconductive per se, for forming materials having semiconductive properties, and (ii) materials that are semiconductive per se, formed by, e.g., doping precursor materials. The crystalline semiconductor material may be single crystalline or polycrystalline.

Indeed, semiconductive materials normally contain at least some internal or surface defects either inherently or purposely added, such as lattice defects or grain boundaries. The term "substantially • crystalline" also reflects the fact that certain dopants may distort or otherwise affect the crystal structure of the semiconductor material.

[ 0042] Referring to FIGS. 4, 5 and 6, occasionally referred to collectively as FIGS. 4-6, there are shown PVS variations 100A, IOOB and lOOC, respectively, of photovoltaic SOI structure 100 in accordance with one or more embodiments of the present invention. Photovoltaic SOI structure 100 may be referred to as a PV SOI structure 100, or simply PVS 100. With respect to the figures, the SOI structure 100 is exemplified as an SiOG structure. The SiOG structure 100 may include an insulator substrate 101 made of glass, a photovoltaic structure foundation 102 (FIG. 4), ion migration zones 103, a back contact layer 104, a p-type semiconductor layer 106, an n-type semiconductor layer 108, and a conducting window layer 110. The SiOG structure 100 has suitable uses in connection with photovoltaic devices.

[ 0043 ] The conducting window layer 110 is an electrically conductive layer of material that is acting as an ohmic contact. The conducting window layer may be translucent, transparent or semi-transparent. An exemplary material would be indium tin oxide, a material that typically is formed by reactive sputtering of an In-Sn target in an oxidative atmosphere. An alternative to indium tin oxide may include, for instance, aluminium-doped zinc oxide, boron-doped zinc oxide, or even carbon nanotubes. Indium tin oxide (ITO, or tin-doped indium oxide) is a mixture of indium(m) oxide (In₂O₃) and tin(IV) oxide (SnO₂), typically may be 90% In₂O₃, 10% SnO₂ by weight. It is transparent and colorless in thin layers. In bulk form, it is yellowish to grey. Indium tin oxide's main feature is the combination of electrical conductivity and optical transparency. However, a compromise has to be reached during film deposition, as high concentration of charge carriers will increase the material's conductivity, but decrease its transparency. Thin films of indium tin oxide are most commonly deposited on surfaces by electron beam evaporation, physical vapor deposition, or a range of sputtering techniques.

[0044] The semiconductor material of the layers 106 and 108 may be in the form of a substantially single-crystal material. The term "substantially" is used hi describing the layers 106, 108 to take account of the fact that semiconductor materials normally contain at least some internal or surface defects either inherently or purposely added, such as lattice defects or grain boundaries. The term substantially also reflects the fact that certain dopants may distort or otherwise affect the crystal structure of the semiconductor material. In particular, p-type semiconductor layer 106 includes a p-type doping agent, whereas n-type semiconductor layer 108 includes an n-type doping agent. Note that the p-type layer 106 is thicker than the n-type layer 108 in all cases where it is desired that the majority of the electron hole pairs are created in the p- type layer 106. [ 0045] For the purposes of discussion, it is assumed that the semiconductor layers 106,

108 are formed from silicon, unless stated otherwise. It is understood, however, that the semiconductor material may be a silicon-based semiconductor or any other type of semiconductor, such as the IH-V, III-IV, etc., classes of semiconductors. Examples of these materials include: silicon (Si), germanium-doped silicon (SiGe), silicon carbide (SiC), germanium (Ge), gallium arsenide (GaAs), gallium phosphide (GaP), and indium phosphide

(InP).

[ 0046] The back contact layer 104 may be a conductive layer, such as a conductive metal-based or metal oxide-based layer. The back contact layer is an ohmic contact, i.e., a region on a semiconductor device that has been prepared so that the current-voltage (I- V) curve of the device is linear and symmetric. The back contact material may be chosen for its thermal robustness in contact with Si. For instance, back contact layer 104 may be film based on aluminum or a suicide, such as or titanium disilicide, tungsten disilicide or nickel suicide, an example of which is discussed below. A silicide-polysilicon combination has better electrical properties than polysilicon alone and yet does not melt in subsequent processing.

[ 0047 ] The back contact layer 104 may be created, for example, by deposition, such as

LPE, CVD or PECVD. Mesotaxy or epitaxy may be used also. Whereas as epitaxy is the growth of a matching phase on the surface of a substrate, mesotaxy is the growth of a crystallographically matching phase underneath the surface of the host crystal. Ih this process, ions are implanted at a high enough energy and dose into a material to create a layer of a second phase, and the temperature is controlled so that the crystal structure of the target is not destroyed. The crystal orientation of the layer can be engineered to match that of the target, even though the exact crystal structure and lattice constant may be very different. For example, after the implantation of nickel ions into a silicon wafer, a layer of nickel suicide can be grown in which the crystal orientation of the sin^' cide matches that of the silicon.

[ 0048 ] Use of epitaxy or mesotaxy to form back contact layer 104 may be thought of as a conceptual interface between the structure IOOA described FIG. 4 and the structures IOOB and IOOC described in FIGS. 5 and 6, insofar as the exfoliation layer 122, discussed in FIGS. 7-9 and 11, may include an epitaxial or mesotaxial layer, forming the back contact 104, and the semiconductor layer above it. Whereas the semiconductor layer alone may serve as a photovoltaic structure foundation (PVSF) 102, in FIG. 4, the combination of the semiconductor layer and back contact layer 104 may be considered a partially completed PVS 124, introduced in FIGS. 8 and 13. Hence, forming back contact layer 104 using epitaxy or mesotaxy or ion implantation before anodic bonding (step 208) creates a partially completed PVS 124 that is transferred to the substrate 101 as in processes 200B and 200C, whereas transferring a PVSF 102 and then forming back contact layer 104 using epitaxy or mesotaxy or ion implantation after exfoliation separation (step 210) follows process 200A. Likewise, the back contact layer 104 may be formed by heavy doping of PVSF 102 after exfoliation separation. Such heavy doping can typically be carried out by ion implantation.

[0049 ] Moreover, if the back contact layer 104 is deposited on top of PVSF 102 after exfoliation separation (step 210), a PVS 100 of variation IOOA may result. Alternatively, if PVSF 102 is doped, before or after mesotaxy, as a p-type semiconductor and back contact layer 104 is formed by mesotaxy, a PVS 100 similar to variation IOOA or IOOB may result. If the depth of the mesotaxial growth of the back contact layer 104 is within the middle of PVSF 102, a layer of PVSF 102 may remain underneath the back contact layer 104, as in variation IOOA. If the depth of the mesotaxial growth of the back contact layer 104 reaches the bonding surface 126 of PVSF 102, little to none of the layer of PVSF 102 may remain underneath the back contact layer 104, as in variation IOOB.

[ 0050 ] Insofar as the conductive layer is formed on or in the exfoliation layer 122, whether formed by epitaxy, mesotaxy, ion implantation, doping, vapor transport, vapor deposition, etc., the conductive layer will be integral to the exfoliation layer 122. If the conductive layer is formed on or in the exfoliation layer 122 before the exfoliation layer 122 is bonded to the insulator substrate 101, the conductive layer will be proximate to the insulator substrate 101 when the exfoliation layer 122 is bonded to the substrate 101. In other words, the conductive layer will have been formed near the side of the exfoliation layer 122 that faces the insulator substrate, such that, for example, the resulting conductive layer may be between the insulator substrate and the exfoliation layer. If the exfoliation layer 122 is bonded to the insulator substrate 101 first and then the conductive layer is formed on or in the exfoliation layer 122 thereafter, the conductive layer will be on or near the side of the exfoliation layer 122 opposite the insulator substrate 101 and thus distal to the insulator substrate 101. Likewise, any photovoltaic device layers formed in, on or above the exfoliation layer 122 after the exfoliation layer 122 has been bonded to the insulator substrate 101 will be distal to the insulator substrate 101. [ 0051] As will be discussed in more detail in reference to FIGS. 15-17, an ion migration zone 103 forms on either side of an anodic bond between the insulator substrate 101 and the layer bonded to the insulator substrate 101; i.e., PVS foundation 102, in variation IOOA; back contact 104, in variation IOOB; or conducting window layer 110, in variation lOOC. The ion migration zones 103 result from the anodic bonding process described in FIG. 15. These ion migration zones 103 have not been present in prior art photovoltaic structures.

[0052] La contrast to variations IOOB and 10OC in FIGS. 5 and 6, variation IOOA in FIG.

4 includes a PV structure foundation 102. Photovoltaic structure foundation 102 may arise when the exfoliation layer 122 is transferred to the insulator substrate 101 in the absence of any additional layer(s) that would amount to a partially completed PVS 124 (PCPVS). In essence, the exfoliation layer 122 may be thought to become the PVSF 102 upon bonding to insulator substrate 101. As such, PVSF 102 preferably may comprise a substantially single crystal semiconductor layer, as it comes from donor wafer 120 introduced in FIGS. 7 and 10. [ 0053 ] The insulator substrate 101, here a glass substrate 101, may be formed from an oxide glass or an oxide glass-ceramic. Although not required, the embodiments described herein may include an oxide glass or glass-ceramic exhibiting a strain point of less than about 1,000⁰C. As is conventional in the glass making art, the strain point is the temperature at which the glass or glass-ceramic has a viscosity of 10¹⁴⁶ poise (10^{13 6} Pa.s). As between oxide glasses and oxide glass-ceramics, the glasses may have the advantage'of being simpler to manufacture, thus making them more widely available and less expensive.

[ 0054] By way of example, the glass substrate 101 may be formed from glass substrates containing alkaline-earth ions, such as, substrates made of Glass No. 1737 and Eagle 2000™, both supplied by Corning Incorporated, Corning, New York, U. S. A. These glass materials have other uses, in particular, for example, in the production of liquid crystal displays. [ 0055] The glass substrate may have a thickness in the range of about 0.1 mm to about

10 mm, such as in the range of about 0.5 mm to about 3 mm. For some SOI structures, insulating layers having a thickness greater than or equal to about 1 micron (i.e., 0.001 mm or 1000 nm) are desirable, e.g., to avoid parasitic capacitive effects which arise when standard SOI structures having a silicon/silicon dioxide/silicon configuration are operated at high frequencies. In the past, such thicknesses have been difficult to achieve. In accordance with the present invention, an SOI structure having an insulating layer thicker than about 1 micron is readily achieved by simply using a glass substrate 101 having a thickness that is greater than or equal to about 1 micron. A lower limit on the thickness of the glass substrate 101 may be about 1 micron, i.e., 1000 nm. [0056 ] In general, the glass substrate 101 should be thick enough to support the semiconductor layer 106, 108 through the bonding process steps, as well as subsequent processing performed on the photovoltaic SiOG structure 100. Although there is no theoretical upper limit on the thickness of the glass substrate 101, a thickness beyond that needed for the support function or that desired for the ultimate photovoltaic SiOG structure 100 might not be advantageous since the greater the thickness of the glass substrate 101, the more difficult it will be to accomplish at least some of the process steps in forming the photovoltaic SiOG structure 100. [ 0057 ] The oxide glass or oxide glass-ceramic substrate 101 may be silica-based. Thus, the mole percent of Siθ₂ in the oxide glass or oxide glass-ceramic may be greater than 30 mole percent and may be greater than 40 mole percent. In the case of glass-ceramics, the crystalline phase can be mullite, cordierite, anorthite, spinel, or other crystalline phases known in the art for glass-ceramics. Non-silica-based glasses and glass-ceramics may be used in the practice of one or more embodiments of the invention, but are generally less advantageous because of their higher cost and/or inferior performance characteristics.

[ 0058] Similarly, for some applications, e.g., for SOI structures employing semiconductor materials that are not silicon-based, glass substrates which are not oxide based, e.g., non-oxide glasses, may be desirable, but are generally not advantageous because of then- higher cost. As will be discussed in more detail below, in one or more embodiments, the glass or glass-ceramic substrate 101 is designed to match a coefficient of thermal expansion (CTE) of one or more semiconductor materials (e.g., silicon, germanium, etc.) of the layer(s) (potentially 102, 104, 106, 108, or 110) that is (are) bonded thereto, directly or indirectly. The CTE match ensures desirable mechanical properties during heating cycles of the deposition process.

[ 0059] For photovoltaic applications, the glass or glass-ceramic 101 may be transparent in the visible, near UV, and/or IR wavelength ranges, e.g., the glass or glass ceramic 101 may be transparent in the 350 run to 2 micron wavelength range. Having transparent, or at least translucent, glass is important in particular in variation lOOC, where the light enters the insulator substrate 101 before reaching the rest of PV structure lOOC. However, in variations IOOA and 10OB, the light does not enter the insulator substrate 101, so it is largely irrelevant whether the insulator substrate 101 is translucent, let alone transparent, in which case the insulator substrate 101 is chosen based on other criteria, inter alia CTE, not the least of which is cost. [ 0060] Although the glass substrate 101 may be composed of a single glass or glass- ceramic layer, laminated structures may be used if desired. When laminated structures are used, the layer of the laminate closest to the layer bonded thereto (e.g., 102, 104 or 110) may have the properties discussed herein for a glass substrate 101 composed of a single glass or glass-ceramic. Layers farther from the bonded layer may also have those properties, but may have relaxed properties because they do not directly interact with the bonded layer. In the latter case, the glass substrate 101 is considered to have ended when the properties specified for a glass substrate 101 are no longer satisfied.

[ 0061] Referring to FIGS. 7, 8 and 9, occasionally referred to collectively as FIGS. 7-9, process steps are illustrated that may be carried out in order to produce the PV structure 100 in accordance with one or more embodiments of the present invention. Process 200A is depicted in FIG. 7, process 200B is depicted in FIG. 8, and process 200C is depicted in FIG. 9. The individual actions (steps) in these block drawings have the following meaning: 202: Prepare surface of donor semiconductor wafer; 203: Subject the donor semiconductor wafer to a ion implantation process; 204: Subject the donor semiconductor wafer to mild oxidation; 205: Create the partially completed photovoltaic structure;

206: Subject partially completed PVS and donor wafer to an ion implantation process; 207: subject the partially completed photovoltaic structure to mold oxidation; 208: Form anodic bond between photovoltaic structure (or partially completed photovoltaic) foundation and glass;

210: Separate the glass layer/PVSF/exfoliation layer from the donor semiconductor wafer; and

212: Subject the donor semiconductor wafer and/or PVS foundation to finishing process. [0062 ] FIGS. 10-18 illustrate intermediate and near-final structures that may be formed in carrying out the processes of FIGS. 7, 8 and 9. In FIG. 10, the arrows indicate a surface preparation operation. In FIG. 11 , the arrows indicate a stream of ions (such as hydrogen ions) being implanted and general directions thereof according to certain embodiments of the present invention. In FIG. 12, the arrows indicate, e.g., O₂ plasma or other materials or operations and general direction thereof in the surface finishing step of the exfoliation layer according to certain embodiments of the present invention. In FIG. 13, the arrows indicate the materials and/or operations, and general deposition direction thereof, for forming back contact layer and/or the conducting window in certain embodiments of the present invention. In FIG. 14, the arrows indicate the materials (such as doping agents) and/or operations (doping process), and general direction thereof, for doping the respective layers.

[0063] At action 202 of FIGS. 7-10, a prepared donor surface 121 of a donor semiconductor wafer 120 is prepared, such as by polishing, cleaning, etc. to produce a relatively flat and uniform prepared donor surface 121 suitable for bonding to a subsequent layer of the

PVS. The prepared donor surface 121 will form the underside of the PV structure foundation 102 or semiconductor layer 106, 108. For the purposes of discussion, the semiconductor wafer 120 may be a doped (n-type or p-type) substantially single-crystal Si wafer, although as discussed above any other suitable semiconductor material may be employed. [0064] At either action 203, for processes 200A and 200B, or action 206, for process

200C₅ also shown in FIG. 11, an exfoliation layer 122 is created by subjecting an ion implantation surface 121i, i.e., the prepared donor surface 121, or any layer created on prepared donor surface 121, to one or more ion implantation processes to create a weakened region below the prepared donor surface 121 of the donor semiconductor wafer 120. Although the embodiments of the present invention are not limited to any particular method of forming the exfoliation layer 122, one suitable method dictates that the prepared donor surface 121 of the donor semiconductor wafer 120 may be subject to a hydrogen ion implantation process to at least initiate the creation of the exfoliation layer 122 in the donor semiconductor wafer 120. [00651 The implantation energy may be adjusted using conventional techniques to achieve an approximate thickness of the exfoliation layer 122. By way of example, hydrogen ion implantation may be employed, although other ions or multiples thereof may be employed, such as boron + hydrogen, helium + hydrogen, or other ions known in the literature for exfoliation. Again, any other known or hereinafter developed technique suitable for forming the exfoliation layer 122 may be employed without departing from the spirit and scope of the present invention. [ 0066 ] Depending on the parameters of the PV SOI structure 100, the number and thickness of layers on top of the prepared donor surface 121, and the potential use of any intermediate preparation step, such as CMP or FA, the exfoliation layer 122 may be made as thick or thin as desired and/or as feasible. If various design constraints require the exfoliation layer 122 to be thicker than desired, such as for use in microelectronics, a known method of mass removal, such as CMP or polishing, may be used to reduce the thickness of the layer 122 after it is exfoliated in action 210. However, using a mass removal step adds time and expense to the overall manufacturing process and may not be necessary for PVS 100. For instance, in variation 10OA, the PVSF 102 layer may not need to be thin or thick; preferably, PVSF 102 is thick enough to serve as a stable foundation for later finishing processes, but otherwise thin to conserve materials, and hence money. [0067 ] The opposite issue is more likely to arise with PV structure 100, namely that the exfoliation layer may be too thin. In variations 10OB and 10OC, a thick layer of Si is desirable for a PVS 100 because a thicker layer of Si will absorb more light and increase its efficiency. The energy needed to create a desirably thick exfoliation layer may exceed available equipment parameters, and hence additional Si may be deposited or grown epitaxially after the exfoliation layer 122 is created. The additional Si may be added to the exfoliation layer 122 before or after it is transferred to the glass substrate 101. If added before, the Si addition becomes part of a creation of a partially completed PVS 124, whereas if added after, the Si addition becomes part of a finishing process. Similarly, semiconductor layers will be added to PVS 10OA after PVSF 102 and back contact 104 are on substrate 101. [0068 ] At either action 204, for processes 200A and 200B, or action 207, for process

200C, also shown in FIG. 12, the ion implantation surface 121i, i.e., the prepared donor surface 121, and any layer created on prepared donor surface 121, on donor semiconductor wafer 120 may be treated to reduce, for example, the hydrogen ion concentration on the ion implantation surface 121i. For example, the donor semiconductor wafer 120 may be washed and cleaned, and the bonding surface 126 of the exfoliation layer 122 may be subjected to mild oxidation. The mild oxidation treatments may include treatment in oxygen plasma, ozone treatments, treatment with hydrogen peroxide, hydrogen peroxide and ammonia, hydrogen peroxide and an acid or a combination of these processes. It is expected that during these treatments hydrogen-terminated surface groups oxidize to hydroxyl groups, which in turn also makes the surface of the bonding surface 126 hydrophilic. The treatment may be carried out at room temperature for the oxygen plasma and at temperature between 25-150⁰C for the ammonia or acid treatments. [0069 ] Action 205 of FIGS. 8 and 9, also shown in FIGS. 13 and 14, involves creating a partially completed PVS 124 on the donor semiconductor wafer 120. The partially completed PVS 120 may be created either after the exfoliation layer 122 is created, as in process 200B, or before the exfoliation layer 122 is created, as in process 200C. After both the exfoliation layer 122 and the partially completed PVS 124 are created, though, the exfoliation layer actually forms part of the partially completed PVS 124. An exposed surface of the partially completed PVS 124 will be a bonding surface 126 for bonding to the glass insulator substrate 101 in action 208. [0070] With reference to FIGS. 13 and 14, occasionally referred to collectively as FIGS.

13-14, the donor semiconductor wafer 120 may be processed as part of the creation of a partially completed PVS 124. FIGS. 13-14 depicts the exfoliation layer 122 as already having been formed on the prepared donor surface 121 of the donor semiconductor wafer 120, when further steps are taken in the creation of the partially completed PVS 124. Many different actions may be taken in creating the partially completed PVS 124. For instance, creation of the partially completed PVS 124 may include, as shown in FIG. 13, addition of the back contact layer 104, as in variation 10OB, or addition of the conducting window layer 110, as in variation 11OB, or as shown in FIG. 14, use of an intermediary doping step.

[0071] FIG. 13 depicts the addition, according to one or more embodiments of the present invention, of either the back contact layer 104, as in variation 10OB, or the conducting window layer 110, as in variation lOOC. On a high level, these two processes-are similar enough to may be depicted using one block diagram. While a simplified deposition process is depicted, such as CVD or PECVD, the diagram is meant to represent any possible process, such as epitaxy and mesotaxy, as discussed above. It is preferred that the back contact 104, or conducting window layer 110, respectively, be deposited on the partially completed PVS 124, rather than directly on the glass substrate 101 , prior to bonding the partially completed PVS and the glass substrate 101, insofar as the anodic bonding process of action 208 appears to work better in this sequence. Another benefit of depositing one of these onto the partially completed PVS 124 while attached to the donor semiconductor wafer 120 would be the relaxation of process constraints required to deposit these layers directly onto the glass substrate 101, which may be more sensitive to extreme conditions. [0072 ] FIG. 14 depicts the ion implantation surface 121i of exfoliation layer 122 being doped, creating a subsurface n-p junction 128. Depending on whether variation IOOB or IOOC is desired, for example, semiconductor layers 106, 108 may be made from a doped Si boule that receives an opposite doping on its surface. In an exemplary embodiment of variation IOOB, an n- type doped donor semiconductor layer 120 may be doped on its surface with a p-type doping agent, creating a subsurface n-p junction. Conversely, in an exemplary embodiment of variation 100C₅ a p-type doped donor semiconductor layer 120 may be doped on its surface with an n-type doping agent, creating a subsurface n-p junction.

[ 0073 ] At action 208, in FIGS. 7-9 and 15, the glass substrate 101 may be bonded to the bonding surface 126 of the exfoliation layer 122 / PVSF 102 / partially completed PVS 124. A suitable bonding process is described in U.S. Patent Application No. 2004/0229444, the entire disclosure of which is hereby incorporated by reference. Portions of this process, known as anodic bonding, electrolysis, bonding by means of electrolysis, and/or forming an anodic bond by electrolysis, are discussed below. In the anodic bonding / electrolysis process, appropriate surface cleaning of the glass substrate 101 (and the bonding surface 126 / exfoliation layer 122 if not done already) may be carried out. Thereafter, the intermediate structures are brought into direct or indirect contact to achieve the arrangement schematically illustrated in FIGS. 15-16. [0074 ] Prior to or after the contact, the structure(s) comprising the donor semiconductor wafer 120, the exfoliation layer 122 /PVSF 102 / partially completed PVS 124, and the glass substrate 101 are heated under a differential temperature gradient. The glass substrate 101 may be heated to a higher temperature than the donor semiconductor wafer 120 and exfoliation layer 122 / PVSF 102 / partially completed PVS 124. By way of example, the temperature difference between the glass substrate 101 and the donor semiconductor wafer 120 (and the exfoliation later 122 / PVSF 102 / partially completed PVS 124) is at least 1°C, although the difference may be as high as about 100 to about 150⁰C. This temperature differential is desirable for a glass having a coefficient of thermal expansion (CTE) matched to that of the donor semiconductor wafer 120

(such as matched to the CTE of silicon) since it facilitates later separation of the exfoliation layer 122 from the semiconductor wafer 120 due to thermal stresses. The glass substrate 101 and the donor semiconductor wafer 120 may be taken to a temperature within about 150⁰C of the strain point of the glass substrate 101. [ 0075] Once the temperature differential between the glass substrate 101 and the donor semiconductor wafer 120 is stabilized, mechanical pressure is applied to the intermediate assembly. The pressure range may be between about 1 to about 50 psi. Application of higher pressures, e.g., pressures above 100 psi, might cause breakage of the glass substrate 101. The appropriate pressure may be determined in light of the manufacturing parameters, such as materials being used, and their thicknesses.

[0076] Next, a voltage is applied across the intermediate assembly, for example with the donor semiconductor wafer 120 at the positive electrode and the glass substrate 101 the negative electrode. The application of the voltage potential causes alkali or alkaline earth ions in the glass substrate 101 to move away from the semiconductor/glass interface further into the glass substrate 101. This accomplishes two functions: (i) an alkali or alkaline earth ion free interface is created; and (ii) the glass substrate 101 becomes very reactive and bonds strongly to the exfoliation layer 122 of the donor semiconductor wafer 120.

[0077] At action 210₅ of FIGS . 7-9 and 15 , after the intermediate assembly is held under the above conditions for some time (e.g., approximately 1 hour or less), the voltage is removed and the intermediate assembly is allowed to cool to room temperature. The donor semiconductor wafer 120 and the glass substrate 101 are then separated, which may include some peeling if they have not already become completely free, to obtain a glass substrate 101 with the relatively thin exfoliation layer 122 / PVSF 102 / partially completed PVS 124 formed of the semiconductor material of the donor semiconductor layer 120 bonded thereto. The separation may be accomplished via fracture of the ion implantation zone due to thermal stresses. Alternatively or in addition, mechanical stresses, such as water jet or laser cutting, or chemical etching may be used to facilitate the separation.

[0078] Referring to FIG. 16, the ion migration zone 103 mentioned in reference to FIGS.

4-6 is shown in greater detail. The structural details pertain particularly to the anodic bond region at the interface of the glass substrate 101 and the layer just above it, either PVSF 102 in FIG. 4, back contact 104 in FIG. 5, or conducting window layer 110 in FIG. 6, of the exfoliation layer 122. The bonding process (action 208) transforms the interface between the exfoliation layer 122 and the glass substrate 101 into an interface region 300. The interface region 300 preferably comprises a hybrid region 160 and a depletion region 230. The interface region 300 may also include one or more positive ion pile-up regions in the vicinity of the distal edge of the depletion region 230.

[0079] The hybrid region 160 is of enhanced oxygen concentration of thickness Tl 60.

When bonding the conducting window layer 110, for instance, this hybrid region 160 may be enhanced by beginning with a composition stoichiometrically depleted of oxygen to enhance oxygen transfer from the glass substrate 101. This thickness may be defined in terms of a reference concentration for oxygen at a reference surface 170 within the exfoliation layer 122 / PVSF 102 / partially completed PVS 124. The reference surface 170 is substantially parallel to the bonding surface between the glass substrate 101 and the exfoliation layer 122 / PVSF 102 / partially completed PVS 124 and is separated from that surface by a distance DSl. Using the reference surface 170, the thickness Tl 60 of the hybrid region 160 will typically satisfy the relationship:

T160 < 200 nm,

[0080] where Tl 60 is the distance between bonding surface 126 and a surface which is:

(i) substantially parallel to bonding surface 126, and (ii) is the surface farthest from bonding surface 126 for which the following relationship is satisfied:

CO(x)-CO/Ref > 50 percent, 0 < x <T160, [ 0081] where CO(x) is the concentration of oxygen as a function of distance x from the bonding surface 126, CO/Ref is the concentration of oxygen at the above reference surface 170, and CO(x) and CO/Ref are in atomic percent.

[ 0082 ] Typically, Tl 60 will be substantially smaller than 200 nanometers, e.g., on the order of about 50 to about 100 nanometers. It should be noted that CO/Ref will typically be zero, so that the above relationship will in most cases reduce to:

CO(x) > 50 percent, 0 < x <T160.

[0083 ] In connection with the depletion region 230, the oxide glass or oxide glass- ceramic substrate 101 preferably comprises at least some positive ions that move in the direction of the applied electric field, i.e., away from the bonding surface 126 and into the glass substrate 101. Alkali ions, e.g., Li⁺¹, Na⁺¹, and/or K⁺¹ ions, are suitable positive ions for this purpose because they generally have higher mobility rates than other types of positive ions typically incorporated in oxide glasses and oxide glass-ceramics, e.g., alkaline-earth ions. [ 0084 ] However, oxide glasses and oxide glass-ceramics having positive ions other than alkali ions, e.g., oxide glasses and oxide glass-ceramics having only alkaline-earth ions, can be used in the practice of the invention. The concentration of the alkali and alkaline-earth ions can vary over a wide range, representative concentrations being between 0.1 and 40 wt. % on an oxide basis. Preferred alkali and alkaline-earth ion concentrations are 0.1 to 10 wt. % on an oxide basis in the case of alkali ions, and 0-25 wt. % on an oxide basis in the case of alkaline-earth ions. [ 0085] The electric field applied in the bonding step (action 208) moves the positive ions

(cations) further into the glass substrate 101 forming the depletion region 230. The formation of the depletion region 230 is especially desirable when the oxide glass or oxide glass-ceramic contains alkali ions, since such ions are known to interfere with the operation of semiconductor devices. Alkaline-earth ions, e.g., Mg⁺², Ca⁺², Sr⁺², and/or Ba⁺², can also interfere with the operation of semiconductor devices and thus the depletion region also preferably has reduced concentrations of these ions.

[0086] It has been found that the depletion region 230 once formed is stable over time even if the PV structure 100 is heated to an elevated temperature comparable to, or even to some extent higher than, that used in the bonding process. Having been formed at an elevated temperature, the depletion region 230 is especially stable at the normal operating and formation temperatures of PV structures. These considerations ensure that alkali and alkaline-earth ions will not diffuse back from the oxide glass or oxide glass-ceramic 101 into the semiconductor material 104 during use or further device processing, which is an important benefit derived from using an electric field as part of the bonding process. [0087 ] As with selecting the operating parameters to achieve a strong bond, the operating parameters needed to achieve a depletion region 230 of a desired width and a desired reduced positive ion concentration for all of the positive ions of concern can be readily determined by persons skilled in the art from the present disclosure. When present, the depletion region 230 is a characteristic feature of a PV structure 100 produced in accordance with one or more embodiments of the present invention. [ 0088] As illustrated in FlG. 17, after separation, the resulting structure may include the glass substrate 101 and the exfoliation layer 122 of semiconductor material bonded thereto. The cleaved surface 123 of the SOl structure just after exfoliation may exhibit excessive surface roughness 123 A (depicted abstractly in FIG. 17), possible excessive silicon layer thickness (more likely for microelectronic applications), and implantation damage of the silicon layer (e.g., due to hydrogen ions and the formation of an amorphized silicon layer).

[ 0089 ] At action 212, in FIGS. 7-9 and 18, the donor semiconductor wafer 120, PVSF

102, and/or partially completed PVS 124 may be subjected to one or more finishing process(es) 130. The finishing process 130 may include, for example, one or more subprocesses. For instance, a finishing process 130 may include various scribing steps needed to create the topography of PVS variations IOOB and lOOC. Such scribing steps, well known in the art, may be done before, after, or in conjunction with other finishing processes 130. [0090] Another finishing process 130 may include augmenting the semiconductor thickness of the exfoliation layer 122. In the case of variation 10OA, semiconductor material may be added, for example, before mesotaxial growth of a back contact layer 104. It is desired in certain embodiments that the final combined thickness of the semiconductor layers 106 and 108 should be, for example, more than 10 microns (i.e., 10000 nm) and less than about 30 microns. Therefore, an appropriately thick exfoliation layer 122 should be created and augmented with an additional semiconductor layer 132 (e.g., of Si) until the desired thickness is created. Augmentation with an additional Si layer 132 may include a doping step as well. Historically, the amorphized silicon layer has been on the order of about 50-150 nm in thickness, and depending on the implantation energy and implantation time, the thickness of the exfoliation layer 122 has been on the order of about 500 nm. As with microelectronic SOI structures, however, a thinner exfoliation layer 122 may be created for the PVSF 102, with the amorphized silicon layer necessarily being thinner as well, with more semiconductor material added in the finishing processes.

[0091] Also according to action 212, the cleaved surface 123 may subject to post- cleaving processing which may include subjecting the cleaved surface 123 to a polishing or annealing process to reduce roughness 123 A. Moreover, in order to achieve the exemplary embodiment of variation IOOB, the finishing process may include application of the conducting window layer 110, such as deposition of indium tin oxide. Conversely, to achieve the exemplary embodiment of variation lOOC, the finishing process may include application of the back contact layer 104, a conductive metal-based or metal oxide-based layer, such as an aluminum-based film deposited by LPE, CVD or PECVD. As discussed above, back contact layer 104 also may be formed by epitaxial or mesotaxial growth, such as of nickel silicide.

[0092] To the extent that the partially completed PVS 124 has more of the features of the intended final product, fewer finishing processes are necessary. By contrast, insofar as the formation of PVSF 102 on insulator substrate 101 alone does not distinguish the substrate 101- PVSF 102 combination as a photovoltaic structure over any other semiconductor-on-insulator structure of U.S. Patent Application No.: 2004/0229444, several PVS-specific finishing processes are necessary. However, having a substantially single crystal layer as the photovoltaic structure foundation 102 relaxes the .parameters within which to operate and expands the scope of options and outcomes available from which to choose, in proceeding with the finishing processes. [0093] In particular, formation of the PVSF 102 or the partially completed PVS 124 allows for greater flexibility in the creation of advanced, multi-junction PVS devices. For example, building on a PVSF 102 of crystal-Si, a manufacturer may exploit the different specific heat capacities of crystal-Si versus GaAs, Ge, and GaInP₂ to create various multi-junction layers of GaAs, Ge and GaInP₂. Optionally, as the preferred embodiments of FIG. 21 describe, the PVSF 102 may comprise Ge, or GaAs₅ or the PCPVS 124 may comprise a doped Ge/GaAs layer. [0094] Alternative embodiments of the invention will now be described with reference to the aforementioned SiOG processes and further details. For example, a result of separating the exfoliation layer 122 from the donor semiconductor wafer 120 may produce a first cleaved surface of the donor semiconductor wafer 120 and a second cleaved surface 123 of the exfoliation layer 122. As previously discussed, the finishing process 130 may be applied to the second cleaved surface 123 of the exfoliation layer 122. Additionally or alternatively, the finishing process 130 may be applied to the first cleaved surface of the donor semiconductor wafer 120 (using one or more of the techniques described above), such as polishing.

[ 0095] In another embodiment of the present invention, the donor semiconductor wafer

120 may be part of a donor structure, including a substantially single-crystal donor semiconductor wafer 120, and an epitaxial semiconductor layer disposed on the donor semiconductor wafer 120. (Details of an epitaxially grown semiconductor layer in an SOI context may be found in co- pending U.S. Patent Application No.: 11/159,889, filed June 23, 2005, the entire disclosure of which is incorporated herein by reference.) The exfoliation layer 122, therefore, may be formed substantially from the epitaxial semiconductor layer (and may also include some of the single- crystal donor semiconductor material from the wafer 120). Thus, the aforementioned finishing process may be applied to the cleaved surface 123 of an exfoliation layer 122 formed substantially of epitaxial semiconductor material and/or a combination of epitaxial semiconductor material and single-crystal semiconductor material. [ 0096 ] The photovoltaic cell creation process of one or more embodiments of the present invention could be automated, moreover, in a system for the formation of photovoltaic structures 100. The system could include a PVS handling assembly, which handles the PV structures 100 for processing, and a photovoltaic processing assembly. The photovoltaic processing assembly would include various subsystems, such as a preparing or finishing system and a transferring or bonding system, used in manufacturing PV structures 100 being handled by the PV semiconductor-on-insulator handling assembly.

[ 0097 ] For example, when the exfoliation layer 122 is prepared, comprising either the

PVSF 102 or partially completed PV structure 124, the handling assembly could transport and position the PV structures 100 in need of completion within the PVS processing assembly to permit anodic bonding to occur. Further transportation and positioning of the substrate 101, bonded to PVSF 102 or partially completed PVS 124, within the PVS processing assembly may allow additional actions 210 and 212 of exfoliating and finishing, respectively, to occur. [ 0098] Referring to FIG. 19, a simplified multifunction variation 10OD of PVS 100 is depicted according to one or more preferred embodiments . Multijunction PVS 10OD may bear a general resemblance to the PVS of FIG.3, but with important exceptions, such as the substitution of a glass substrate 101 for the crystal-Ge wafer substrate, with an exfoliated crystal-Ge film on top of the glass substrate. A p-type germanium or a GaAs wafer 500 microns thick with a resistivity of 0.01-0.04 Ohm-Cm may be implanted with hydrogen at 1 OOKev and a dosage of 8xlO¹⁶. The wafer then may be cleaned by chemical means and subjected to oxygen plasma treatment to oxidize the surface groups. Following cleaning, the GaAs wafer may be inserted into the deposition chamber and coated with a layer of doped or undoped Ge film, the thickness depending on the device design. Deposition of germanium onto the GaAs wafer may be accomplished with a variety of techniques including plasma enhanced chemical vapor deposition, ion beam assisted sputter deposition, evaporation or chemical vapor phase epitaxy. Doping (p- type) of the Ge layers can be accomplished with As or P. An alkali-aluminoborosilicate glass wafer with thermal expansion matched to germanium and thickness of lmm then may be washed with standard cleaning techniques, such as with a detergent and distilled water followed by a dilute acid wash to clean the surface. The two wafers then may be brought into contact and placed in a bonding system. A voltage of 1000V may be applied across the wafers at 450C and 400C, the temperatures of the glass and germanium wafer or Ge-coated GaAs wafer, respectively, for 20 minutes before cooling down and removing the applied voltage. A thin film of germanium or a multilayer of GaAs/Ge bonded to the glass may be separated from the mother wafer, with very strong bonding to the glass being achieved. Thus in this FIG. 19, the reference numerals can have the following meaning: 101: glass substrate; 104: doped Ge film as the back-contact layer; 105: GaAs tunnel junction; 106: p-type GaAs; 108: n-type GaAs or GaInP; 107: AlGaAs tunnel junction;

110: conducting window layer.

[0099] The glass wafer with the germanium or GaAs/Ge film optionally then may be polished, annealed or healed to remove the damaged germanium or GaAs top layer and a good quality layer surface. This wafer may be used as a substrate to grow epitaxial structures to form the solar cell. Examples of materials may include GaAs, GalnP/GaAs, Ga_xIUyPZGa₀, In_dAs/Ge and others known in the art-. Various processes may be utilized to deposit the epitaxial films including CVST (closed space vapor transport), MOCVD (metallo-organic chemical vapor deposition), MBE (molecular beam epitaxy) and others known in the art. A number of surface passivating window layers such as wide bandgap epilayers of AlGaAs, InGaP or ZnSe may be employed as well as other encapsulating or passivation layers and surface treatments may be used to complete the cell.

[ 00100] The ohmic contacts may be applied in varying configurations, depending on the device design, but the basic requirement is that the produced current flow from one contact to the next contact to allow for a completed electric circuit, the circuit being completed once the two electrodes leading from the device are coupled with a load. As such, the back contact layer need not be the outermost layer relative to the semiconductor layers, as depicted in FIG. 6. For instance, the back contact 104 may rest on top, rather than underneath, semiconductor layer 106, ^• if spaced appropriately to create a proper circuit and electrical flow configuration.

[00101] Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims

1. A photovoltaic device, comprising: an insulator structure; an exfoliation layer; and a conductive layer integral to the exfoliation layer and proximate to the insulator structure; and a bond bonding the insulator structure to the conductive layer and the exfoliation layer, wherein the exfoliation layer comprises a substantially single-crystal exfoliation layer of a substantially single-crystal donor semiconductor wafer.

2. The photovoltaic device of claim 1 , wherein the exfoliation layer is based on a single-crystal material selected from silicon (Si), germanium-doped silicon (SiGe), silicon carbide (SiC), germanium (Ge), gallium arsenide (GaAs), gallium phosphide (GaP), and indium phosphide (InP).

3. The photovoltaic device of claim 1 or claim 2, wherein the bond bonding the insulator structure to the conductive layer and the exfoliation layer is an anodic bond comprising an interface region.

4. The photovoltaic device of claim 3, wherein the interface region comprises a hybrid region and a depletion region.

5. The photovoltaic device of any one of the preceding claims, further comprising: a first ion migration zone in the insulator; and a second ion migration zone across the conductive layer and the exfoliation layer.

6. The photovoltaic device of any one of the preceding claims, wherein the conductive layer comprises a metal-based material or a metal-oxide based material.

7. The photovoltaic device of any one of the preceding claims, wherein the exfoliation layer comprises a doped semiconductor layer and the conductive layer comprises a back contact layer or a conducting window layer.

8. The photovoltaic device of claim 7, wherein the doped semiconductor layer comprises an n-type semiconductor layer, a p-type semiconductor layer, or a semiconductor junction layer having n-type and ρ-tyρe doped regions.

9. The photovoltaic device of claim 7, wherein: the back contact layer comprises aluminum, titanium, nickel, tungsten, indium, molybdenum, gold, platinum, palladium, gallium, tin, antimony, silver, germanium, or a suicide; and the conducting window layer comprises tin-doped indium oxide, aluminum-doped zinc oxide, boron-doped zinc oxide, or carbon nanotubes.

10. The photovoltaic device of any one of the preceding claims, further comprising a plurality of photovoltaic device layers created in or on the exfoliation layer and distal to the insulator substrate.

11. The photovoltaic device of claim 10, wherein the plurality of photovoltaic device layers includes at least one semiconductive layer, at least one conductive layer, and at least one passivating layer.

12. The photovoltaic device of claim 10, wherein at least one of the plurality of photovoltaic device layers comprises an epitaxially grown crystalline layer.

13. The photovoltaic device of claim 1 , further comprising at least one additional photovoltaic device layer integral to the exfoliation layer and proximate to the insulator substrate.

14. A photovoltaic device any one of the preceding claims, comprising: an insulator structure; an exfoliation layer proximate to the insulator structure; an anodic bond bonding the insulator structure and the exfoliation layer; and a plurality of photovoltaic device layers distal to the insulator substrate and in or on the exfoliation layer; wherein the exfoliation layer comprises a substantially single-crystal exfoliation layer of a substantially single-crystal donor semiconductor wafer.

15. The photovoltaic device of claim 14, further comprising: a first ion migration zone in the insulator; and a second ion migration zone in the exfoliation layer.

16. The photovoltaic device of claim 14 or claim 15, wherein the anodic bond comprises an interface region.

17. The photovoltaic device of claim 16, wherein the interface region comprises a hybrid region and a depletion region.

18. The photovoltaic device of any one of claims 14 to 17, wherein the plurality of photovoltaic device layers includes a semiconductive layer and a conductive layer.

19. The photovoltaic device of claim 18, wherein the plurality of photovoltaic device layers further includes at least one more semiconductive layer, at least one more conductive layer, and at least one passivating layer.

20. The photovoltaic device of claim 18, wherein the conductive layer comprises a metal-based material or a metal-oxide based material.

21. The photovoltaic device of claim 14, wherein the plurality of photovoltaic device layers includes a doped semiconductor layer, a back contact layer and a conducting window layer.

22. The photovoltaic device of claim 21 , wherein the doped semiconductor layer comprises an n-type semiconductor layer, a p-type semiconductor layer, or a semiconductor junction layer having n-type and p-type doped regions.

23. The photovoltaic device of claim 21 , wherein: the back contact layer comprises aluminum, titanium, nickel, tungsten, indium, molybdenum, gold, platinum, palladium, gallium, tin, antimony, silver, germanium, or a silicide; and the conducting window layer comprises tin-doped indium oxide, aluminum-doped zinc oxide, boron-doped zinc oxide, or carbon nanotubes.

24. The photovoltaic device of claim 14, wherein at least one of the plurality of photovoltaic device layers comprises an epitaxially grown crystalline layer.

25. A method of forming a photovoltaic structure, the method comprising: creating on a donor semiconductor wafer an exfoliation layer having a conductive layer; and - transferring the exfoliation layer to an insulator substrate.

26. The method of claim 25, further comprising: subjecting the donor semiconductor wafer to an ion implantation process to create the exfoliation layer of the donor semiconductor wafer; bonding the exfoliation layer to the insulator substrate; and separating the exfoliation layer from the donor semiconductor wafer, thereby exposing an at least one cleaved surface.

27. The method of claim 26, further comprising subjecting the at least one cleaved surface to a plurality of finishing processes.

28. The method of claim 27, wherein the at least one cleaved surface includes a first cleaved surface of the donor semiconductor wafer and a second cleaved surface of the exfoliation layer.

29. The method of claim 28, wherein the plurality of finishing processes is applied to at least the second cleaved surface of the exfoliation layer.

30. The method of claim 28, wherein the plurality of finishing processes is applied to at least the first cleaved surface of the donor semiconductor wafer.

31. The method of claim 27, wherein the plurality of finishing processes is selected from a group including scribing, creating a back contact layer, creating a conducting window layer, polishing, annealing, cleaning, doping, creating a passivating layer, creating an encapsulating layer, and adding additional semiconductor material.

32. The method of claim 26, wherein the step of bonding includes: heating at least one of the insulator substrate and the donor semiconductor wafer; bringing the insulator substrate into direct or indirect contact with the exfoliation layer of the donor semiconductor wafer; pressing together the insulator substrate and the exfoliation layer; and applying a voltage potential across the insulator substrate and the donor semiconductor wafer to induce the bond.

33. The method of any one of claims 25 to 32, wherein the donor semiconductor wafer comprises substantially single-crystal donor semiconductor wafer comprising silicon, germanium, or gallium-arsenide.

34. ^■ The method of any one of claims 25 to 32, wherein the .donor semiconductor wafer is taken from the group consisting of: silicon (Si), germanium-doped silicon (SiGe), silicon carbide (SiC), germanium (Ge), gallium arsenide (GaAs), gallium phosphide (GaP), and indium phosphide (InP).

35. The method of any one of claims 25 to 32, wherein the donor semiconductor wafer includes a substantially single-crystal donor semiconductor wafer, and the separated exfoliation layer is formed substantially from the single-crystal donor semiconductor wafer material.

36. The method of any one of claims 25 to 32, wherein the donor semiconductor wafer includes a donor semiconductor wafer and an epitaxial semiconductor layer disposed on the donor semiconductor wafer, and the separated exfoliation layer is formed substantially from the epitaxial semiconductor layer.

37. The method of any one of claims 25 to 32, wherein creating the exfoliation layer having the conductive layer involves one or more of epitaxy, mesotaxy, exfoliation, vapor transport, vapor deposition, ion implantation, and oxidation.

38. The method of any one of claims 25 to 32, wherein the conductive layer comprises a metal-based material or a metal-oxide based material.

39. The method of any one of claims 25 to 32, wherein the exfoliation layer comprises a doped semiconductor layer and the conductive layer comprises a back contact layer or a conducting window layer.

40. The method of any one of claims 25 to 32, wherein the doped semiconductor layer comprises an n-type semiconductor layer, a p-type semiconductor layer, or a semiconductor junction layer having n-type and p-type doped regions.

41. The method of claim 39, wherein: the back contact layer comprises aluminum, titanium, nickel, tungsten, indium, molybdenum, gold, platinum, palladium, gallium, tin, antimony, silver, germanium, or a suicide; and the conducting window layer comprises tin-doped indium oxide, aluminum-doped zinc oxide, boron-doped zinc oxide, or carbon nanotubes.

42. The method of any one of claims 25 to 41 , wherein the photovoltaic structure comprises a single-junction photovoltaic structure or multi-junction photovoltaic structure.

43. The method of any one of claims 25 to 41, further comprising subjecting the exfoliation layer to at least one finishing process prior to transferring the exfoliation layer to the insulator substrate.

44. The method of claim 43, wherein the at least one finishing process creates at least one additional photovoltaic device layer prior to transferring the exfoliation layer to the insulator substrate.

45. A method of forming a photovoltaic structure of any one of claims 25 to 44, the method comprising: subjecting a donor semiconductor wafer to an ion implantation process to create an exfoliation layer on the donor semiconductor wafer; forming an anodic bond between the exfoliation layer and the insulator substrate by means of electrolysis; separating the exfoliation layer from the donor semiconductor wafer, thereby exposing an at least one cleaved surface; and creating a plurality of photovoltaic structure layers proximate to the exfoliation layer and distal to the insulator substrate.

46. The method of claim 45, further comprising subjecting the at least one cleaved surface to a plurality of finishing processes, wherein creating the plurality of photovoltaic structure layers includes at least one of the plurality of finishing processes.

47. The method of claim 46, wherein the at least one cleaved surface includes a first cleaved surface of the donor semiconductor wafer and a second cleaved surface of the exfoliation layer.

48. The method of claim 47, wherein the plurality of finishing processes is applied to at least the second cleaved surface of the exfoliation layer.

49. The method of claim 47, wherein the plurality of finishing processes is applied to at least the first cleaved surface of the donor semiconductor wafer.

50. The method of claim 46, wherein the plurality of finishing processes is selected from a group including scribing, creating a back contact layer, creating a conducting window layer, polishing, annealing, cleaning, doping, creating a passivating layer, creating an encapsulating layer, and adding additional semiconductor material.

51. The method of claim 45, wherein the step of forming an anodic bond by means of electrolysis includes: heating at least one of the insulator substrate and the donor semiconductor wafer; bringing the insulator substrate into direct or indirect contact with the exfoliation layer of the donor semiconductor wafer; pressing together the insulator substrate and the exfoliation layer; and applying a voltage potential across the insulator substrate and the donor semiconductor wafer to induce the anodic bond.

52. The method of claim 45, wherein the donor semiconductor wafer comprises a substantially single-crystal donor semiconductor wafer comprising silicon, germanium, or gallium arsenide.

53. The method of claim 45, wherein the donor semiconductor wafer is taken from the group consisting of: silicon (Si), germanium-doped silicon (SiGe), silicon carbide (SiC), germanium (Ge), gallium arsenide (GaAs)₃ gallium phosphide (GaP), and indium phosphide

^■ (InP)-

54. The method of claim 45, wherein the donor semiconductor wafer includes a substantially single-crystal donor semiconductor wafer, and the separated exfoliation layer is formed substantially from the single-crystal donor semiconductor wafer material.

55. The method of claim 45, wherein the donor semiconductor wafer includes a donor semiconductor wafer and an epitaxial semiconductor layer disposed on the donor semiconductor wafer, and the separated exfoliation layer is formed substantially from the epitaxial semiconductor layer.

56. The method of claim 45, wherein creating the plurality of photovoltaic structure layers involves one or more of epitaxy, mesotaxy, exfoliation, vapor transport, vapor deposition, ion implantation, and oxidation.

57. The method of claim 45, wherein the plurality of photovoltaic structure layers includes a semiconductive layer and a conductive layer.

58. The method of claim 33, wherein the conductive layer comprises a metal-based material or a metal-oxide based material.

59. The method of claim 45, wherein the plurality of photovoltaic structure layers includes a doped semiconductor layer, a back contact layer and a conducting window layer.

60. The method of claim 35, wherein the doped semiconductor layer comprises an n- type semiconductor layer, a p-type semiconductor layer, or a semiconductor junction layer having n-type and p-type doped regions.

61. The method of claim 35, wherein: the back contact layer comprises aluminum, titanium, nickel, tungsten, indium, molybdenum, gold, platinum, palladium, gallium, tin, antimony, silver, germanium, or a silicide; and the conducting window layer comprises tin-doped indium oxide, aluminum-doped zinc oxide, boron-doped zinc oxide, or carbon nanotubes.

62. The method of claim 45, wherein the photovoltaic structure comprises a single- junction photovoltaic structure or multi-junction photovoltaic structure.

63. A system for the formation of photovoltaic structures, the system comprising: a photovoltaic structure handling assembly, and a photovoltaic structure processing assembly, wherein the photovoltaic structure processing assembly comprises a preparing system and a transferring system, wherein the preparing system prepares exfoliation layers being handled by the photovoltaic structure handling assembly, and the transferring system transfers the exfoliation layers to insulator substrates.

64. The system of claim 63, wherein each exfoliation layer has a conductive layer prior to being transferred to the insulator substrate.

65. The system of claim 63 or claim 64, further comprising a bonding system, wherein the bonding system is configured to form an anodic bond between the insulator substrate and the exfoliation layer by means of electrolysis.

66. The system of any one of claims 63 to 65, further comprising a finishing system, wherein the finishing system is configured to perform at least one finishing process selected from a group including scribing, creating a back contact layer, creating a conducting window layer, • polishing, annealing, cleaning, doping, creating a passivating layer, creating an encapsulating layer, and adding additional semiconductor material.