WO2007145728A2 - A test structure and probe for differential signals - Google Patents
A test structure and probe for differential signals Download PDFInfo
- Publication number
- WO2007145728A2 WO2007145728A2 PCT/US2007/010801 US2007010801W WO2007145728A2 WO 2007145728 A2 WO2007145728 A2 WO 2007145728A2 US 2007010801 W US2007010801 W US 2007010801W WO 2007145728 A2 WO2007145728 A2 WO 2007145728A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- probe pad
- probe
- output signal
- signal probe
- input signal
- Prior art date
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Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2607—Circuits therefor
- G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2822—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere of microwave or radiofrequency circuits
Definitions
- the present invention relates to wafer probing and, more particularly, to probes and test structures for wafer probing with differential signals.
- Integrated circuits are economically attractive because large numbers of often complex circuits, for example microprocessors, can be inexpensively fabricated on the surface of a wafer or substrate.
- individual dies including one or more circuits, are separated or singulated and encased in a package that provides for electrical connections between the exterior of the package and the circuit on the enclosed die.
- the separation and packaging of a die comprises a significant portion of the cost of manufacturing the integrated circuit device and to monitor and control the IC fabrication process and avoid the cost of packaging defective dies, manufacturers commonly add electrical circuits or test structures to the wafer to enable on-wafer testing or "probing" to verify the characteristics of the integrated circuits before the dies are singulated.
- a test structure typically includes a device-under-test (DUT), a plurality of metallic probe or bond pads that are deposited at the wafer's surface and a plurality of conductive vias that connect the bond pads to the DUT which is typically fabricated beneath the surface of the wafer.
- the DUT typically comprises a simple circuit that includes a copy of one or more of the basic elements of the integrated circuit, such as a single line of conducting material, a chain of vias or a single transistor.
- the circuit elements of the DUT are typically produced with the same process and in the same layers of the die as the corresponding elements of the integrated circuit.
- the ICs are typically characterized "on-wafer" by applying a test instrument generated signal to the test structure and measuring the response of the test structure to the signal. Since the circuit elements of the DUT are fabricated with the same process as the corresponding elements of the integrated circuit, the electrical properties of the DUT are expected to be representative of the electrical properties of the corresponding components of the integrated circuit.
- the network analyzer comprises a source of an AC signal, commonly, a radio frequency (RF) signal, that is used to stimulate the DUT of a test structure.
- RF radio frequency
- a forward- reverse switch directs the stimulating signals to one or more of the bond pads of the test structure.
- Directional couplers or bridges pick off the forward or reverse waves traveling to or from the test structure.
- IF intermediate frequency
- the result is a plurality of s-pararneters (scattering parameters), the ratio of a normalized power wave comprising the response of the DUT to a normalized power wave comprising the stimulus supplied by the signal source.
- the preferred interconnection for communicating the signals between the signal source and the receiver of the network analyzer and the test structure is coaxial cable.
- the transition between the coaxial cable and the bond pads of the test structure is preferably provided by a movable probe having one or more conductive probe tips that are arranged to be co-locatable with the bond pads of the test structure.
- the network analyzer and the test structure can be temporarily interconnected by bringing the probe tips into contact with the bond pads of the test structure.
- Integrated circuits typically comprise a ground plane at the lower surface of the substrate on which the active and passive devices of the circuit are fabricated.
- the terminals of transistors fabricated on a semi-conductive substrate are typically capacitively interconnected, through the substrate, to the ground plane.
- the impedance of this parasitic capacitive interconnection is frequency dependent and at higher frequencies the ground potential and the true nature of ground referenced (single ended) signals becomes uncertain.
- confidential Balanced devices are more tolerant to poor radio frequency (RF) grounding than single ended devices making them attractive for high performance ICs.
- a differential gain cell 20 is a balanced device comprising two nominally identical circuit halves 2OA, 2OB.
- a virtual ground is established at the symmetrical axis 28 of the two circuit halves.
- the potential at the operating frequency does not change with time regardless of the amplitude of the stimulating signal.
- the quality of the virtual ground of a balanced device is independent of the physical ground path and, therefore, balanced or differential circuits can tolerate poor RF grounding better than circuits operated with single ended signals.
- the two waveforms of the differential output signal (So +1 and So" 1 ) 30, 32 are mutual references providing greater certainty in determining the transition from one binary value to the other and permitting a reduction the voltage swing of the signal and faster transition between binary values.
- differential devices can operate at lower signal power and higher data rates than single ended devices.
- noise from external sources, such as adjacent conductors tends to couple, electrically and electromagnetically, in the common mode and cancel in the differential mode.
- balanced or differential circuits have good immunity to noise including noise at even-harmonic frequencies since signals that are of opposite phase at the fundamental frequency are in phase at the even harmonics. Improved tolerance to poor RF grounding, increased resistance to noise and reduced signal power make differential devices attractive for operation at higher frequencies.
- a DUT comprising a differential gain cell provides a basis for a test structure enabling high frequency, on-wafer evaluation of devices included in the marketable integrated circuits fabricated on the wafer.
- the impedance of the internal connections of the DUT's components are often frequency dependant complicating de-embedding of the DUT and affecting the accuracy of the testing.
- the input and output of a differential gain cell, such as the differential gain cell 20 are commonly capacitively interconnected as a result of parasitic capacitance connecting the terminals of the cell's transistors.
- Parasitic capacitance 42 between the gate 38, 40 and the drain 34, 36 a result of diffusion of the drain dopant under the oxide of the gate, is intrinsic and typical of MOS transistors. As a result to the transistor's gain, a change in the gate voltage produces an even larger change in the voltage at the transistor's drain.
- the application of differing voltages at the terminals of the parasitic gate- to-drain capacitor (C gd ) causes the capacitor to behave as a much larger capacitance, a phenomenon known as the Miller effect.
- input impedance of the differential device varies substantially with frequency, producing instability in the operation of the differential device.
- FIG. 1 is schematic diagram of a balanced device.
- FIG. 2 is a schematic illustration of a probe and a differential test structure comprising field effect transistors and a pair of Miller effect neutralizing capacitors.
- FIG. 3 is a schematic illustration of a probe and a differential test structure comprising bipolar junction (BJT) transistors and a pair of Miller effect neutralizing capacitors.
- BJT bipolar junction
- FIG. 4 is a perspective view of a test structure and a probe.
- FIG. 5 is a schematic illustration of a differential test structure for go-no go testing of the functionality of a transistor.
- a differential gain cell 20 is a balanced device comprising two nominally identical circuit halves 2OA, 2OB.
- a DC current source 22 When biased, with a DC current source 22, and stimulated with a differential mode signal, comprising even and odd mode components of equal amplitude and opposite phase (S 1 +1 and S 1 '1 ) 24, 26, a virtual ground is established at the symmetrical axis 28 of the two circuit halves. At the virtual ground, the potential at the operating frequency does not change with time regardless of the amplitude of the stimulating signal.
- the quality of the virtual ground of a balanced device is independent of the physical ground path and, therefore, balanced or differential circuits can tolerate poor RF grounding better than circuits operated with single ended (ground referenced) signals.
- Differential devices can also typically operate with lower signal power and at higher data rates than single ended devices and have good immunity to noise from external sources, such as adjacent conductors, including noise at even-harmonic frequencies.
- Integrated circuits are fabricated by depositing layers of semi-conductive and insulating materials on a semi-conductive substrate and intrinsic frequency dependent connections commonly exist between the various elements of the fabricated devices.
- One such intrinsic frequency dependent connection connects the gates and drains of MOS transistors and the bases and collectors of bipolar junction (BJT) transistors.
- BJT bipolar junction
- an intrinsic parasitic capacitance (Cgd) interconnects the gate and the drain of a typical MOS transistor because the drain dopant diffuses under the oxide comprising the transistor's gate.
- the impedance between gate and drain of the transistor and, therefore, the input impedance of the differential gain cell changes.
- any change in voltage at the gate of the transistor is amplified at the drain of the transistor causing the parasitic capacitance (C gd ) to appear to be a much larger capacitor; a phenomenon known as the Miller effect.
- the inventors realized that the signals conducted by the respective transistors of the differential gain cell are mirror images and concluded that the Miller effect could be minimized or eliminated and the input impedance of a test structure comprising a differential gain cell stabilized connecting the gate of one transistor to the drain of the second transistor with a capacitor having a value equal to the parasitic gate-to-drain capacitance (C gd ).
- a test structure 50 comprises a differential gain cell 51 including transistors 52A, 52B.
- the gates of the respective transistors are connected to probe pads 54, 56
- Probe tips 64, 66 arranged to be co-locatable with the probe pads are connected to a source 74 of a differential input signal comprising the component signal, S *1 ' and its differential complement signal, Sf 1 .
- the source of the differential signal is typically a radio frequency (RF) source included in a network analyzer 76.
- the network analyzer also includes a sink 78 for the output signal of the test structure comprising components S 0 +1 and S 0 "1 .
- the respective components of the output signal are transmitted from the drains of the transistors to probe pads 58, 60 which are connectible to the signal sink through probe tips 68, 70.
- the sources of the transistors are interconnected and connected to a bias probe pad 62 which is e ⁇ gageable with a probe tip 72.
- the probe tip is interconnected to a DC current source 80 that provides the bias for the differential gain cell.
- Intrinsic in each transistor 52A, 52B is parasitic capacitance (C gd ) 82A, 82B interconnecting the respective gates and drains which comprise respectively the input terminals and the output terminals of the test structure.
- C gd parasitic capacitance
- the gain (A) of the transistor a change in voltage (dV) at the gate of a transistor is amplified at the drain (A*dV) causing the opposing sides of the parasitic capacitance to experience differing voltage.
- the parasitic capacitance (C gd ) has the effect of a larger capacitor causing the input impedance of the test structure to vary substantially with frequency.
- a compensating capacitor 84A, 84B is connected from the gate of each transistor, for example the gate of transistor 52A, to the drain of the second transistor of the differential gain cell, for example the drain of transistor 52B.
- the compensating capacitor has a value equal to the value of C gc j.
- the change in voltage at the drain of a transistor due to the gate-to-drain capacitance, for example, A*dV, is offset by the voltage at the compensating capacitor # (-A*dV) and the input impedance of the test structure remains constant.
- a test structure 100 comprises a differential gain cell 102 comprising bipolar junction (BJT) transistors 104A, 104B connected in a common emitter configuration.
- the bases of the transistors are connected to probe pads 106, 108 that are engageable by probe tips 106, 108 interconnected to a source 126 of a differential signal comprising the component input signals (Sj +1 and Sf 1 ).
- the collectors of the transistors are connected to probe pads 110, 112 which are engageable by probe tips 120, 122 which are interconnected to a sink 128 for the output signal of the differential cell comprising the component signals (S 0 +1 and S 0 "1 ).
- the emitters of the matched transistors are interconnected and connected through a probe tip 124, contactable with a bias probe pad 114, to a DC current source 130 that biases the differential gain cell.
- Each BJT includes parasitic base-to-collector capacitance (C bc ) 132 that comprises a frequency dependent interconnection between an input and an output of the test structure.
- C bc parasitic base-to-collector capacitance
- a compensating capacitor 134 having a value equal to C bc interconnects the gate of each of the transistors 104A, 104B respectively to the collector of the other transistor of the differential gain cell.
- the compensating capacitors may be fabricated on the wafer as part of the test structure enabling consistent matching to the parasitic capacitance of the transistors.
- the compensating capacitors may be connected across the respective probe tips arranged to engage the appropriate probe pads.
- differential probing is performed with two probes.
- the differential test structure 200 comprises at least four bond or probe pads, including probe pads 202, 204 for the input signal components and probe pads 206, 208 for the output signal components that are arranged in a linear array and connected to the DUT 212, which is fabricated below the surface of a wafer 214, by a plurality of conductive vias 216.
- the fifth probe pad 210, through which the DUT is biased, is preferably fabricated within the linear array but could be offset.
- the linear arrangement of probe pads also enables probing with a single probe comprising a linear array of at least four probe tips 222, 224, 226, 228 which may be fabricated on the surfaces of a dielectric plate 232 and which are arranged to be co-Iocatable with the probe pads for the input and output signals.
- the fifth probe tip 230, through which the DUT is biased, is preferably fabricated in the linear array probe tips but could be offset or arranged at a different angle to the wafer.
- the linear arrangement of probe tips facilitates fabrication of conductors 234 and compensating capacitors 236 interconnecting the probe tips 222, 224 transmitting the input signals and the probe tips 226, 228 transmitting the output signals for the two transistors of the differential gain cell of the DUT.
- an easily tested go-no go test structure 150 comprising a differential gain cell 152 having circuit elements fabricated with the same process and in the same layers of the wafer as their counterpart elements of the marketable integrated circuits.
- the test structure comprises compensating capacitors 156 connecting the gate of each transistor 154A 1 154B to the drain of its counterpart, respectively 154B, 154A 1 to neutralize the Miller effect originating with the parasitic gate-to-drain capacitance (C gd ) and stabilize the input impedance of the test structure.
- a resistor network comprising resistors 178 connect the signal input probe tips 168, 170, arranged to engage the input probe pads 158, 160, and the signal source 74.
- the signal output probe pads 162, 164 are connected to the signal sink 78 through probe tips 172, 174 and resistors 182, 184.
- the test structure is biased through the probe pad 166 and the probe tip 176 which is connected to ground through the bias resistor 186.
- the resistors at all terminations stabilize the DC operation of the amplifier and prevent it from oscillating by reducing the Q factor of resonances produced by the capacitive and inductive interconnections of the device parasitics.
- the values of the resistors are selected to provide stability and a convenient level of gain, preferably, approximately unity. Data is collected by testing a plurality transistor pairs known to be good. Comparing this data to data obtained by testing on-wafer test structures provides a go-no go gauge of transistor functionality that can be easily used during the production process.
- the input impedance of a test structure comprising a differential gain cell is stabilized by interconnecting the gate of one transistor and the drain of the second transistor of the differential pair with a capacitor having a value approximating the parasitic gate-to-drain (base-to-collector) capacitance of the device.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009515391A JP4870211B2 (en) | 2006-06-12 | 2007-05-03 | Differential signal test structure and probe |
DE112007001435T DE112007001435T5 (en) | 2006-06-12 | 2007-05-03 | Test structure and probe for differential signals |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US81311906P | 2006-06-12 | 2006-06-12 | |
US60/813,119 | 2006-06-12 | ||
US11/710,149 | 2007-02-22 | ||
US11/710,149 US7403028B2 (en) | 2006-06-12 | 2007-02-22 | Test structure and probe for differential signals |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2007145728A2 true WO2007145728A2 (en) | 2007-12-21 |
WO2007145728A3 WO2007145728A3 (en) | 2008-05-02 |
Family
ID=38832257
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/010801 WO2007145728A2 (en) | 2006-06-12 | 2007-05-03 | A test structure and probe for differential signals |
Country Status (3)
Country | Link |
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JP (1) | JP4870211B2 (en) |
DE (2) | DE112007001435T5 (en) |
WO (1) | WO2007145728A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103117536A (en) * | 2013-01-15 | 2013-05-22 | 费新华 | Storage battery protective circuit |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE202005021435U1 (en) | 2004-09-13 | 2008-02-28 | Cascade Microtech, Inc., Beaverton | Double-sided test setups |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5940965A (en) * | 1995-02-03 | 1999-08-24 | Hewlett-Packard Company | Method of making multiple lead voltage probe |
US20040140819A1 (en) * | 2003-01-21 | 2004-07-22 | Mctigue Michael T. | Differential voltage probe |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001242214A (en) * | 2000-02-28 | 2001-09-07 | Asahi Kasei Microsystems Kk | Characteristic measuring circuit of semiconductor |
JP2002057288A (en) * | 2000-08-09 | 2002-02-22 | Rohm Co Ltd | Semiconductor integrated circuit device |
JP4151572B2 (en) * | 2003-12-16 | 2008-09-17 | 株式会社デンソー | Transistor pair characteristic difference measuring device and characteristic difference measuring method |
-
2007
- 2007-05-03 DE DE112007001435T patent/DE112007001435T5/en not_active Withdrawn
- 2007-05-03 JP JP2009515391A patent/JP4870211B2/en not_active Expired - Fee Related
- 2007-05-03 DE DE200720018748 patent/DE202007018748U1/en not_active Expired - Lifetime
- 2007-05-03 WO PCT/US2007/010801 patent/WO2007145728A2/en active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5940965A (en) * | 1995-02-03 | 1999-08-24 | Hewlett-Packard Company | Method of making multiple lead voltage probe |
US20040140819A1 (en) * | 2003-01-21 | 2004-07-22 | Mctigue Michael T. | Differential voltage probe |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103117536A (en) * | 2013-01-15 | 2013-05-22 | 费新华 | Storage battery protective circuit |
Also Published As
Publication number | Publication date |
---|---|
DE202007018748U1 (en) | 2009-04-02 |
DE202007018748U8 (en) | 2009-08-13 |
WO2007145728A3 (en) | 2008-05-02 |
DE112007001435T5 (en) | 2009-05-20 |
JP2009540331A (en) | 2009-11-19 |
JP4870211B2 (en) | 2012-02-08 |
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