WO2007145843B1 - Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control - Google Patents

Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control

Info

Publication number
WO2007145843B1
WO2007145843B1 PCT/US2007/012884 US2007012884W WO2007145843B1 WO 2007145843 B1 WO2007145843 B1 WO 2007145843B1 US 2007012884 W US2007012884 W US 2007012884W WO 2007145843 B1 WO2007145843 B1 WO 2007145843B1
Authority
WO
WIPO (PCT)
Prior art keywords
node
circuit
original
bidirectional buffer
forward signal
Prior art date
Application number
PCT/US2007/012884
Other languages
French (fr)
Other versions
WO2007145843A2 (en
WO2007145843A3 (en
Inventor
Chadwick N Marak
Jeffrey C Dunnihoo
Adam Whitworth
Original Assignee
Micro Devices Corp California
Chadwick N Marak
Jeffrey C Dunnihoo
Adam Whitworth
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micro Devices Corp California, Chadwick N Marak, Jeffrey C Dunnihoo, Adam Whitworth filed Critical Micro Devices Corp California
Priority to EP07795567.2A priority Critical patent/EP2036129A4/en
Publication of WO2007145843A2 publication Critical patent/WO2007145843A2/en
Publication of WO2007145843A3 publication Critical patent/WO2007145843A3/en
Publication of WO2007145843B1 publication Critical patent/WO2007145843B1/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Bidirectional Digital Transmission (AREA)

Abstract

The present invention is directed to bidirectional buffer with slew rate control in at least one direction. The present invention is also directed to a method of bidirectionally transmitting signals with slew rate control in at least one direction.

Claims

received by the International Bureau on 14 April 2008 (14.04.2008) Originally filed claims 1-14 unchanged. Claims 15-16 added.
1. (Original) A bidirectional buffer provided on an integrated circuit that provides slew rate control for a forward signal along with external resistive and capacitive elements comprising: a first node that functions as an input node for a forward signal and an output node for a reverse signal; a second node that functions as an output node for a forward signal and an input node for a reverse signal; a signal line disposed between the first and second node, with a pass transistor disposed thereon; fA, . a first circuit that provides impedance control to the forward signal when input onto the first node, the first circuit coupled to the first node and to at least one of the resistive elements; a second circuit that provides slew rate control of the forward signal output onto the second node, the second circuit coupled to the second node and to at least another one of the resistive elements and to the capacitive element
2i,,, (Original) The bidirectional buffer according to claim 1 wherein a slew rate control inpu is not provided,
3. re SM.. (Original) The bidirectional buffer according to claim 1 wherein the first circuit includes a capacitor, a bias circuit, and a plurality of transistors that are coupled between the first node and a gate of the pass transistor.
4., : . The bidirectional buffer according to claim 3 wherein the bias circuit includes a current mirror.
5'. (Original) The bidirectional buffer according to claim 1 wherein the second circuit includes a pull-down circuit, a pull-up circuit, and a current source circuit.
6. (Original) The bidirectional buffer according to claim 5 wherein the pull-down circuit ijtfc-Udes a pull-down transistor, a first capacitor, and a plurality of resistors that are coupled to the second node.
R«b to ISR CLEAN CLAIMS SET.DOC
7. (Original) The bidirectional buffer according to claim 6 wherein the pull-up circuit (includes a pull-up transistor, a first capacitor, and a plurality of resistors that are coupled to the second node.
8, (Original) The bidirectional buffer according to claim 7 wherein the current source circuit biases the second node by a ratio of at least 5:1.
,
9. ,„ (Original) The bidirectional buffer according to claim 7 wherein a value of the current source is set by the HDMI specification.
10. b (Original) The bidirectional buffer according to claim 5 wherein the current source circuit biases the second node by a ratio of at least 5:1.
11. (Original) The bidirectional buffer according to claim 5 wherein a value of the current source is set by the HDMI specification.
12./>r> (Original) The bidirectional buffer according to claim 1 wherein the first circuit and the second circuit are substantially turned off and the pass transistor is turned on during a period when there exists the reverse signal,
13. (Original) A method of providing signal transmission through a bus on a buffer comprising the steps of: providing for a slew rate controlled forward signal through the bus on the buffer in a first direction, the slew rate controlled forward signal being provided without usage of any external control signal; and
I11. providing for a reverse signal through the bus on the buffer in a second direction, the second direction being opposite the first direction, thereby resulting in a bi-directional bus with qlew rate control in at least one direction, l,4vw ■ (Original) The method according to claim 13 wherein transitions of the forward signal are either pulled-up or pulled-down to decrease a period of the transitions.
15. (New) A method according to claim 13 or 14 and further comprising providing for impedance control of the forward signal in the first direction, wherein transitions of the forward signal are either pulled-up or pulled-down to decrease a period of the transitions.
16. (New) A method according to claim 15, wherein providing the impedance control
I ' includes controlling the gate of a pass transistor disposed in the path of the forward signal.
fep.tς ISR CLEAN CLAIMS SET.DOC
PCT/US2007/012884 2006-06-15 2007-05-31 Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control WO2007145843A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP07795567.2A EP2036129A4 (en) 2006-06-15 2007-05-31 Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/424,535 US7321241B1 (en) 2006-06-15 2006-06-15 Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control
US11/424,535 2006-06-15

Publications (3)

Publication Number Publication Date
WO2007145843A2 WO2007145843A2 (en) 2007-12-21
WO2007145843A3 WO2007145843A3 (en) 2008-04-10
WO2007145843B1 true WO2007145843B1 (en) 2008-06-05

Family

ID=38832294

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/012884 WO2007145843A2 (en) 2006-06-15 2007-05-31 Bidirectional buffer with slew rate control and method of bidirectionally transmitting signals with slew rate control

Country Status (4)

Country Link
US (1) US7321241B1 (en)
EP (1) EP2036129A4 (en)
TW (1) TWI448074B (en)
WO (1) WO2007145843A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7692450B2 (en) * 2007-12-17 2010-04-06 Intersil Americas Inc. Bi-directional buffer with level shifting
US7737727B2 (en) * 2007-12-17 2010-06-15 Intersil Americas Inc. Bi-directional buffer for open-drain or open-collector bus
US7639045B2 (en) * 2008-05-23 2009-12-29 Intersil Americas Inc. Bi-directional buffer and method for bi-directional buffering that reduce glitches due to feedback
US9183713B2 (en) 2011-02-22 2015-11-10 Kelly Research Corp. Perimeter security system

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4701720A (en) * 1986-04-28 1987-10-20 National Semiconductor Corporation Capacitive feedback to boost amplifier slew rate
US5084637A (en) * 1989-05-30 1992-01-28 International Business Machines Corp. Bidirectional level shifting interface circuit
JP3251661B2 (en) * 1991-10-15 2002-01-28 テキサス インスツルメンツ インコーポレイテツド CMOS buffer circuit with controlled slew rate
DE69422010T2 (en) * 1993-12-22 2000-07-20 Koninkl Philips Electronics Nv Phase shift amplifier and its use in a merge circuit
US5517135A (en) * 1995-07-26 1996-05-14 Xilinx, Inc. Bidirectional tristate buffer with default input
US5656950A (en) * 1995-10-26 1997-08-12 Xilinx, Inc. Interconnect lines including tri-directional buffer circuits
US6064250A (en) * 1996-07-29 2000-05-16 Townsend And Townsend And Crew Llp Various embodiments for a low power adaptive charge pump circuit
US6034547A (en) * 1996-09-04 2000-03-07 Advantage Logic, Inc. Method and apparatus for universal program controlled bus
US6066971A (en) * 1997-10-02 2000-05-23 Motorola, Inc. Integrated circuit having buffering circuitry with slew rate control
US6052325A (en) * 1998-05-22 2000-04-18 Micron Technology, Inc. Method and apparatus for translating signals
US7084666B2 (en) * 2002-10-21 2006-08-01 Viciciv Technology Programmable interconnect structures
US6903588B2 (en) * 2003-04-15 2005-06-07 Broadcom Corporation Slew rate controlled output buffer

Also Published As

Publication number Publication date
EP2036129A4 (en) 2013-10-09
EP2036129A2 (en) 2009-03-18
WO2007145843A2 (en) 2007-12-21
TWI448074B (en) 2014-08-01
US7321241B1 (en) 2008-01-22
TW200810356A (en) 2008-02-16
US20070290711A1 (en) 2007-12-20
WO2007145843A3 (en) 2008-04-10

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