WO2007146734A3 - Self aligned gate jfet structure and method - Google Patents

Self aligned gate jfet structure and method Download PDF

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Publication number
WO2007146734A3
WO2007146734A3 PCT/US2007/070589 US2007070589W WO2007146734A3 WO 2007146734 A3 WO2007146734 A3 WO 2007146734A3 US 2007070589 W US2007070589 W US 2007070589W WO 2007146734 A3 WO2007146734 A3 WO 2007146734A3
Authority
WO
WIPO (PCT)
Prior art keywords
source
drain contacts
aligned gate
polysilicon
substrate
Prior art date
Application number
PCT/US2007/070589
Other languages
French (fr)
Other versions
WO2007146734A2 (en
Inventor
Ashok Kumar Kapoor
Original Assignee
Dsm Solutions Inc
Ashok Kumar Kapoor
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dsm Solutions Inc, Ashok Kumar Kapoor filed Critical Dsm Solutions Inc
Priority to EP07798213A priority Critical patent/EP2038937A4/en
Priority to CA002647600A priority patent/CA2647600A1/en
Priority to JP2009514527A priority patent/JP2009540579A/en
Publication of WO2007146734A2 publication Critical patent/WO2007146734A2/en
Publication of WO2007146734A3 publication Critical patent/WO2007146734A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66893—Unipolar field-effect transistors with a PN junction gate, i.e. JFET
    • H01L29/66901—Unipolar field-effect transistors with a PN junction gate, i.e. JFET with a PN homojunction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or suicide) and a self-aligned gate contact made of second polysilicon which has been polished back to be flush with a top surface of a dielectric layer covering the tops of the source and drain contacts. The dielectric layer preferably has a nitride cap to act as a polish stop. In some embodiments, nitride covers the entire dielctric layer covering the source and drain contacts as well as the field oxide region defining an active area for said JFET. An embodiment with an epitaxially grown channel region formed on the surface of the substrate is also disclosed.
PCT/US2007/070589 2006-06-09 2007-06-07 Self aligned gate jfet structure and method WO2007146734A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP07798213A EP2038937A4 (en) 2006-06-09 2007-06-07 Self aligned gate jfet structure and method
CA002647600A CA2647600A1 (en) 2006-06-09 2007-06-07 Self aligned gate jfet structure and method
JP2009514527A JP2009540579A (en) 2006-06-09 2007-06-07 Self-aligned gate JFET structure and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/450,112 2006-06-09
US11/450,112 US7560755B2 (en) 2006-06-09 2006-06-09 Self aligned gate JFET structure and method

Publications (2)

Publication Number Publication Date
WO2007146734A2 WO2007146734A2 (en) 2007-12-21
WO2007146734A3 true WO2007146734A3 (en) 2008-02-21

Family

ID=38821001

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/070589 WO2007146734A2 (en) 2006-06-09 2007-06-07 Self aligned gate jfet structure and method

Country Status (8)

Country Link
US (2) US7560755B2 (en)
EP (1) EP2038937A4 (en)
JP (1) JP2009540579A (en)
KR (1) KR20090023476A (en)
CN (1) CN101467265A (en)
CA (1) CA2647600A1 (en)
TW (1) TW200810114A (en)
WO (1) WO2007146734A2 (en)

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US7560755B2 (en) * 2006-06-09 2009-07-14 Dsm Solutions, Inc. Self aligned gate JFET structure and method
US7557393B2 (en) * 2006-08-10 2009-07-07 Dsm Solutions, Inc. JFET with built in back gate in either SOI or bulk silicon
US7764137B2 (en) * 2006-09-28 2010-07-27 Suvolta, Inc. Circuit and method for generating electrical solutions with junction field effect transistors
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US20080128762A1 (en) * 2006-10-31 2008-06-05 Vora Madhukar B Junction isolated poly-silicon gate JFET
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US20080099796A1 (en) * 2006-11-01 2008-05-01 Vora Madhukar B Device with patterned semiconductor electrode structure and method of manufacture
US20080265936A1 (en) * 2007-04-27 2008-10-30 Dsm Solutions, Inc. Integrated circuit switching device, structure and method of manufacture
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US7525138B2 (en) * 2007-05-03 2009-04-28 Dsm Solutions, Inc. JFET device with improved off-state leakage current and method of fabrication
US7629812B2 (en) * 2007-08-03 2009-12-08 Dsm Solutions, Inc. Switching circuits and methods for programmable logic devices
US8035139B2 (en) * 2007-09-02 2011-10-11 Suvolta, Inc. Dynamic random access memory having junction field effect transistor cell access device
US7977714B2 (en) * 2007-10-19 2011-07-12 International Business Machines Corporation Wrapped gate junction field effect transistor
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US20090206375A1 (en) * 2008-02-19 2009-08-20 Saha Samar K Reduced Leakage Current Field-Effect Transistor Having Asymmetric Doping And Fabrication Method Therefor
US20090224291A1 (en) * 2008-03-04 2009-09-10 Dsm Solutions, Inc. Method for self aligned sharp and shallow doping depth profiles
US7710148B2 (en) * 2008-06-02 2010-05-04 Suvolta, Inc. Programmable switch circuit and method, method of manufacture, and devices and systems including the same
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US7943971B1 (en) 2008-12-17 2011-05-17 Suvolta, Inc. Junction field effect transistor (JFET) structure having top-to-bottom gate tie and method of manufacture
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US8264058B2 (en) * 2009-02-13 2012-09-11 University Of South Carolina MOS-driver compatible JFET structure with enhanced gate source characteristics
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CN103187310B (en) * 2011-12-31 2017-03-15 中芯国际集成电路制造(北京)有限公司 A kind of complementary junction field effect transistor c JFET devices and its manufacture method of post tensioned unbonded prestressed concrete
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Title
See also references of EP2038937A4 *

Also Published As

Publication number Publication date
EP2038937A2 (en) 2009-03-25
US7687335B2 (en) 2010-03-30
US20070284628A1 (en) 2007-12-13
TW200810114A (en) 2008-02-16
EP2038937A4 (en) 2010-04-28
US20090017585A1 (en) 2009-01-15
CA2647600A1 (en) 2007-12-21
WO2007146734A2 (en) 2007-12-21
CN101467265A (en) 2009-06-24
KR20090023476A (en) 2009-03-04
US7560755B2 (en) 2009-07-14
JP2009540579A (en) 2009-11-19

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