WO2007149515A3 - Floating gate memory devices and fabrication - Google Patents

Floating gate memory devices and fabrication Download PDF

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Publication number
WO2007149515A3
WO2007149515A3 PCT/US2007/014431 US2007014431W WO2007149515A3 WO 2007149515 A3 WO2007149515 A3 WO 2007149515A3 US 2007014431 W US2007014431 W US 2007014431W WO 2007149515 A3 WO2007149515 A3 WO 2007149515A3
Authority
WO
WIPO (PCT)
Prior art keywords
floating gate
fabrication
inter
transistors
memory devices
Prior art date
Application number
PCT/US2007/014431
Other languages
French (fr)
Other versions
WO2007149515A2 (en
Inventor
Seiichi Aritome
Original Assignee
Micron Technology Inc
Seiichi Aritome
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc, Seiichi Aritome filed Critical Micron Technology Inc
Priority to JP2009516566A priority Critical patent/JP5801030B2/en
Priority to CN200780022954.0A priority patent/CN101473429B/en
Priority to KR1020097001240A priority patent/KR101350632B1/en
Priority to EP07809749A priority patent/EP2036122A2/en
Publication of WO2007149515A2 publication Critical patent/WO2007149515A2/en
Publication of WO2007149515A3 publication Critical patent/WO2007149515A3/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND

Abstract

A floating gate memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another and methods of fabricating the same. Floating gate transistors are formed such that each of the floating gate transistors in the array has a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array. Methods of fabricating such structures are also provided.
PCT/US2007/014431 2006-06-21 2007-06-20 Floating gate memory devices and fabrication WO2007149515A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2009516566A JP5801030B2 (en) 2006-06-21 2007-06-20 Floating gate memory device and manufacturing
CN200780022954.0A CN101473429B (en) 2006-06-21 2007-06-20 Memory devices having reduced interference between floating gates and methods of fabricating such devices
KR1020097001240A KR101350632B1 (en) 2006-06-21 2007-06-20 Floating gate memory devices and fabrication
EP07809749A EP2036122A2 (en) 2006-06-21 2007-06-20 Memory devices having reduced interference between floating gates and methods of fabricating such devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/471,772 US7977190B2 (en) 2006-06-21 2006-06-21 Memory devices having reduced interference between floating gates and methods of fabricating such devices
US11/471,772 2006-06-21

Publications (2)

Publication Number Publication Date
WO2007149515A2 WO2007149515A2 (en) 2007-12-27
WO2007149515A3 true WO2007149515A3 (en) 2008-02-21

Family

ID=38669533

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/014431 WO2007149515A2 (en) 2006-06-21 2007-06-20 Floating gate memory devices and fabrication

Country Status (6)

Country Link
US (3) US7977190B2 (en)
EP (1) EP2036122A2 (en)
JP (1) JP5801030B2 (en)
KR (1) KR101350632B1 (en)
CN (1) CN101473429B (en)
WO (1) WO2007149515A2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7763933B2 (en) 2007-02-15 2010-07-27 Micron Technology, Inc. Transistor constructions and processing methods
US7948021B2 (en) 2007-04-27 2011-05-24 Kabushiki Kaisha Toshiba Semiconductor memory device and method of fabricating the same
US20080273410A1 (en) * 2007-05-04 2008-11-06 Jaydeb Goswami Tungsten digitlines
JP4594973B2 (en) 2007-09-26 2010-12-08 株式会社東芝 Nonvolatile semiconductor memory device
US8750040B2 (en) 2011-01-21 2014-06-10 Micron Technology, Inc. Memory devices having source lines directly coupled to body regions and methods
CN102184869B (en) * 2011-04-28 2015-07-08 上海华虹宏力半导体制造有限公司 Method for manufacturing metal oxide semiconductor (MOS) transistor isolation area and MOS transistor
CN105304549A (en) * 2014-07-29 2016-02-03 盛美半导体设备（上海）有限公司 Shallow trench isolation structure formation method
CN108292516A (en) * 2015-11-03 2018-07-17 硅存储技术公司 Metal floating boom in the nonvolatile memory integrated

Citations (5)

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US20030151084A1 (en) * 2002-02-08 2003-08-14 Samsung Electronics Co., Ltd. Cells of nonvolatile memory devices with floating gates and methods for fabricatng the same
US20040152252A1 (en) * 2003-02-04 2004-08-05 Anam Semiconductor, Inc. Method for manufacturing non-volatile memory devices
US20050067652A1 (en) * 2003-09-30 2005-03-31 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and a fabrication method thereof
US20050106813A1 (en) * 2003-11-19 2005-05-19 Lee Seong C. Method of manufacturing flash memory device
US20060060927A1 (en) * 2003-07-04 2006-03-23 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and manufacturing method for the same

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US6781895B1 (en) 1991-12-19 2004-08-24 Kabushiki Kaisha Toshiba Non-volatile semiconductor memory device and memory system using the same
JP3469362B2 (en) 1994-08-31 2003-11-25 株式会社東芝 Semiconductor storage device
US5622881A (en) * 1994-10-06 1997-04-22 International Business Machines Corporation Packing density for flash memories
JP3583579B2 (en) * 1997-06-06 2004-11-04 株式会社東芝 Nonvolatile semiconductor memory device and method of manufacturing the same
JP4237344B2 (en) * 1998-09-29 2009-03-11 株式会社東芝 Semiconductor device and manufacturing method thereof
US6228713B1 (en) * 1999-06-28 2001-05-08 Chartered Semiconductor Manufacturing Ltd. Self-aligned floating gate for memory application using shallow trench isolation
US6461915B1 (en) 1999-09-01 2002-10-08 Micron Technology, Inc. Method and structure for an improved floating gate memory cell
JP2002076272A (en) * 2000-08-23 2002-03-15 Sony Corp Method of manufacturing semiconductor device
JP3984020B2 (en) * 2000-10-30 2007-09-26 株式会社東芝 Nonvolatile semiconductor memory device
US6656852B2 (en) * 2001-12-06 2003-12-02 Texas Instruments Incorporated Method for the selective removal of high-k dielectrics
US6795326B2 (en) 2001-12-12 2004-09-21 Micron Technology, Inc. Flash array implementation with local and global bit lines
KR100537277B1 (en) * 2002-11-27 2005-12-19 주식회사 하이닉스반도체 Method of manufacturing a semiconductor device
JP3923926B2 (en) * 2003-07-04 2007-06-06 株式会社東芝 Semiconductor memory device
US6982905B2 (en) 2003-10-09 2006-01-03 Micron Technology, Inc. Method and apparatus for reading NAND flash memory array
US6996004B1 (en) 2003-11-04 2006-02-07 Advanced Micro Devices, Inc. Minimization of FG-FG coupling in flash memory
US7045419B2 (en) * 2003-12-12 2006-05-16 Macronix International Co., Ltd. Elimination of the fast-erase phenomena in flash memory
JP2005209931A (en) * 2004-01-23 2005-08-04 Renesas Technology Corp Nonvolatile semiconductor memory device and its manufacturing method
US6951790B1 (en) 2004-03-24 2005-10-04 Micron Technology, Inc. Method of forming select lines for NAND memory devices
US7332408B2 (en) * 2004-06-28 2008-02-19 Micron Technology, Inc. Isolation trenches for memory devices
JP2007096151A (en) * 2005-09-30 2007-04-12 Toshiba Corp Semiconductor storage and manufacturing method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030151084A1 (en) * 2002-02-08 2003-08-14 Samsung Electronics Co., Ltd. Cells of nonvolatile memory devices with floating gates and methods for fabricatng the same
US20040152252A1 (en) * 2003-02-04 2004-08-05 Anam Semiconductor, Inc. Method for manufacturing non-volatile memory devices
US20060060927A1 (en) * 2003-07-04 2006-03-23 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and manufacturing method for the same
US20050067652A1 (en) * 2003-09-30 2005-03-31 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory and a fabrication method thereof
US20050106813A1 (en) * 2003-11-19 2005-05-19 Lee Seong C. Method of manufacturing flash memory device

Also Published As

Publication number Publication date
US9018059B2 (en) 2015-04-28
WO2007149515A2 (en) 2007-12-27
CN101473429A (en) 2009-07-01
KR101350632B1 (en) 2014-01-10
JP2009541999A (en) 2009-11-26
JP5801030B2 (en) 2015-10-28
US20110266610A1 (en) 2011-11-03
KR20090034892A (en) 2009-04-08
US8441058B2 (en) 2013-05-14
US20070296015A1 (en) 2007-12-27
EP2036122A2 (en) 2009-03-18
CN101473429B (en) 2011-08-03
US7977190B2 (en) 2011-07-12
US20130237031A1 (en) 2013-09-12

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