WO2008002836A3 - Stacked, interconnected semiconductor packages - Google Patents

Stacked, interconnected semiconductor packages Download PDF

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Publication number
WO2008002836A3
WO2008002836A3 PCT/US2007/071881 US2007071881W WO2008002836A3 WO 2008002836 A3 WO2008002836 A3 WO 2008002836A3 US 2007071881 W US2007071881 W US 2007071881W WO 2008002836 A3 WO2008002836 A3 WO 2008002836A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor packages
stacked
interconnected semiconductor
stacked semiconductor
embodiment includes
Prior art date
Application number
PCT/US2007/071881
Other languages
French (fr)
Other versions
WO2008002836A2 (en
Inventor
Cheeman Yu
Chih-Chin Liao
Hem Takiar
Original Assignee
Sandisk Corp
Cheeman Yu
Chih-Chin Liao
Hem Takiar
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/427,695 external-priority patent/US7615409B2/en
Priority claimed from US11/427,689 external-priority patent/US7550834B2/en
Application filed by Sandisk Corp, Cheeman Yu, Chih-Chin Liao, Hem Takiar filed Critical Sandisk Corp
Publication of WO2008002836A2 publication Critical patent/WO2008002836A2/en
Publication of WO2008002836A3 publication Critical patent/WO2008002836A3/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
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    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
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    • H01L2225/1064Electrical connections provided on a side surface of one or more of the containers
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    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/1815Shape

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Memories (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.
PCT/US2007/071881 2006-06-29 2007-06-22 Stacked, interconnected semiconductor packages WO2008002836A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/427,695 2006-06-29
US11/427,695 US7615409B2 (en) 2006-06-29 2006-06-29 Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages
US11/427,689 US7550834B2 (en) 2006-06-29 2006-06-29 Stacked, interconnected semiconductor packages
US11/427,689 2006-06-29

Publications (2)

Publication Number Publication Date
WO2008002836A2 WO2008002836A2 (en) 2008-01-03
WO2008002836A3 true WO2008002836A3 (en) 2008-02-14

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ID=38710528

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/071881 WO2008002836A2 (en) 2006-06-29 2007-06-22 Stacked, interconnected semiconductor packages

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TW (1) TWI376777B (en)
WO (1) WO2008002836A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0669653A1 (en) * 1994-02-21 1995-08-30 ABB Management AG Power semiconductor module and circuit arrangement with at least two semiconductor modules
US20030042564A1 (en) * 2000-12-04 2003-03-06 Fujitsu Limited Semiconductor device having an interconnecting post formed on an interposer within a sealing resin
WO2005112117A2 (en) * 2004-05-11 2005-11-24 Infineon Technologies Ag Power semiconductor assembly

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0669653A1 (en) * 1994-02-21 1995-08-30 ABB Management AG Power semiconductor module and circuit arrangement with at least two semiconductor modules
US20030042564A1 (en) * 2000-12-04 2003-03-06 Fujitsu Limited Semiconductor device having an interconnecting post formed on an interposer within a sealing resin
WO2005112117A2 (en) * 2004-05-11 2005-11-24 Infineon Technologies Ag Power semiconductor assembly

Also Published As

Publication number Publication date
TW200807665A (en) 2008-02-01
WO2008002836A2 (en) 2008-01-03
TWI376777B (en) 2012-11-11

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